diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h index 86ab85935c4ebc39a9a813d84b62082335f590fb..55d4fd5c9607a6fc436949015275efd4761e3171 100644 --- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -27,8 +27,8 @@ #define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12) #define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (2U << 12) -#define mc_client_order_id(id, client) \ - (~MC_CLIENT_ORDER_ID_##id##_##client##_MASK | \ +#define mc_client_order_id(val, id, client) \ + ((val & ~MC_CLIENT_ORDER_ID_##id##_##client##_MASK) | \ MC_CLIENT_ORDER_ID_##id##_##client##_ORDER_ID) /******************************************************************************* diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index a59cd11ae7321bb890d4bd86f46d3116c18f4853..374797c076307e7f74324044a4959ce00a9055c9 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -577,17 +577,14 @@ static void tegra194_memctrl_reconfig_mss_clients(void) tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val); /* Set Order Id only for the clients having non zero order id */ - reg_val = MC_CLIENT_ORDER_ID_9_RESET_VAL & - mc_client_order_id(9, XUSB_HOSTW); + reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_9_RESET_VAL, 9, XUSB_HOSTW); tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val); - reg_val = MC_CLIENT_ORDER_ID_27_RESET_VAL & - mc_client_order_id(27, PCIE0W); + reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_27_RESET_VAL, 27, PCIE0W); tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val); - reg_val = MC_CLIENT_ORDER_ID_28_RESET_VAL & - mc_client_order_id(28, PCIE4W) & - mc_client_order_id(28, PCIE5W); + reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_28_RESET_VAL, 28, PCIE4W); + reg_val = mc_client_order_id(reg_val, 28, PCIE5W); tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val); /* Set VC Id only for the clients having different reset values */