Unverified Commit 9a207532 authored by Antonio Niño Díaz's avatar Antonio Niño Díaz Committed by GitHub
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Merge pull request #1726 from antonio-nino-diaz-arm/an/includes

Sanitise includes across codebase
parents 3f99f7e4 8e7b27a4
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
#ifndef IO_WIN_H #ifndef IO_WIN_H
#define IO_WIN_H #define IO_WIN_H
#include <addr_map.h> #include <drivers/marvell/addr_map.h>
int init_io_win(int ap_index); int init_io_win(int ap_index);
void iow_temp_win_insert(int ap_index, struct addr_map_win *win, int size); void iow_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
......
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
#ifndef IOB_H #ifndef IOB_H
#define IOB_H #define IOB_H
#include <addr_map.h> #include <drivers/marvell/addr_map.h>
enum target_ids_iob { enum target_ids_iob {
INTERNAL_TID = 0x0, INTERNAL_TID = 0x0,
......
...@@ -10,7 +10,8 @@ ...@@ -10,7 +10,8 @@
#ifndef CP110_SETUP_H #ifndef CP110_SETUP_H
#define CP110_SETUP_H #define CP110_SETUP_H
#include <mmio.h> #include <lib/mmio.h>
#include <mvebu_def.h> #include <mvebu_def.h>
#define MVEBU_DEVICE_ID_REG (MVEBU_CP_DFX_OFFSET + 0x40) #define MVEBU_DEVICE_ID_REG (MVEBU_CP_DFX_OFFSET + 0x40)
......
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
#ifndef A3700_CONSOLE_H #ifndef A3700_CONSOLE_H
#define A3700_CONSOLE_H #define A3700_CONSOLE_H
#include <console.h> #include <drivers/console.h>
/* MVEBU UART Registers */ /* MVEBU UART Registers */
#define UART_RX_REG 0x00 #define UART_RX_REG 0x00
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#ifndef MESON_CONSOLE_H #ifndef MESON_CONSOLE_H
#define MESON_CONSOLE_H #define MESON_CONSOLE_H
#include <console.h> #include <drivers/console.h>
#define CONSOLE_T_MESON_BASE CONSOLE_T_DRVDATA #define CONSOLE_T_MESON_BASE CONSOLE_T_DRVDATA
......
...@@ -8,7 +8,8 @@ ...@@ -8,7 +8,8 @@
#define MMC_H #define MMC_H
#include <stdint.h> #include <stdint.h>
#include <utils_def.h>
#include <lib/utils_def.h>
#define MMC_BLOCK_SIZE U(512) #define MMC_BLOCK_SIZE U(512)
#define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1)) #define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1))
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#ifndef GPT_H #ifndef GPT_H
#define GPT_H #define GPT_H
#include <partition.h> #include <drivers/partition/partition.h>
#define PARTITION_TYPE_GPT 0xee #define PARTITION_TYPE_GPT 0xee
#define GPT_HEADER_OFFSET PARTITION_BLOCK_SIZE #define GPT_HEADER_OFFSET PARTITION_BLOCK_SIZE
......
...@@ -7,9 +7,10 @@ ...@@ -7,9 +7,10 @@
#ifndef PARTITION_H #ifndef PARTITION_H
#define PARTITION_H #define PARTITION_H
#include <cassert.h>
#include <stdint.h> #include <stdint.h>
#include <lib/cassert.h>
#if !PLAT_PARTITION_MAX_ENTRIES #if !PLAT_PARTITION_MAX_ENTRIES
# define PLAT_PARTITION_MAX_ENTRIES 128 # define PLAT_PARTITION_MAX_ENTRIES 128
#endif /* PLAT_PARTITION_MAX_ENTRIES */ #endif /* PLAT_PARTITION_MAX_ENTRIES */
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#ifndef IO_MMC_H #ifndef IO_MMC_H
#define IO_MMC_H #define IO_MMC_H
#include <io_driver.h> #include <drivers/io/io_driver.h>
int register_io_dev_mmc(const io_dev_connector_t **dev_con); int register_io_dev_mmc(const io_dev_connector_t **dev_con);
......
...@@ -7,8 +7,8 @@ ...@@ -7,8 +7,8 @@
#ifndef IO_STM32IMAGE_H #ifndef IO_STM32IMAGE_H
#define IO_STM32IMAGE_H #define IO_STM32IMAGE_H
#include <io_driver.h> #include <drivers/io/io_driver.h>
#include <partition.h> #include <drivers/partition/partition.h>
#define MAX_LBA_SIZE 512 #define MAX_LBA_SIZE 512
#define MAX_PART_NAME_SIZE (EFI_NAMELEN + 1) #define MAX_PART_NAME_SIZE (EFI_NAMELEN + 1)
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#ifndef STM32_CONSOLE_H #ifndef STM32_CONSOLE_H
#define STM32_CONSOLE_H #define STM32_CONSOLE_H
#include <console.h> #include <drivers/console.h>
#define CONSOLE_T_STM32_BASE CONSOLE_T_DRVDATA #define CONSOLE_T_STM32_BASE CONSOLE_T_DRVDATA
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#ifndef STM32_GPIO_H #ifndef STM32_GPIO_H
#define STM32_GPIO_H #define STM32_GPIO_H
#include <utils_def.h> #include <lib/utils_def.h>
#define STM32_GPIOA_BANK U(0x50002000) #define STM32_GPIOA_BANK U(0x50002000)
#define STM32_GPIOZ_BANK U(0x54004000) #define STM32_GPIOZ_BANK U(0x54004000)
......
...@@ -8,7 +8,8 @@ ...@@ -8,7 +8,8 @@
#define STM32_I2C_H #define STM32_I2C_H
#include <stdint.h> #include <stdint.h>
#include <utils_def.h>
#include <lib/utils_def.h>
/* Bit definition for I2C_CR1 register */ /* Bit definition for I2C_CR1 register */
#define I2C_CR1_PE BIT(0) #define I2C_CR1_PE BIT(0)
......
...@@ -7,9 +7,10 @@ ...@@ -7,9 +7,10 @@
#ifndef STM32_SDMMC2_H #ifndef STM32_SDMMC2_H
#define STM32_SDMMC2_H #define STM32_SDMMC2_H
#include <mmc.h>
#include <stdbool.h> #include <stdbool.h>
#include <drivers/mmc.h>
struct stm32_sdmmc2_params { struct stm32_sdmmc2_params {
uintptr_t reg_base; uintptr_t reg_base;
unsigned int clk_rate; unsigned int clk_rate;
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#ifndef STM32_UART_REGS_H #ifndef STM32_UART_REGS_H
#define STM32_UART_REGS_H #define STM32_UART_REGS_H
#include <utils_def.h> #include <lib/utils_def.h>
#define USART_CR1 U(0x00) #define USART_CR1 U(0x00)
#define USART_CR2 U(0x04) #define USART_CR2 U(0x04)
......
...@@ -7,9 +7,10 @@ ...@@ -7,9 +7,10 @@
#ifndef STM32MP1_CLK_H #ifndef STM32MP1_CLK_H
#define STM32MP1_CLK_H #define STM32MP1_CLK_H
#include <arch_helpers.h>
#include <stdbool.h> #include <stdbool.h>
#include <arch_helpers.h>
int stm32mp1_clk_probe(void); int stm32mp1_clk_probe(void);
int stm32mp1_clk_init(void); int stm32mp1_clk_init(void);
bool stm32mp1_clk_is_enabled(unsigned long id); bool stm32mp1_clk_is_enabled(unsigned long id);
......
...@@ -7,9 +7,10 @@ ...@@ -7,9 +7,10 @@
#ifndef STM32MP1_CLKFUNC_H #ifndef STM32MP1_CLKFUNC_H
#define STM32MP1_CLKFUNC_H #define STM32MP1_CLKFUNC_H
#include <libfdt.h>
#include <stdbool.h> #include <stdbool.h>
#include <libfdt.h>
enum stm32mp_osc_id { enum stm32mp_osc_id {
_HSI, _HSI,
_HSE, _HSE,
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#ifndef STM32MP1_DDR_REGS_H #ifndef STM32MP1_DDR_REGS_H
#define STM32MP1_DDR_REGS_H #define STM32MP1_DDR_REGS_H
#include <utils_def.h> #include <lib/utils_def.h>
/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */ /* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
struct stm32mp1_ddrctl { struct stm32mp1_ddrctl {
......
...@@ -9,6 +9,8 @@ ...@@ -9,6 +9,8 @@
#include <stdbool.h> #include <stdbool.h>
#include <stm32mp1_def.h>
bool dt_check_pmic(void); bool dt_check_pmic(void);
int dt_pmic_enable_boot_on_regulators(void); int dt_pmic_enable_boot_on_regulators(void);
void initialize_pmic_i2c(void); void initialize_pmic_i2c(void);
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#ifndef STM32MP1_PWR_H #ifndef STM32MP1_PWR_H
#define STM32MP1_PWR_H #define STM32MP1_PWR_H
#include <utils_def.h> #include <lib/utils_def.h>
#define PWR_CR1 U(0x00) #define PWR_CR1 U(0x00)
#define PWR_CR2 U(0x08) #define PWR_CR2 U(0x08)
......
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