Merge changes from topic "amlogic-refactoring" into integration

* changes:
  amlogic: Fix includes order
  amlogic: Fix header guards
  amlogic: Fix prefixes in the SoC specific files
  amlogic: Fix prefixes in the PM code
  amlogic: Fix prefixes in the SCPI related code
  amlogic: Fix prefixes in the MHU code
  amlogic: Fix prefixes in the SIP/SVC code
  amlogic: Fix prefixes in the thermal driver
  amlogic: Fix prefixes in the private header file
  amlogic: Fix prefixes in the efuse driver
  amlogic: Fix prefixes in the platform macros file
  amlogic: Fix prefixes in the helpers file
  amlogic: Rework Makefiles
  amlogic: Move the SIP SVC code to common directory
  amlogic: Move topology file to common directory
  amlogic: Move thermal code to common directory
  amlogic: Move MHU code to common directory
  amlogic: Move efuse code to common directory
  amlogic: Move platform macros assembly file to common directory
  amlogic: Introduce unified private header file
  amlogic: Move SCPI code to common directory
  amlogic: Move the SHA256 DMA driver to common directory
  amlogic: Move assembly helpers to common directory
  amlogic: Introduce directory parameters in the makefiles
  meson: Rename platform directory to amlogic

plat/meson/gxbb/platform.mk → plat/amlogic/gxbb/platform.mk

 #
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 include lib/xlat_tables_v2/xlat_tables.mk
 
-PLAT_INCLUDES		:=	-Iplat/meson/gxbb/include
+AML_PLAT		:=	plat/amlogic
+AML_PLAT_SOC		:=	${AML_PLAT}/${PLAT}
+AML_PLAT_COMMON		:=	${AML_PLAT}/common
 
-GXBB_GIC_SOURCES	:=	drivers/arm/gic/common/gic_common.c	\
+PLAT_INCLUDES		:=	-Iinclude/drivers/amlogic/			\
+				-I${AML_PLAT_SOC}/include			\
+				-I${AML_PLAT_COMMON}/include
+
+GIC_SOURCES		:=	drivers/arm/gic/common/gic_common.c		\
 				drivers/arm/gic/v2/gicv2_main.c			\
 				drivers/arm/gic/v2/gicv2_helpers.c		\
 				plat/common/plat_gicv2.c
 
-PLAT_BL_COMMON_SOURCES	:=	drivers/meson/console/aarch64/meson_console.S \
-				plat/meson/gxbb/gxbb_common.c		\
-				plat/meson/gxbb/gxbb_topology.c		\
-				${XLAT_TABLES_LIB_SRCS}
-
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S			\
 				plat/common/plat_psci_common.c			\
-				plat/meson/gxbb/aarch64/gxbb_helpers.S	\
-				plat/meson/gxbb/gxbb_bl31_setup.c	\
-				plat/meson/gxbb/gxbb_efuse.c		\
-				plat/meson/gxbb/gxbb_mhu.c		\
-				plat/meson/gxbb/gxbb_pm.c		\
-				plat/meson/gxbb/gxbb_scpi.c		\
-				plat/meson/gxbb/gxbb_sip_svc.c		\
-				plat/meson/gxbb/gxbb_thermal.c		\
-				${GXBB_GIC_SOURCES}
+				drivers/amlogic/console/aarch64/meson_console.S	\
+				${AML_PLAT_SOC}/gxbb_bl31_setup.c		\
+				${AML_PLAT_SOC}/gxbb_pm.c			\
+				${AML_PLAT_SOC}/gxbb_common.c			\
+				${AML_PLAT_COMMON}/aarch64/aml_helpers.S	\
+				${AML_PLAT_COMMON}/aml_efuse.c			\
+				${AML_PLAT_COMMON}/aml_mhu.c			\
+				${AML_PLAT_COMMON}/aml_scpi.c			\
+				${AML_PLAT_COMMON}/aml_sip_svc.c		\
+				${AML_PLAT_COMMON}/aml_thermal.c		\
+				${AML_PLAT_COMMON}/aml_topology.c		\
+				${XLAT_TABLES_LIB_SRCS}				\
+				${GIC_SOURCES}
 
 # Tune compiler for Cortex-A53
 ifeq ($(notdir $(CC)),armclang)
@@ -61,9 +66,9 @@ USE_COHERENT_MEM		:= 1
 # -------------------
 
 ifneq (${RESET_TO_BL31}, 0)
-  $(error Error: gxbb needs RESET_TO_BL31=0)
+  $(error Error: ${PLAT} needs RESET_TO_BL31=0)
 endif
 
 ifeq (${ARCH},aarch32)
-  $(error Error: AArch32 not supported on gxbb)
+  $(error Error: AArch32 not supported on ${PLAT})
 endif

plat/meson/gxl/gxl_bl31_setup.c → plat/amlogic/gxl/gxl_bl31_setup.c

@@ -6,14 +6,14 @@
 
 #include <assert.h>
 #include <common/bl_common.h>
-#include <drivers/arm/gicv2.h>
 #include <common/interrupt_props.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
+#include <drivers/arm/gicv2.h>
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_mmu_helpers.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
 
-#include "gxl_private.h"
+#include "aml_private.h"
 
 /*
  * Placeholder variables for copying the arguments that have been passed to
@@ -69,7 +69,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	struct gxl_bl31_param *from_bl2;
 
 	/* Initialize the console to provide early debug support */
-	gxbb_console_init();
+	aml_console_init();
 
 	/* Check that params passed from BL2 are not NULL. */
 	from_bl2 = (struct gxl_bl31_param *) arg0;
@@ -96,21 +96,21 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 void bl31_plat_arch_setup(void)
 {
-	gxbb_setup_page_tables();
+	aml_setup_page_tables();
 
 	enable_mmu_el3(0);
 }
 
 static inline bool gxl_scp_ready(void)
 {
-	return GXBB_AO_RTI_SCP_IS_READY(mmio_read_32(GXBB_AO_RTI_SCP_STAT));
+	return AML_AO_RTI_SCP_IS_READY(mmio_read_32(AML_AO_RTI_SCP_STAT));
 }
 
 static inline void gxl_scp_boot(void)
 {
-	scpi_upload_scp_fw(bl30_image_info.image_base,
+	aml_scpi_upload_scp_fw(bl30_image_info.image_base,
 			       bl30_image_info.image_size, 0);
-	scpi_upload_scp_fw(bl301_image_info.image_base,
+	aml_scpi_upload_scp_fw(bl301_image_info.image_base,
 			       bl301_image_info.image_size, 1);
 	while (!gxl_scp_ready())
 		;
@@ -119,7 +119,7 @@ static inline void gxl_scp_boot(void)
 /*******************************************************************************
  * GICv2 driver setup information
  ******************************************************************************/
-static const interrupt_prop_t gxbb_interrupt_props[] = {
+static const interrupt_prop_t gxl_interrupt_props[] = {
 	INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
 		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
 	INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
@@ -140,23 +140,23 @@ static const interrupt_prop_t gxbb_interrupt_props[] = {
 		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
 };
 
-static const gicv2_driver_data_t gxbb_gic_data = {
-	.gicd_base = GXBB_GICD_BASE,
-	.gicc_base = GXBB_GICC_BASE,
-	.interrupt_props = gxbb_interrupt_props,
-	.interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props),
+static const gicv2_driver_data_t gxl_gic_data = {
+	.gicd_base = AML_GICD_BASE,
+	.gicc_base = AML_GICC_BASE,
+	.interrupt_props = gxl_interrupt_props,
+	.interrupt_props_num = ARRAY_SIZE(gxl_interrupt_props),
 };
 
 void bl31_platform_setup(void)
 {
-	mhu_secure_init();
+	aml_mhu_secure_init();
 
-	gicv2_driver_init(&gxbb_gic_data);
+	gicv2_driver_init(&gxl_gic_data);
 	gicv2_distif_init();
 	gicv2_pcpu_distif_init();
 	gicv2_cpuif_enable();
 
 	gxl_scp_boot();
 
-	gxbb_thermal_unknown();
+	aml_thermal_unknown();
 }

plat/meson/gxl/gxl_common.c → plat/amlogic/gxl/gxl_common.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
+#include <bl31/interrupt_mgmt.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <common/ep_info.h>
-#include <bl31/interrupt_mgmt.h>
-#include <meson_console.h>
 #include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <meson_console.h>
 #include <platform_def.h>
 #include <stdint.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
 
 /*******************************************************************************
  * Platform memory map regions
  ******************************************************************************/
-#define MAP_NSDRAM0	MAP_REGION_FLAT(GXBB_NSDRAM0_BASE,		\
-					GXBB_NSDRAM0_SIZE,		\
+#define MAP_NSDRAM0	MAP_REGION_FLAT(AML_NSDRAM0_BASE,		\
+					AML_NSDRAM0_SIZE,		\
 					MT_MEMORY | MT_RW | MT_NS)
 
-#define MAP_NSDRAM1	MAP_REGION_FLAT(GXBB_NSDRAM1_BASE,		\
-					GXBB_NSDRAM1_SIZE,		\
+#define MAP_NSDRAM1	MAP_REGION_FLAT(AML_NSDRAM1_BASE,		\
+					AML_NSDRAM1_SIZE,		\
 					MT_MEMORY | MT_RW | MT_NS)
 
-#define MAP_SEC_DEVICE0	MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE,		\
-					GXBB_SEC_DEVICE0_SIZE,		\
+#define MAP_SEC_DEVICE0	MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE,		\
+					AML_SEC_DEVICE0_SIZE,		\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
-#define MAP_SEC_DEVICE1	MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE,		\
-					GXBB_SEC_DEVICE1_SIZE,		\
+#define MAP_SEC_DEVICE1	MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE,		\
+					AML_SEC_DEVICE1_SIZE,		\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
-#define MAP_TZRAM	MAP_REGION_FLAT(GXBB_TZRAM_BASE,		\
-					GXBB_TZRAM_SIZE,		\
+#define MAP_TZRAM	MAP_REGION_FLAT(AML_TZRAM_BASE,			\
+					AML_TZRAM_SIZE,			\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
-#define MAP_SEC_DEVICE2	MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE,		\
-					GXBB_SEC_DEVICE2_SIZE,		\
+#define MAP_SEC_DEVICE2	MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE,		\
+					AML_SEC_DEVICE2_SIZE,		\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
-#define MAP_SEC_DEVICE3	MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE,		\
-					GXBB_SEC_DEVICE3_SIZE,		\
+#define MAP_SEC_DEVICE3	MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE,		\
+					AML_SEC_DEVICE3_SIZE,		\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
-static const mmap_region_t gxbb_mmap[] = {
+static const mmap_region_t gxl_mmap[] = {
 	MAP_NSDRAM0,
 	MAP_NSDRAM1,
 	MAP_SEC_DEVICE0,
@@ -79,10 +79,10 @@ static const mmap_region_t gxbb_mmap[] = {
 /*******************************************************************************
  * Function that sets up the translation tables.
  ******************************************************************************/
-void gxbb_setup_page_tables(void)
+void aml_setup_page_tables(void)
 {
 #if IMAGE_BL31
-	const mmap_region_t gxbb_bl_mmap[] = {
+	const mmap_region_t gxl_bl_mmap[] = {
 		MAP_BL31,
 		MAP_BL_CODE,
 		MAP_BL_RO_DATA,
@@ -93,9 +93,9 @@ void gxbb_setup_page_tables(void)
 	};
 #endif
 
-	mmap_add(gxbb_bl_mmap);
+	mmap_add(gxl_bl_mmap);
 
-	mmap_add(gxbb_mmap);
+	mmap_add(gxl_mmap);
 
 	init_xlat_tables();
 }
@@ -103,14 +103,14 @@ void gxbb_setup_page_tables(void)
 /*******************************************************************************
  * Function that sets up the console
  ******************************************************************************/
-static console_meson_t gxbb_console;
+static console_meson_t gxl_console;
 
-void gxbb_console_init(void)
+void aml_console_init(void)
 {
-	int rc = console_meson_register(GXBB_UART0_AO_BASE,
-					GXBB_UART0_AO_CLK_IN_HZ,
-					GXBB_UART_BAUDRATE,
-					&gxbb_console);
+	int rc = console_meson_register(AML_UART0_AO_BASE,
+					AML_UART0_AO_CLK_IN_HZ,
+					AML_UART_BAUDRATE,
+					&gxl_console);
 	if (rc == 0) {
 		/*
 		 * The crash console doesn't use the multi console API, it uses
@@ -120,7 +120,7 @@ void gxbb_console_init(void)
 		panic();
 	}
 
-	console_set_scope(&gxbb_console.console,
+	console_set_scope(&gxl_console.console,
 			  CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
 }
 
@@ -131,13 +131,13 @@ unsigned int plat_get_syscnt_freq2(void)
 {
 	uint32_t val;
 
-	val = mmio_read_32(GXBB_SYS_CPU_CFG7);
+	val = mmio_read_32(AML_SYS_CPU_CFG7);
 	val &= 0xFDFFFFFF;
-	mmio_write_32(GXBB_SYS_CPU_CFG7, val);
+	mmio_write_32(AML_SYS_CPU_CFG7, val);
 
-	val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL);
+	val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
 	val &= 0xFFFFFE00;
-	mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val);
+	mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
 
-	return GXBB_OSC24M_CLK_IN_HZ;
+	return AML_OSC24M_CLK_IN_HZ;
 }

plat/meson/gxl/gxl_def.h → plat/amlogic/gxl/gxl_def.h

@@ -4,66 +4,66 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef GXBB_DEF_H
-#define GXBB_DEF_H
+#ifndef GXL_DEF_H
+#define GXL_DEF_H
 
 #include <lib/utils_def.h>
 
 /*******************************************************************************
  * System oscillator
  ******************************************************************************/
-#define GXBB_OSC24M_CLK_IN_HZ			ULL(24000000) /* 24 MHz */
+#define AML_OSC24M_CLK_IN_HZ			ULL(24000000) /* 24 MHz */
 
 /*******************************************************************************
  * Memory regions
  ******************************************************************************/
-#define GXBB_NSDRAM0_BASE			UL(0x01000000)
-#define GXBB_NSDRAM0_SIZE			UL(0x0F000000)
+#define AML_NSDRAM0_BASE			UL(0x01000000)
+#define AML_NSDRAM0_SIZE			UL(0x0F000000)
 
-#define GXBB_NSDRAM1_BASE			UL(0x10000000)
-#define GXBB_NSDRAM1_SIZE			UL(0x00100000)
+#define AML_NSDRAM1_BASE			UL(0x10000000)
+#define AML_NSDRAM1_SIZE			UL(0x00100000)
 
 #define BL31_BASE				UL(0x05100000)
 #define BL31_SIZE				UL(0x000C0000)
 #define BL31_LIMIT				(BL31_BASE + BL31_SIZE)
 
 /* Shared memory used for SMC services */
-#define GXBB_SHARE_MEM_INPUT_BASE		UL(0x050FE000)
-#define GXBB_SHARE_MEM_OUTPUT_BASE		UL(0x050FF000)
+#define AML_SHARE_MEM_INPUT_BASE		UL(0x050FE000)
+#define AML_SHARE_MEM_OUTPUT_BASE		UL(0x050FF000)
 
-#define GXBB_SEC_DEVICE0_BASE			UL(0xC0000000)
-#define GXBB_SEC_DEVICE0_SIZE			UL(0x09000000)
+#define AML_SEC_DEVICE0_BASE			UL(0xC0000000)
+#define AML_SEC_DEVICE0_SIZE			UL(0x09000000)
 
-#define GXBB_SEC_DEVICE1_BASE			UL(0xD0040000)
-#define GXBB_SEC_DEVICE1_SIZE			UL(0x00008000)
+#define AML_SEC_DEVICE1_BASE			UL(0xD0040000)
+#define AML_SEC_DEVICE1_SIZE			UL(0x00008000)
 
-#define GXBB_TZRAM_BASE				UL(0xD9000000)
-#define GXBB_TZRAM_SIZE				UL(0x00014000)
+#define AML_TZRAM_BASE				UL(0xD9000000)
+#define AML_TZRAM_SIZE				UL(0x00014000)
 /* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
 
 /* Mailboxes */
-#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD	UL(0xD9013800)
-#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD	UL(0xD9013A00)
-#define GXBB_PSCI_MAILBOX_BASE			UL(0xD9013F00)
+#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD	UL(0xD9013800)
+#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD	UL(0xD9013A00)
+#define AML_PSCI_MAILBOX_BASE			UL(0xD9013F00)
 
 // * [	 1K]	0xD901_3800 - 0xD901_3BFF	Secure Mailbox (3)
 // * [	 1K]	0xD901_3400 - 0xD901_37FF	High Mailbox (2) *
 // * [	 1K]	0xD901_3000 - 0xD901_33FF	High Mailbox (1) *
 
-#define GXBB_TZROM_BASE				UL(0xD9040000)
-#define GXBB_TZROM_SIZE				UL(0x00010000)
+#define AML_TZROM_BASE				UL(0xD9040000)
+#define AML_TZROM_SIZE				UL(0x00010000)
 
-#define GXBB_SEC_DEVICE2_BASE			UL(0xDA000000)
-#define GXBB_SEC_DEVICE2_SIZE			UL(0x00200000)
+#define AML_SEC_DEVICE2_BASE			UL(0xDA000000)
+#define AML_SEC_DEVICE2_SIZE			UL(0x00200000)
 
-#define GXBB_SEC_DEVICE3_BASE			UL(0xDA800000)
-#define GXBB_SEC_DEVICE3_SIZE			UL(0x00200000)
+#define AML_SEC_DEVICE3_BASE			UL(0xDA800000)
+#define AML_SEC_DEVICE3_SIZE			UL(0x00200000)
 
 /*******************************************************************************
  * GIC-400 and interrupt handling related constants
  ******************************************************************************/
-#define GXBB_GICD_BASE				UL(0xC4301000)
-#define GXBB_GICC_BASE				UL(0xC4302000)
+#define AML_GICD_BASE				UL(0xC4301000)
+#define AML_GICC_BASE				UL(0xC4302000)
 
 #define IRQ_SEC_PHY_TIMER			29
 
@@ -79,50 +79,50 @@
 /*******************************************************************************
  * UART definitions
  ******************************************************************************/
-#define GXBB_UART0_AO_BASE			UL(0xC81004C0)
-#define GXBB_UART0_AO_CLK_IN_HZ			GXBB_OSC24M_CLK_IN_HZ
-#define GXBB_UART_BAUDRATE			U(115200)
+#define AML_UART0_AO_BASE			UL(0xC81004C0)
+#define AML_UART0_AO_CLK_IN_HZ			AML_OSC24M_CLK_IN_HZ
+#define AML_UART_BAUDRATE			U(115200)
 
 /*******************************************************************************
  * Memory-mapped I/O Registers
  ******************************************************************************/
-#define GXBB_AO_TIMESTAMP_CNTL			UL(0xC81000B4)
+#define AML_AO_TIMESTAMP_CNTL			UL(0xC81000B4)
 
-#define GXBB_SYS_CPU_CFG7			UL(0xC8834664)
+#define AML_SYS_CPU_CFG7			UL(0xC8834664)
 
-#define GXBB_AO_RTI_STATUS_REG3			UL(0xDA10001C)
-#define GXBB_AO_RTI_SCP_STAT			UL(0xDA10023C)
-#define GXBB_AO_RTI_SCP_READY_OFF		U(0x14)
-#define GXBB_A0_RTI_SCP_READY_MASK		U(3)
-#define GXBB_AO_RTI_SCP_IS_READY(v)		\
-	((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \
-	  GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK)
+#define AML_AO_RTI_STATUS_REG3			UL(0xDA10001C)
+#define AML_AO_RTI_SCP_STAT			UL(0xDA10023C)
+#define AML_AO_RTI_SCP_READY_OFF		U(0x14)
+#define AML_A0_RTI_SCP_READY_MASK		U(3)
+#define AML_AO_RTI_SCP_IS_READY(v)		\
+	((((v) >> AML_AO_RTI_SCP_READY_OFF) & \
+	  AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK)
 
-#define GXBB_HIU_MAILBOX_SET_0			UL(0xDA83C404)
-#define GXBB_HIU_MAILBOX_STAT_0			UL(0xDA83C408)
-#define GXBB_HIU_MAILBOX_CLR_0			UL(0xDA83C40C)
-#define GXBB_HIU_MAILBOX_SET_3			UL(0xDA83C428)
-#define GXBB_HIU_MAILBOX_STAT_3			UL(0xDA83C42C)
-#define GXBB_HIU_MAILBOX_CLR_3			UL(0xDA83C430)
+#define AML_HIU_MAILBOX_SET_0			UL(0xDA83C404)
+#define AML_HIU_MAILBOX_STAT_0			UL(0xDA83C408)
+#define AML_HIU_MAILBOX_CLR_0			UL(0xDA83C40C)
+#define AML_HIU_MAILBOX_SET_3			UL(0xDA83C428)
+#define AML_HIU_MAILBOX_STAT_3			UL(0xDA83C42C)
+#define AML_HIU_MAILBOX_CLR_3			UL(0xDA83C430)
 
 /*******************************************************************************
  * System Monitor Call IDs and arguments
  ******************************************************************************/
-#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE	U(0x82000020)
-#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE	U(0x82000021)
+#define AML_SM_GET_SHARE_MEM_INPUT_BASE		U(0x82000020)
+#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE	U(0x82000021)
 
-#define GXBB_SM_EFUSE_READ			U(0x82000030)
-#define GXBB_SM_EFUSE_USER_MAX			U(0x82000033)
+#define AML_SM_EFUSE_READ			U(0x82000030)
+#define AML_SM_EFUSE_USER_MAX			U(0x82000033)
 
-#define GXBB_SM_JTAG_ON				U(0x82000040)
-#define GXBB_SM_JTAG_OFF			U(0x82000041)
+#define AML_SM_JTAG_ON				U(0x82000040)
+#define AML_SM_JTAG_OFF				U(0x82000041)
 
-#define GXBB_JTAG_STATE_ON			U(0)
-#define GXBB_JTAG_STATE_OFF			U(1)
+#define AML_JTAG_STATE_ON			U(0)
+#define AML_JTAG_STATE_OFF			U(1)
 
-#define GXBB_JTAG_M3_AO				U(0)
-#define GXBB_JTAG_M3_EE				U(1)
-#define GXBB_JTAG_A53_AO			U(2)
-#define GXBB_JTAG_A53_EE			U(3)
+#define AML_JTAG_M3_AO				U(0)
+#define AML_JTAG_M3_EE				U(1)
+#define AML_JTAG_A53_AO				U(2)
+#define AML_JTAG_A53_EE				U(3)
 
-#endif /* GXBB_DEF_H */
+#endif /* GXL_DEF_H */

plat/meson/gxl/gxl_pm.c → plat/amlogic/gxl/gxl_pm.c

@@ -6,16 +6,16 @@
 
 #include <arch_helpers.h>
 #include <assert.h>
-#include <drivers/console.h>
 #include <common/debug.h>
-#include <errno.h>
 #include <drivers/arm/gicv2.h>
+#include <drivers/console.h>
+#include <errno.h>
 #include <lib/mmio.h>
+#include <lib/psci/psci.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
-#include <lib/psci/psci.h>
 
-#include "gxl_private.h"
+#include "aml_private.h"
 
 #define SCPI_POWER_ON		0
 #define SCPI_POWER_RETENTION	1
@@ -24,31 +24,31 @@
 #define SCPI_SYSTEM_SHUTDOWN	0
 #define SCPI_SYSTEM_REBOOT	1
 
-static uintptr_t gxbb_sec_entrypoint;
-static volatile uint32_t gxbb_cpu0_go;
+static uintptr_t gxl_sec_entrypoint;
+static volatile uint32_t gxl_cpu0_go;
 
 static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(mpidr);
-	uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
+	unsigned int core = plat_calc_core_pos(mpidr);
+	uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4);
 
 	mmio_write_64(cpu_mailbox_addr, value);
 }
 
 static void gxl_pm_reset(u_register_t mpidr)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(mpidr);
-	uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8;
+	unsigned int core = plat_calc_core_pos(mpidr);
+	uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8;
 
 	mmio_write_32(cpu_mailbox_addr, 0);
 }
 
-static void __dead2 gxbb_system_reset(void)
+static void __dead2 gxl_system_reset(void)
 {
 	INFO("BL31: PSCI_SYSTEM_RESET\n");
 
 	u_register_t mpidr = read_mpidr_el1();
-	uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3);
+	uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3);
 	int ret;
 
 	NOTICE("BL31: Reboot reason: 0x%x\n", status);
@@ -57,9 +57,9 @@ static void __dead2 gxbb_system_reset(void)
 
 	console_flush();
 
-	mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status);
+	mmio_write_32(AML_AO_RTI_STATUS_REG3, status);
 
-	ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
+	ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
 
 	if (ret != 0) {
 		ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret);
@@ -74,14 +74,14 @@ static void __dead2 gxbb_system_reset(void)
 	panic();
 }
 
-static void __dead2 gxbb_system_off(void)
+static void __dead2 gxl_system_off(void)
 {
 	INFO("BL31: PSCI_SYSTEM_OFF\n");
 
 	u_register_t mpidr = read_mpidr_el1();
 	int ret;
 
-	ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
+	ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
 
 	if (ret != 0) {
 		ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret);
@@ -97,17 +97,17 @@ static void __dead2 gxbb_system_off(void)
 	panic();
 }
 
-static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
+static int32_t gxl_pwr_domain_on(u_register_t mpidr)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+	unsigned int core = plat_calc_core_pos(mpidr);
 
 	/* CPU0 can't be turned OFF, emulate it with a WFE loop */
-	if (core == GXBB_PRIMARY_CPU) {
+	if (core == AML_PRIMARY_CPU) {
 		VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
 
-		gxbb_cpu0_go = 1;
-		flush_dcache_range((uintptr_t)&gxbb_cpu0_go,
-				sizeof(gxbb_cpu0_go));
+		gxl_cpu0_go = 1;
+		flush_dcache_range((uintptr_t)&gxl_cpu0_go,
+				sizeof(gxl_cpu0_go));
 		dsb();
 		isb();
 
@@ -116,8 +116,8 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
 		return PSCI_E_SUCCESS;
 	}
 
-	gxl_pm_set_reset_addr(mpidr, gxbb_sec_entrypoint);
-	scpi_set_css_power_state(mpidr,
+	gxl_pm_set_reset_addr(mpidr, gxl_sec_entrypoint);
+	aml_scpi_set_css_power_state(mpidr,
 				     SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
 	dmbsy();
 	sev();
@@ -125,17 +125,17 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
 	return PSCI_E_SUCCESS;
 }
 
-static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
+static void gxl_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+	unsigned int core = plat_calc_core_pos(read_mpidr_el1());
 
 	assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
 					PLAT_LOCAL_STATE_OFF);
 
-	if (core == GXBB_PRIMARY_CPU) {
-		gxbb_cpu0_go = 0;
-		flush_dcache_range((uintptr_t)&gxbb_cpu0_go,
-				sizeof(gxbb_cpu0_go));
+	if (core == AML_PRIMARY_CPU) {
+		gxl_cpu0_go = 0;
+		flush_dcache_range((uintptr_t)&gxl_cpu0_go,
+				sizeof(gxl_cpu0_go));
 		dsb();
 		isb();
 	}
@@ -144,32 +144,32 @@ static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
 	gicv2_cpuif_enable();
 }
 
-static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
+static void gxl_pwr_domain_off(const psci_power_state_t *target_state)
 {
 	u_register_t mpidr = read_mpidr_el1();
-	unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+	unsigned int core = plat_calc_core_pos(mpidr);
 
 	gicv2_cpuif_disable();
 
 	/* CPU0 can't be turned OFF, emulate it with a WFE loop */
-	if (core == GXBB_PRIMARY_CPU)
+	if (core == AML_PRIMARY_CPU)
 		return;
 
-	scpi_set_css_power_state(mpidr,
+	aml_scpi_set_css_power_state(mpidr,
 				     SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON);
 }
 
-static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
+static void __dead2 gxl_pwr_domain_pwr_down_wfi(const psci_power_state_t
 						 *target_state)
 {
 	u_register_t mpidr = read_mpidr_el1();
-	unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+	unsigned int core = plat_calc_core_pos(mpidr);
 
 	/* CPU0 can't be turned OFF, emulate it with a WFE loop */
-	if (core == GXBB_PRIMARY_CPU) {
+	if (core == AML_PRIMARY_CPU) {
 		VERBOSE("BL31: CPU0 entering wait loop...\n");
 
-		while (gxbb_cpu0_go == 0)
+		while (gxl_cpu0_go == 0)
 			wfe();
 
 		VERBOSE("BL31: CPU0 resumed.\n");
@@ -181,7 +181,7 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
 		 * In order to avoid an assert, mmu has to be disabled.
 		 */
 		disable_mmu_el3();
-		((void(*)(void))gxbb_sec_entrypoint)();
+		((void(*)(void))gxl_sec_entrypoint)();
 	}
 
 	dsbsy();
@@ -195,20 +195,20 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
 /*******************************************************************************
  * Platform handlers and setup function.
  ******************************************************************************/
-static const plat_psci_ops_t gxbb_ops = {
-	.pwr_domain_on			= gxbb_pwr_domain_on,
-	.pwr_domain_on_finish		= gxbb_pwr_domain_on_finish,
-	.pwr_domain_off			= gxbb_pwr_domain_off,
-	.pwr_domain_pwr_down_wfi	= gxbb_pwr_domain_pwr_down_wfi,
-	.system_off			= gxbb_system_off,
-	.system_reset			= gxbb_system_reset,
+static const plat_psci_ops_t gxl_ops = {
+	.pwr_domain_on			= gxl_pwr_domain_on,
+	.pwr_domain_on_finish		= gxl_pwr_domain_on_finish,
+	.pwr_domain_off			= gxl_pwr_domain_off,
+	.pwr_domain_pwr_down_wfi	= gxl_pwr_domain_pwr_down_wfi,
+	.system_off			= gxl_system_off,
+	.system_reset			= gxl_system_reset,
 };
 
 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
 			const plat_psci_ops_t **psci_ops)
 {
-	gxbb_sec_entrypoint = sec_entrypoint;
-	*psci_ops = &gxbb_ops;
-	gxbb_cpu0_go = 0;
+	gxl_sec_entrypoint = sec_entrypoint;
+	*psci_ops = &gxl_ops;
+	gxl_cpu0_go = 0;
 	return 0;
 }

plat/meson/gxl/include/platform_def.h → plat/amlogic/gxl/include/platform_def.h

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,9 +15,6 @@
 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
 #define PLATFORM_LINKER_ARCH		aarch64
 
-/* Special value used to verify platform parameters from BL2 to BL31 */
-#define GXBB_BL31_PLAT_PARAM_VAL	ULL(0x0F1E2D3C4B5A6978)
-
 #define PLATFORM_STACK_SIZE		UL(0x1000)
 
 #define PLATFORM_MAX_CPUS_PER_CLUSTER	U(4)
@@ -25,7 +22,7 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
 
-#define GXBB_PRIMARY_CPU		U(0)
+#define AML_PRIMARY_CPU			U(0)
 
 #define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \

plat/meson/gxl/platform.mk → plat/amlogic/gxl/platform.mk

 #
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 include lib/xlat_tables_v2/xlat_tables.mk
 
-DOIMAGEPATH		?=	tools/meson
+AML_PLAT		:=	plat/amlogic
+AML_PLAT_SOC		:=	${AML_PLAT}/${PLAT}
+AML_PLAT_COMMON		:=	${AML_PLAT}/common
+
+DOIMAGEPATH		?=	tools/amlogic
 DOIMAGETOOL		?=	${DOIMAGEPATH}/doimage
 
-PLAT_INCLUDES		:=	-Iinclude/drivers/meson/		\
-				-Iinclude/drivers/meson/gxl		\
-				-Iplat/meson/gxl/include
+PLAT_INCLUDES		:=	-Iinclude/drivers/amlogic/			\
+				-I${AML_PLAT_SOC}/include			\
+				-I${AML_PLAT_COMMON}/include
 
-GXBB_GIC_SOURCES	:=	drivers/arm/gic/common/gic_common.c	\
+GIC_SOURCES		:=	drivers/arm/gic/common/gic_common.c		\
 				drivers/arm/gic/v2/gicv2_main.c			\
 				drivers/arm/gic/v2/gicv2_helpers.c		\
 				plat/common/plat_gicv2.c
 
-PLAT_BL_COMMON_SOURCES	:=	drivers/meson/console/aarch64/meson_console.S \
-				plat/meson/gxl/gxl_common.c		\
-				plat/meson/gxl/gxl_topology.c		\
-				${XLAT_TABLES_LIB_SRCS}
-
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S			\
 				plat/common/plat_psci_common.c			\
-				plat/meson/gxl/aarch64/gxl_helpers.S	\
-				plat/meson/gxl/gxl_bl31_setup.c		\
-				plat/meson/gxl/gxl_efuse.c		\
-				plat/meson/gxl/gxl_mhu.c		\
-				plat/meson/gxl/gxl_pm.c			\
-				plat/meson/gxl/gxl_scpi.c		\
-				plat/meson/gxl/gxl_sip_svc.c		\
-				plat/meson/gxl/gxl_thermal.c		\
-				drivers/meson/gxl/crypto/sha_dma.c	\
-				${GXBB_GIC_SOURCES}
+				drivers/amlogic/console/aarch64/meson_console.S	\
+				${AML_PLAT_SOC}/gxl_bl31_setup.c		\
+				${AML_PLAT_SOC}/gxl_pm.c			\
+				${AML_PLAT_SOC}/gxl_common.c			\
+				${AML_PLAT_COMMON}/aarch64/aml_helpers.S	\
+				${AML_PLAT_COMMON}/aml_efuse.c			\
+				${AML_PLAT_COMMON}/aml_mhu.c			\
+				${AML_PLAT_COMMON}/aml_scpi.c			\
+				${AML_PLAT_COMMON}/aml_sip_svc.c		\
+				${AML_PLAT_COMMON}/aml_thermal.c		\
+				${AML_PLAT_COMMON}/aml_topology.c		\
+				drivers/amlogic/crypto/sha_dma.c		\
+				${XLAT_TABLES_LIB_SRCS}				\
+				${GIC_SOURCES}
 
 # Tune compiler for Cortex-A53
 ifeq ($(notdir $(CC)),armclang)
@@ -66,11 +69,11 @@ USE_COHERENT_MEM		:= 1
 # -------------------
 
 ifneq (${RESET_TO_BL31}, 0)
-  $(error Error: gxl needs RESET_TO_BL31=0)
+  $(error Error: ${PLAT} needs RESET_TO_BL31=0)
 endif
 
 ifeq (${ARCH},aarch32)
-  $(error Error: AArch32 not supported on gxl)
+  $(error Error: AArch32 not supported on ${PLAT})
 endif
 
 all: ${BUILD_PLAT}/bl31.img

plat/meson/gxbb/gxbb_efuse.c

-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include "gxbb_private.h"
-
-#define EFUSE_BASE	0x140
-#define EFUSE_SIZE	0xC0
-
-uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size)
-{
-	if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE)
-		return 0;
-
-	return scpi_efuse_read(dst, offset + EFUSE_BASE, size);
-}
-
-uint64_t gxbb_efuse_user_max(void)
-{
-	return EFUSE_SIZE;
-}

plat/meson/gxbb/gxbb_mhu.c

-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <lib/bakery_lock.h>
-#include <lib/mmio.h>
-
-static DEFINE_BAKERY_LOCK(mhu_lock);
-
-void mhu_secure_message_start(void)
-{
-	bakery_lock_get(&mhu_lock);
-
-	while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
-		;
-}
-
-void mhu_secure_message_send(uint32_t msg)
-{
-	mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg);
-
-	while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
-		;
-}
-
-uint32_t mhu_secure_message_wait(void)
-{
-	uint32_t val;
-
-	do {
-		val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0);
-	} while (val == 0);
-
-	return val;
-}
-
-void mhu_secure_message_end(void)
-{
-	mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF);
-
-	bakery_lock_release(&mhu_lock);
-}
-
-void mhu_secure_init(void)
-{
-	bakery_lock_init(&mhu_lock);
-
-	mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF);
-}

plat/meson/gxbb/gxbb_private.h

-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef GXBB_PRIVATE_H
-#define GXBB_PRIVATE_H
-
-#include <stdint.h>
-
-/* Utility functions */
-unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
-void gxbb_console_init(void);
-void gxbb_setup_page_tables(void);
-
-/* MHU functions */
-void mhu_secure_message_start(void);
-void mhu_secure_message_send(uint32_t msg);
-uint32_t mhu_secure_message_wait(void);
-void mhu_secure_message_end(void);
-void mhu_secure_init(void);
-
-/* SCPI functions */
-void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
-			      uint32_t cluster_state, uint32_t css_state);
-uint32_t scpi_sys_power_state(uint64_t system_state);
-void scpi_jtag_set_state(uint32_t state, uint8_t select);
-uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size);
-void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
-			  uint32_t arg2, uint32_t arg3);
-
-/* Peripherals */
-void gxbb_thermal_unknown(void);
-uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size);
-uint64_t gxbb_efuse_user_max(void);
-
-#endif /* GXBB_PRIVATE_H */

plat/meson/gxbb/gxbb_scpi.c

-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <string.h>
-
-#include <platform_def.h>
-
-#include <lib/mmio.h>
-#include <plat/common/platform.h>
-
-#include "gxbb_private.h"
-
-#define SIZE_SHIFT	20
-#define SIZE_MASK	0x1FF
-
-/*
- * Note: The Amlogic SCP firmware uses the legacy SCPI protocol.
- */
-#define SCPI_CMD_SET_CSS_POWER_STATE	0x04
-#define SCPI_CMD_SET_SYS_POWER_STATE	0x08
-
-#define SCPI_CMD_JTAG_SET_STATE		0xC0
-#define SCPI_CMD_EFUSE_READ		0xC2
-
-static inline uint32_t scpi_cmd(uint32_t command, uint32_t size)
-{
-	return command | (size << SIZE_SHIFT);
-}
-
-void scpi_secure_message_send(uint32_t command, uint32_t size)
-{
-	mhu_secure_message_send(scpi_cmd(command, size));
-}
-
-uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out)
-{
-	uint32_t response = mhu_secure_message_wait();
-
-	size_t size = (response >> SIZE_SHIFT) & SIZE_MASK;
-
-	response &= ~(SIZE_MASK << SIZE_SHIFT);
-
-	if (size_out != NULL)
-		*size_out = size;
-
-	if (message_out != NULL)
-		*message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD;
-
-	return response;
-}
-
-void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
-			      uint32_t cluster_state, uint32_t css_state)
-{
-	uint32_t state = (mpidr & 0x0F) | /* CPU ID */
-			 ((mpidr & 0xF00) >> 4) | /* Cluster ID */
-			 (cpu_state << 8) |
-			 (cluster_state << 12) |
-			 (css_state << 16);
-
-	mhu_secure_message_start();
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state);
-	mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4));
-	mhu_secure_message_wait();
-	mhu_secure_message_end();
-}
-
-uint32_t scpi_sys_power_state(uint64_t system_state)
-{
-	uint32_t *response;
-	size_t size;
-
-	mhu_secure_message_start();
-	mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state);
-	mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1));
-	scpi_secure_message_receive((void *)&response, &size);
-	mhu_secure_message_end();
-
-	return *response;
-}
-
-void scpi_jtag_set_state(uint32_t state, uint8_t select)
-{
-	assert(state <= GXBB_JTAG_STATE_OFF);
-
-	if (select > GXBB_JTAG_A53_EE) {
-		WARN("BL31: Invalid JTAG select (0x%x).\n", select);
-		return;
-	}
-
-	mhu_secure_message_start();
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD,
-		      (state << 8) | (uint32_t)select);
-	mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4));
-	mhu_secure_message_wait();
-	mhu_secure_message_end();
-}
-
-uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
-{
-	uint32_t *response;
-	size_t resp_size;
-
-	if (size > 0x1FC)
-		return 0;
-
-	mhu_secure_message_start();
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base);
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size);
-	mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8));
-	scpi_secure_message_receive((void *)&response, &resp_size);
-	mhu_secure_message_end();
-
-	/*
-	 * response[0] is the size of the response message.
-	 * response[1 ... N] are the contents.
-	 */
-	if (*response != 0)
-		memcpy(dst, response + 1, *response);
-
-	return *response;
-}
-
-void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
-			  uint32_t arg2, uint32_t arg3)
-{
-	mhu_secure_message_start();
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0);
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1);
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2);
-	mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3);
-	mhu_secure_message_send(scpi_cmd(0xC3, 16));
-	mhu_secure_message_wait();
-	mhu_secure_message_end();
-}

plat/meson/gxbb/gxbb_sip_svc.c

-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <lib/mmio.h>
-
-#include "gxbb_private.h"
-
-/*******************************************************************************
- * This function is responsible for handling all SiP calls
- ******************************************************************************/
-static uintptr_t gxbb_sip_handler(uint32_t smc_fid,
-				  u_register_t x1, u_register_t x2,
-				  u_register_t x3, u_register_t x4,
-				  void *cookie, void *handle,
-				  u_register_t flags)
-{
-	switch (smc_fid) {
-
-	case GXBB_SM_GET_SHARE_MEM_INPUT_BASE:
-		SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE);
-
-	case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE:
-		SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE);
-
-	case GXBB_SM_EFUSE_READ:
-	{
-		void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE;
-		uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2);
-
-		SMC_RET1(handle, ret);
-	}
-	case GXBB_SM_EFUSE_USER_MAX:
-		SMC_RET1(handle,  gxbb_efuse_user_max());
-
-	case GXBB_SM_JTAG_ON:
-		scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1);
-		SMC_RET1(handle, 0);
-
-	case GXBB_SM_JTAG_OFF:
-		scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1);
-		SMC_RET1(handle, 0);
-
-	default:
-		ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid);
-		break;
-	}
-
-	SMC_RET1(handle, SMC_UNK);
-}
-
-DECLARE_RT_SVC(
-	gxbb_sip_handler,
-
-	OEN_SIP_START,
-	OEN_SIP_END,
-	SMC_TYPE_FAST,
-	NULL,
-	gxbb_sip_handler
-);

plat/meson/gxbb/gxbb_topology.c

-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <platform_def.h>
-
-#include <arch.h>
-
-#include "gxbb_private.h"
-
-/* The power domain tree descriptor */
-static unsigned char power_domain_tree_desc[] = {
-	/* Number of root nodes */
-	PLATFORM_CLUSTER_COUNT,
-	/* Number of children for the first node */
-	PLATFORM_CLUSTER0_CORE_COUNT
-};
-
-/*******************************************************************************
- * This function returns the ARM default topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
-	return power_domain_tree_desc;
-}
-
-/*******************************************************************************
- * This function implements a part of the critical interface between the psci
- * generic layer and the platform that allows the former to query the platform
- * to convert an MPIDR to a unique linear index. An error code (-1) is returned
- * in case the MPIDR is invalid.
- ******************************************************************************/
-int plat_core_pos_by_mpidr(u_register_t mpidr)
-{
-	unsigned int cluster_id, cpu_id;
-
-	mpidr &= MPIDR_AFFINITY_MASK;
-	if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
-		return -1;
-
-	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
-	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
-
-	if (cluster_id >= PLATFORM_CLUSTER_COUNT)
-		return -1;
-
-	if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
-		return -1;
-
-	return plat_gxbb_calc_core_pos(mpidr);
-}

plat/meson/gxl/aarch64/gxl_helpers.S

-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <assert_macros.S>
-#include <platform_def.h>
-
-	.globl	plat_crash_console_flush
-	.globl	plat_crash_console_init
-	.globl	plat_crash_console_putc
-	.globl	platform_mem_init
-	.globl	plat_is_my_cpu_primary
-	.globl	plat_my_core_pos
-	.globl	plat_reset_handler
-	.globl	plat_gxbb_calc_core_pos
-
-	/* -----------------------------------------------------
-	 * unsigned int plat_my_core_pos(void);
-	 * -----------------------------------------------------
-	 */
-func plat_my_core_pos
-	mrs	x0, mpidr_el1
-	b	plat_gxbb_calc_core_pos
-endfunc plat_my_core_pos
-
-	/* -----------------------------------------------------
-	 *  unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
-	 * -----------------------------------------------------
-	 */
-func plat_gxbb_calc_core_pos
-	and	x0, x0, #MPIDR_CPU_MASK
-	ret
-endfunc plat_gxbb_calc_core_pos
-
-	/* -----------------------------------------------------
-	 * unsigned int plat_is_my_cpu_primary(void);
-	 * -----------------------------------------------------
-	 */
-func plat_is_my_cpu_primary
-	mrs	x0, mpidr_el1
-	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
-	cmp	x0, #GXBB_PRIMARY_CPU
-	cset	w0, eq
-	ret
-endfunc plat_is_my_cpu_primary
-
-	/* ---------------------------------------------
-	 * void platform_mem_init(void);
-	 * ---------------------------------------------
-	 */
-func platform_mem_init
-	ret
-endfunc platform_mem_init
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_init(void)
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_init
-	mov_imm	x0, GXBB_UART0_AO_BASE
-	mov_imm	x1, GXBB_UART0_AO_CLK_IN_HZ
-	mov_imm	x2, GXBB_UART_BAUDRATE
-	b	console_meson_init
-endfunc plat_crash_console_init
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_putc(int c)
-	 * Clobber list : x1, x2
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_putc
-	mov_imm	x1, GXBB_UART0_AO_BASE
-	b	console_meson_core_putc
-endfunc plat_crash_console_putc
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_flush()
-	 * Out : return -1 on error else return 0.
-	 * Clobber list : x0, x1
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_flush
-	mov_imm	x0, GXBB_UART0_AO_BASE
-	b	console_meson_core_flush
-endfunc plat_crash_console_flush
-
-	/* ---------------------------------------------
-	 * void plat_reset_handler(void);
-	 * ---------------------------------------------
-	 */
-func plat_reset_handler
-	ret
-endfunc plat_reset_handler

plat/meson/gxl/gxl_private.h

-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef GXBB_PRIVATE_H
-#define GXBB_PRIVATE_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-/* Utility functions */
-unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
-void gxbb_console_init(void);
-void gxbb_setup_page_tables(void);
-
-/* MHU functions */
-void mhu_secure_message_start(void);
-void mhu_secure_message_send(uint32_t msg);
-uint32_t mhu_secure_message_wait(void);
-void mhu_secure_message_end(void);
-void mhu_secure_init(void);
-
-/* SCPI functions */
-void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
-			      uint32_t cluster_state, uint32_t css_state);
-uint32_t scpi_sys_power_state(uint64_t system_state);
-void scpi_jtag_set_state(uint32_t state, uint8_t select);
-uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size);
-void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
-			  uint32_t arg2, uint32_t arg3);
-void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send);
-
-/* Peripherals */
-void gxbb_thermal_unknown(void);
-uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size);
-uint64_t gxbb_efuse_user_max(void);
-
-#endif /* GXBB_PRIVATE_H */

plat/meson/gxl/gxl_thermal.c

-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include "gxl_private.h"
-
-static int32_t modules_initialized = -1;
-
-/*******************************************************************************
- * Unknown commands related to something thermal-related
- ******************************************************************************/
-void gxbb_thermal_unknown(void)
-{
-	uint16_t ret;
-
-	if (modules_initialized == -1) {
-		scpi_efuse_read(&ret, 0, 2);
-		modules_initialized = ret;
-	}
-
-	scpi_unknown_thermal(10, 2,  /* thermal */
-			     13, 1); /* thermalver */
-}

plat/meson/gxl/include/plat_macros.S

-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_MACROS_S
-#define PLAT_MACROS_S
-
-#include <drivers/arm/gicv2.h>
-#include <platform_def.h>
-
-.section .rodata.gic_reg_name, "aS"
-
-gicc_regs:
-	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
-gicd_pend_reg:
-	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
-newline:
-	.asciz "\n"
-spacer:
-	.asciz ":\t\t0x"
-
-	/* ---------------------------------------------
-	 * The below required platform porting macro
-	 * prints out relevant GIC and CCI registers
-	 * whenever an unhandled exception is taken in
-	 * BL31.
-	 * Clobbers: x0 - x10, x16, x17, sp
-	 * ---------------------------------------------
-	 */
-	.macro plat_crash_print_regs
-
-	/* GICC registers */
-
-	mov_imm	x17, GXBB_GICC_BASE
-
-	adr	x6, gicc_regs
-	ldr	w8, [x17, #GICC_HPPIR]
-	ldr	w9, [x17, #GICC_AHPPIR]
-	ldr	w10, [x17, #GICC_CTLR]
-	bl	str_in_crash_buf_print
-
-	/* GICD registers */
-
-	mov_imm	x16, GXBB_GICD_BASE
-
-	add	x7, x16, #GICD_ISPENDR
-	adr	x4, gicd_pend_reg
-	bl	asm_print_str
-
-gicd_ispendr_loop:
-	sub	x4, x7, x16
-	cmp	x4, #0x280
-	b.eq	exit_print_gic_regs
-	bl	asm_print_hex
-
-	adr	x4, spacer
-	bl	asm_print_str
-
-	ldr	x4, [x7], #8
-	bl	asm_print_hex
-
-	adr	x4, newline
-	bl	asm_print_str
-	b	gicd_ispendr_loop
-exit_print_gic_regs:
-
-	.endm
-
-#endif /* PLAT_MACROS_S */