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Commit 9bc3007d authored by Manish Pandey's avatar Manish Pandey Committed by TrustedFirmware Code Review
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Merge "product/tc0: Enable Theodul DSU in TC platform" into integration

parents 96edbe03 e5da15e0
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fdts/tc0.dts
View file @ 9bc3007d
...@@ -38,6 +38,18 @@ ...@@ -38,6 +38,18 @@
core3 { core3 {
cpu = <&CPU3>; cpu = <&CPU3>;
}; };
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
}; };
}; };
...@@ -102,6 +114,42 @@ ...@@ -102,6 +114,42 @@
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
}; };
CPU4:cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x400>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU5:cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x500>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU6:cpu@600 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x600>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU7:cpu@700 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x700>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
}; };
memory@80000000 { memory@80000000 {
......
plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
View file @ 9bc3007d
...@@ -20,30 +20,27 @@ ...@@ -20,30 +20,27 @@
binary_size = <0x80000>; binary_size = <0x80000>;
}; };
chosen {
linux,initrd-start = <0>;
linux,initrd-end = <0>;
};
hypervisor { hypervisor {
compatible = "hafnium,hafnium"; compatible = "hafnium,hafnium";
vm1 { vm1 {
is_ffa_partition; is_ffa_partition;
debug_name = "cactus-primary"; debug_name = "cactus-primary";
load_address = <0xfe000000>; load_address = <0xfe000000>;
vcpu_count = <8>;
mem_size = <1048576>;
}; };
vm2 { vm2 {
is_ffa_partition; is_ffa_partition;
debug_name = "cactus-secondary"; debug_name = "cactus-secondary";
load_address = <0xfe100000>; load_address = <0xfe100000>;
vcpu_count = <4>; vcpu_count = <8>;
mem_size = <1048576>; mem_size = <1048576>;
}; };
vm3 { vm3 {
is_ffa_partition; is_ffa_partition;
debug_name = "cactus-tertiary"; debug_name = "cactus-tertiary";
load_address = <0xfe200000>; load_address = <0xfe200000>;
vcpu_count = <4>; vcpu_count = <8>;
mem_size = <1048576>; mem_size = <1048576>;
}; };
}; };
...@@ -60,9 +57,37 @@ ...@@ -60,9 +57,37 @@
}; };
/* /*
* SPM(Hafnium) requires secondary cpu nodes are declared in * SPMC (Hafnium) requires secondary cpu nodes are declared in
* descending order * descending order
*/ */
CPU7:cpu@700 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
};
CPU6:cpu@600 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x600>;
enable-method = "psci";
};
CPU5:cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
};
CPU4:cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
};
CPU3:cpu@300 { CPU3:cpu@300 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,armv8"; compatible = "arm,armv8";
......
plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
View file @ 9bc3007d
...@@ -5,13 +5,6 @@ ...@@ -5,13 +5,6 @@
*/ */
/dts-v1/; /dts-v1/;
#define AFF 00
#include "fvp-defs.dtsi"
#undef POST
#define POST \
};
/ { / {
compatible = "arm,ffa-core-manifest-1.0"; compatible = "arm,ffa-core-manifest-1.0";
#address-cells = <2>; #address-cells = <2>;
...@@ -27,21 +20,14 @@ ...@@ -27,21 +20,14 @@
binary_size = <0x80000>; binary_size = <0x80000>;
}; };
/*
* temporary: This entry is added based on v2.4 hafnium and will be
* removed when rebased to upstream master.
*/
chosen {
linux,initrd-start = <0>;
linux,initrd-end = <0>;
};
hypervisor { hypervisor {
compatible = "hafnium,hafnium"; compatible = "hafnium,hafnium";
vm1 { vm1 {
is_ffa_partition; is_ffa_partition;
debug_name = "op-tee"; debug_name = "op-tee";
load_address = <0xfd280000>; load_address = <0xfd280000>;
vcpu_count = <8>;
mem_size = <30928896>; /* 32MB TZC DRAM - SPMC region */
}; };
}; };
...@@ -49,25 +35,65 @@ ...@@ -49,25 +35,65 @@
#address-cells = <0x2>; #address-cells = <0x2>;
#size-cells = <0x0>; #size-cells = <0x0>;
CPU_0 CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
};
/* /*
* SPMC (Hafnium) requires secondary core nodes are declared * SPMC (Hafnium) requires secondary cpu nodes are declared in
* in descending order. * descending order
*/ */
CPU_3 CPU7:cpu@700 {
CPU_2 device_type = "cpu";
CPU_1 compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
}; };
/* CPU6:cpu@600 {
* temporary: This device-memory region is added based on v2.4 hafnium device_type = "cpu";
* and will be removed when rebased to upstream master. As first compatible = "arm,armv8";
* Secure Partition no longer maps device memory. reg = <0x0 0x600>;
*/ enable-method = "psci";
device-memory@21000000 { };
device_type = "device-memory";
reg = <0x0 0x21000000 0x5f000000>; CPU5:cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
};
CPU4:cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
};
CPU3:cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
};
CPU2:cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
};
CPU1:cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
};
}; };
/* 32MB of TC0_TZC_DRAM1_BASE */ /* 32MB of TC0_TZC_DRAM1_BASE */
......
plat/arm/board/tc0/include/platform_def.h
View file @ 9bc3007d
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
#include <plat/arm/soc/common/soc_css_def.h> #include <plat/arm/soc/common/soc_css_def.h>
#include <plat/common/common_def.h> #include <plat/common/common_def.h>
#define PLATFORM_CORE_COUNT 4 #define PLATFORM_CORE_COUNT 8
#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
...@@ -202,7 +202,7 @@ ...@@ -202,7 +202,7 @@
#define PLAT_ARM_SCMI_CHANNEL_COUNT 1 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1
#define PLAT_ARM_CLUSTER_COUNT U(1) #define PLAT_ARM_CLUSTER_COUNT U(1)
#define PLAT_MAX_CPUS_PER_CLUSTER U(4) #define PLAT_MAX_CPUS_PER_CLUSTER U(8)
#define PLAT_MAX_PE_PER_CPU U(1) #define PLAT_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000) #define PLAT_CSS_MHU_BASE UL(0x45400000)
......
plat/arm/board/tc0/platform.mk
View file @ 9bc3007d
...@@ -43,7 +43,8 @@ TC0_BASE = plat/arm/board/tc0 ...@@ -43,7 +43,8 @@ TC0_BASE = plat/arm/board/tc0
PLAT_INCLUDES += -I${TC0_BASE}/include/ PLAT_INCLUDES += -I${TC0_BASE}/include/
TC0_CPU_SOURCES := lib/cpus/aarch64/cortex_matterhorn.S TC0_CPU_SOURCES := lib/cpus/aarch64/cortex_klein.S \
lib/cpus/aarch64/cortex_matterhorn.S
INTERCONNECT_SOURCES := ${TC0_BASE}/tc0_interconnect.c INTERCONNECT_SOURCES := ${TC0_BASE}/tc0_interconnect.c
......
plat/arm/board/tc0/tc0_topology.c
View file @ 9bc3007d
...@@ -33,6 +33,9 @@ const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { ...@@ -33,6 +33,9 @@ const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)), (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)), (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)), (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
}; };
/******************************************************************************* /*******************************************************************************
......
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