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Commit 9c7eecce authored by danh-arm's avatar danh-arm
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Merge pull request #284 from kpet/kp/tf-issues-295 

Add support to indicate size and end of assembly functions
parents cd319142 8b779620
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bl1/aarch64/bl1_entrypoint.S
View file @ 9c7eecce
...@@ -172,3 +172,4 @@ func bl1_entrypoint ...@@ -172,3 +172,4 @@ func bl1_entrypoint
bl bl1_main bl bl1_main
panic: panic:
b panic b panic
endfunc bl1_entrypoint
bl2/aarch64/bl2_entrypoint.S
View file @ 9c7eecce
...@@ -124,3 +124,4 @@ func bl2_entrypoint ...@@ -124,3 +124,4 @@ func bl2_entrypoint
bl bl2_main bl bl2_main
_panic: _panic:
b _panic b _panic
endfunc bl2_entrypoint
bl31/aarch64/bl31_entrypoint.S
View file @ 9c7eecce
...@@ -200,3 +200,4 @@ func bl31_entrypoint ...@@ -200,3 +200,4 @@ func bl31_entrypoint
bl bl31_main bl bl31_main
b el3_exit b el3_exit
endfunc bl31_entrypoint
bl31/aarch64/context.S
View file @ 9c7eecce
...@@ -117,6 +117,7 @@ func el1_sysregs_context_save ...@@ -117,6 +117,7 @@ func el1_sysregs_context_save
str x15, [x0, #CTX_FP_FPEXC32_EL2] str x15, [x0, #CTX_FP_FPEXC32_EL2]
ret ret
endfunc el1_sysregs_context_save
/* ----------------------------------------------------- /* -----------------------------------------------------
* The following function strictly follows the AArch64 * The following function strictly follows the AArch64
...@@ -205,6 +206,7 @@ func el1_sysregs_context_restore ...@@ -205,6 +206,7 @@ func el1_sysregs_context_restore
/* No explict ISB required here as ERET covers it */ /* No explict ISB required here as ERET covers it */
ret ret
endfunc el1_sysregs_context_restore
/* ----------------------------------------------------- /* -----------------------------------------------------
* The following function follows the aapcs_64 strictly * The following function follows the aapcs_64 strictly
...@@ -249,6 +251,7 @@ func fpregs_context_save ...@@ -249,6 +251,7 @@ func fpregs_context_save
str x10, [x0, #CTX_FP_FPCR] str x10, [x0, #CTX_FP_FPCR]
ret ret
endfunc fpregs_context_save
/* ----------------------------------------------------- /* -----------------------------------------------------
* The following function follows the aapcs_64 strictly * The following function follows the aapcs_64 strictly
...@@ -298,4 +301,5 @@ func fpregs_context_restore ...@@ -298,4 +301,5 @@ func fpregs_context_restore
*/ */
ret ret
endfunc fpregs_context_restore
#endif /* CTX_INCLUDE_FPREGS */ #endif /* CTX_INCLUDE_FPREGS */
bl31/aarch64/cpu_data.S
View file @ 9c7eecce
...@@ -51,6 +51,7 @@ func init_cpu_data_ptr ...@@ -51,6 +51,7 @@ func init_cpu_data_ptr
bl _cpu_data_by_mpidr bl _cpu_data_by_mpidr
msr tpidr_el3, x0 msr tpidr_el3, x0
ret x10 ret x10
endfunc init_cpu_data_ptr
/* ----------------------------------------------------------------- /* -----------------------------------------------------------------
...@@ -68,6 +69,7 @@ func _cpu_data_by_mpidr ...@@ -68,6 +69,7 @@ func _cpu_data_by_mpidr
bl platform_get_core_pos bl platform_get_core_pos
mov x30, x9 mov x30, x9
b _cpu_data_by_index b _cpu_data_by_index
endfunc _cpu_data_by_mpidr
/* ----------------------------------------------------------------- /* -----------------------------------------------------------------
...@@ -83,3 +85,4 @@ func _cpu_data_by_index ...@@ -83,3 +85,4 @@ func _cpu_data_by_index
adr x1, percpu_data adr x1, percpu_data
add x0, x1, x0, LSL #CPU_DATA_LOG2SIZE add x0, x1, x0, LSL #CPU_DATA_LOG2SIZE
ret ret
endfunc _cpu_data_by_index
bl31/aarch64/crash_reporting.S
View file @ 9c7eecce
...@@ -85,6 +85,7 @@ intr_excpt_msg: ...@@ -85,6 +85,7 @@ intr_excpt_msg:
func print_newline func print_newline
mov x0, '\n' mov x0, '\n'
b plat_crash_console_putc b plat_crash_console_putc
endfunc print_newline
/* /*
* Helper function to print from crash buf. * Helper function to print from crash buf.
...@@ -122,6 +123,7 @@ test_size_list: ...@@ -122,6 +123,7 @@ test_size_list:
exit_size_print: exit_size_print:
mov x30, sp mov x30, sp
ret ret
endfunc size_controlled_print
/* /*
* Helper function to store x8 - x15 registers to * Helper function to store x8 - x15 registers to
...@@ -140,6 +142,7 @@ func str_in_crash_buf_print ...@@ -140,6 +142,7 @@ func str_in_crash_buf_print
stp x12, x13, [x0, #REG_SIZE * 4] stp x12, x13, [x0, #REG_SIZE * 4]
stp x14, x15, [x0, #REG_SIZE * 6] stp x14, x15, [x0, #REG_SIZE * 6]
b size_controlled_print b size_controlled_print
endfunc str_in_crash_buf_print
/* ------------------------------------------------------ /* ------------------------------------------------------
* This macro calculates the offset to crash buf from * This macro calculates the offset to crash buf from
...@@ -176,6 +179,7 @@ func report_unhandled_exception ...@@ -176,6 +179,7 @@ func report_unhandled_exception
mov sp, x0 mov sp, x0
/* This call will not return */ /* This call will not return */
b do_crash_reporting b do_crash_reporting
endfunc report_unhandled_exception
/* ----------------------------------------------------- /* -----------------------------------------------------
...@@ -192,6 +196,7 @@ func report_unhandled_interrupt ...@@ -192,6 +196,7 @@ func report_unhandled_interrupt
mov sp, x0 mov sp, x0
/* This call will not return */ /* This call will not return */
b do_crash_reporting b do_crash_reporting
endfunc report_unhandled_interrupt
/* ----------------------------------------------------- /* -----------------------------------------------------
* This function allows to report a crash (if crash * This function allows to report a crash (if crash
...@@ -208,6 +213,7 @@ func el3_panic ...@@ -208,6 +213,7 @@ func el3_panic
mov sp, x0 mov sp, x0
/* This call will not return */ /* This call will not return */
b do_crash_reporting b do_crash_reporting
endfunc el3_panic
/* ------------------------------------------------------------ /* ------------------------------------------------------------
* The common crash reporting functionality. It requires x0 * The common crash reporting functionality. It requires x0
...@@ -346,13 +352,16 @@ func do_crash_reporting ...@@ -346,13 +352,16 @@ func do_crash_reporting
/* Done reporting */ /* Done reporting */
b crash_panic b crash_panic
endfunc do_crash_reporting
#else /* CRASH_REPORTING */ #else /* CRASH_REPORTING */
func report_unhandled_exception func report_unhandled_exception
report_unhandled_interrupt: report_unhandled_interrupt:
b crash_panic b crash_panic
endfunc report_unhandled_exception
#endif /* CRASH_REPORING */ #endif /* CRASH_REPORING */
func crash_panic func crash_panic
b crash_panic b crash_panic
endfunc crash_panic
\ No newline at end of file
bl31/aarch64/runtime_exceptions.S
View file @ 9c7eecce
...@@ -479,6 +479,7 @@ smc_prohibited: ...@@ -479,6 +479,7 @@ smc_prohibited:
rt_svc_fw_critical_error: rt_svc_fw_critical_error:
msr spsel, #1 /* Switch to SP_ELx */ msr spsel, #1 /* Switch to SP_ELx */
bl report_unhandled_exception bl report_unhandled_exception
endfunc smc_handler
/* ----------------------------------------------------- /* -----------------------------------------------------
* The following functions are used to saved and restore * The following functions are used to saved and restore
...@@ -503,6 +504,7 @@ func save_gp_registers ...@@ -503,6 +504,7 @@ func save_gp_registers
stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
save_x18_to_x29_sp_el0 save_x18_to_x29_sp_el0
ret ret
endfunc save_gp_registers
func restore_gp_registers_eret func restore_gp_registers_eret
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
...@@ -525,3 +527,4 @@ restore_gp_registers_callee_eret: ...@@ -525,3 +527,4 @@ restore_gp_registers_callee_eret:
msr sp_el0, x17 msr sp_el0, x17
ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
eret eret
endfunc restore_gp_registers_eret
bl32/tsp/aarch64/tsp_entrypoint.S
View file @ 9c7eecce
...@@ -149,6 +149,7 @@ func tsp_entrypoint ...@@ -149,6 +149,7 @@ func tsp_entrypoint
tsp_entrypoint_panic: tsp_entrypoint_panic:
b tsp_entrypoint_panic b tsp_entrypoint_panic
endfunc tsp_entrypoint
/* ------------------------------------------- /* -------------------------------------------
...@@ -166,6 +167,7 @@ func tsp_vector_table ...@@ -166,6 +167,7 @@ func tsp_vector_table
b tsp_fiq_entry b tsp_fiq_entry
b tsp_system_off_entry b tsp_system_off_entry
b tsp_system_reset_entry b tsp_system_reset_entry
endfunc tsp_vector_table
/*--------------------------------------------- /*---------------------------------------------
* This entrypoint is used by the TSPD when this * This entrypoint is used by the TSPD when this
...@@ -180,6 +182,7 @@ func tsp_vector_table ...@@ -180,6 +182,7 @@ func tsp_vector_table
func tsp_cpu_off_entry func tsp_cpu_off_entry
bl tsp_cpu_off_main bl tsp_cpu_off_main
restore_args_call_smc restore_args_call_smc
endfunc tsp_cpu_off_entry
/*--------------------------------------------- /*---------------------------------------------
* This entrypoint is used by the TSPD when the * This entrypoint is used by the TSPD when the
...@@ -191,6 +194,7 @@ func tsp_cpu_off_entry ...@@ -191,6 +194,7 @@ func tsp_cpu_off_entry
func tsp_system_off_entry func tsp_system_off_entry
bl tsp_system_off_main bl tsp_system_off_main
restore_args_call_smc restore_args_call_smc
endfunc tsp_system_off_entry
/*--------------------------------------------- /*---------------------------------------------
* This entrypoint is used by the TSPD when the * This entrypoint is used by the TSPD when the
...@@ -202,6 +206,7 @@ func tsp_system_off_entry ...@@ -202,6 +206,7 @@ func tsp_system_off_entry
func tsp_system_reset_entry func tsp_system_reset_entry
bl tsp_system_reset_main bl tsp_system_reset_main
restore_args_call_smc restore_args_call_smc
endfunc tsp_system_reset_entry
/*--------------------------------------------- /*---------------------------------------------
* This entrypoint is used by the TSPD when this * This entrypoint is used by the TSPD when this
...@@ -292,6 +297,7 @@ func tsp_cpu_on_entry ...@@ -292,6 +297,7 @@ func tsp_cpu_on_entry
/* Should never reach here */ /* Should never reach here */
tsp_cpu_on_entry_panic: tsp_cpu_on_entry_panic:
b tsp_cpu_on_entry_panic b tsp_cpu_on_entry_panic
endfunc tsp_cpu_on_entry
/*--------------------------------------------- /*---------------------------------------------
* This entrypoint is used by the TSPD when this * This entrypoint is used by the TSPD when this
...@@ -305,6 +311,7 @@ tsp_cpu_on_entry_panic: ...@@ -305,6 +311,7 @@ tsp_cpu_on_entry_panic:
func tsp_cpu_suspend_entry func tsp_cpu_suspend_entry
bl tsp_cpu_suspend_main bl tsp_cpu_suspend_main
restore_args_call_smc restore_args_call_smc
endfunc tsp_cpu_suspend_entry
/*--------------------------------------------- /*---------------------------------------------
* This entrypoint is used by the TSPD to pass * This entrypoint is used by the TSPD to pass
...@@ -357,6 +364,7 @@ func tsp_fiq_entry ...@@ -357,6 +364,7 @@ func tsp_fiq_entry
tsp_fiq_entry_panic: tsp_fiq_entry_panic:
b tsp_fiq_entry_panic b tsp_fiq_entry_panic
endfunc tsp_fiq_entry
/*--------------------------------------------- /*---------------------------------------------
* This entrypoint is used by the TSPD when this * This entrypoint is used by the TSPD when this
...@@ -373,6 +381,7 @@ func tsp_cpu_resume_entry ...@@ -373,6 +381,7 @@ func tsp_cpu_resume_entry
restore_args_call_smc restore_args_call_smc
tsp_cpu_resume_panic: tsp_cpu_resume_panic:
b tsp_cpu_resume_panic b tsp_cpu_resume_panic
endfunc tsp_cpu_resume_entry
/*--------------------------------------------- /*---------------------------------------------
* This entrypoint is used by the TSPD to ask * This entrypoint is used by the TSPD to ask
...@@ -384,6 +393,7 @@ func tsp_fast_smc_entry ...@@ -384,6 +393,7 @@ func tsp_fast_smc_entry
restore_args_call_smc restore_args_call_smc
tsp_fast_smc_entry_panic: tsp_fast_smc_entry_panic:
b tsp_fast_smc_entry_panic b tsp_fast_smc_entry_panic
endfunc tsp_fast_smc_entry
/*--------------------------------------------- /*---------------------------------------------
* This entrypoint is used by the TSPD to ask * This entrypoint is used by the TSPD to ask
...@@ -399,3 +409,4 @@ func tsp_std_smc_entry ...@@ -399,3 +409,4 @@ func tsp_std_smc_entry
restore_args_call_smc restore_args_call_smc
tsp_std_smc_entry_panic: tsp_std_smc_entry_panic:
b tsp_std_smc_entry_panic b tsp_std_smc_entry_panic
endfunc tsp_std_smc_entry
bl32/tsp/aarch64/tsp_request.S
View file @ 9c7eecce
...@@ -56,6 +56,7 @@ func tsp_get_magic ...@@ -56,6 +56,7 @@ func tsp_get_magic
stp x0, x1, [x4, #0] stp x0, x1, [x4, #0]
ret ret
endfunc tsp_get_magic
.align 2 .align 2
_tsp_fid_get_magic: _tsp_fid_get_magic:
......
common/aarch64/debug.S
View file @ 9c7eecce
...@@ -98,6 +98,7 @@ func asm_assert ...@@ -98,6 +98,7 @@ func asm_assert
asm_print_line_dec asm_print_line_dec
_assert_loop: _assert_loop:
b _assert_loop b _assert_loop
endfunc asm_assert
#endif #endif
/* /*
...@@ -114,6 +115,7 @@ func asm_print_str ...@@ -114,6 +115,7 @@ func asm_print_str
b 1b b 1b
2: 2:
ret x3 ret x3
endfunc asm_print_str
/* /*
* This function prints a hexadecimal number in x4. * This function prints a hexadecimal number in x4.
...@@ -138,6 +140,7 @@ func asm_print_hex ...@@ -138,6 +140,7 @@ func asm_print_hex
bl plat_crash_console_putc bl plat_crash_console_putc
cbnz x5, 1b cbnz x5, 1b
ret x3 ret x3
endfunc asm_print_hex
/*********************************************************** /***********************************************************
* The common implementation of do_panic for all BL stages * The common implementation of do_panic for all BL stages
...@@ -185,4 +188,5 @@ el3_panic: ...@@ -185,4 +188,5 @@ el3_panic:
bl asm_print_hex bl asm_print_hex
_panic_loop: _panic_loop:
b _panic_loop b _panic_loop
endfunc do_panic
drivers/arm/pl011/pl011_console.S
View file @ 9c7eecce
...@@ -64,6 +64,7 @@ func console_init ...@@ -64,6 +64,7 @@ func console_init
adrp x3, console_base adrp x3, console_base
str x0, [x3, :lo12:console_base] str x0, [x3, :lo12:console_base]
b console_core_init b console_core_init
endfunc console_init
/* ----------------------------------------------- /* -----------------------------------------------
* int console_core_init(unsigned long base_addr, * int console_core_init(unsigned long base_addr,
...@@ -107,6 +108,7 @@ func console_core_init ...@@ -107,6 +108,7 @@ func console_core_init
mov w0, #1 mov w0, #1
init_fail: init_fail:
ret ret
endfunc console_core_init
/* --------------------------------------------- /* ---------------------------------------------
* int console_putc(int c) * int console_putc(int c)
...@@ -122,6 +124,7 @@ func console_putc ...@@ -122,6 +124,7 @@ func console_putc
adrp x2, console_base adrp x2, console_base
ldr x1, [x2, :lo12:console_base] ldr x1, [x2, :lo12:console_base]
b console_core_putc b console_core_putc
endfunc console_putc
/* -------------------------------------------------------- /* --------------------------------------------------------
* int console_core_putc(int c, unsigned int base_addr) * int console_core_putc(int c, unsigned int base_addr)
...@@ -154,6 +157,7 @@ func console_core_putc ...@@ -154,6 +157,7 @@ func console_core_putc
putc_error: putc_error:
mov w0, #-1 mov w0, #-1
ret ret
endfunc console_core_putc
/* --------------------------------------------- /* ---------------------------------------------
* int console_getc(void) * int console_getc(void)
...@@ -176,3 +180,4 @@ func console_getc ...@@ -176,3 +180,4 @@ func console_getc
getc_error: getc_error:
mov w0, #-1 mov w0, #-1
ret ret
endfunc console_getc
include/common/asm_macros.S
View file @ 9c7eecce
...@@ -85,9 +85,18 @@ ...@@ -85,9 +85,18 @@
.macro func _name .macro func _name
.section .text.\_name, "ax" .section .text.\_name, "ax"
.type \_name, %function .type \_name, %function
.func \_name
\_name: \_name:
.endm .endm
/*
* This macro is used to mark the end of a function.
*/
.macro endfunc _name
.endfunc
.size \_name, . - \_name
.endm
/* --------------------------------------------- /* ---------------------------------------------
* Find the type of reset and jump to handler * Find the type of reset and jump to handler
* if present. If the handler is null then it is * if present. If the handler is null then it is
......
lib/aarch64/cache_helpers.S
View file @ 9c7eecce
...@@ -56,6 +56,7 @@ flush_loop: ...@@ -56,6 +56,7 @@ flush_loop:
b.lo flush_loop b.lo flush_loop
dsb sy dsb sy
ret ret
endfunc flush_dcache_range
/* ------------------------------------------ /* ------------------------------------------
...@@ -75,6 +76,7 @@ inv_loop: ...@@ -75,6 +76,7 @@ inv_loop:
b.lo inv_loop b.lo inv_loop
dsb sy dsb sy
ret ret
endfunc inv_dcache_range
/* --------------------------------------------------------------- /* ---------------------------------------------------------------
...@@ -154,6 +156,7 @@ level_done: ...@@ -154,6 +156,7 @@ level_done:
isb isb
exit: exit:
ret ret
endfunc do_dcsw_op
dcsw_loop_table: dcsw_loop_table:
dcsw_loop isw dcsw_loop isw
...@@ -163,10 +166,12 @@ dcsw_loop_table: ...@@ -163,10 +166,12 @@ dcsw_loop_table:
func dcsw_op_louis func dcsw_op_louis
dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
endfunc dcsw_op_louis
func dcsw_op_all func dcsw_op_all
dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
endfunc dcsw_op_all
/* --------------------------------------------------------------- /* ---------------------------------------------------------------
* Helper macro for data cache operations by set/way for the * Helper macro for data cache operations by set/way for the
...@@ -189,6 +194,7 @@ func dcsw_op_all ...@@ -189,6 +194,7 @@ func dcsw_op_all
*/ */
func dcsw_op_level1 func dcsw_op_level1
dcsw_op_level #(1 << LEVEL_SHIFT) dcsw_op_level #(1 << LEVEL_SHIFT)
endfunc dcsw_op_level1
/* --------------------------------------------------------------- /* ---------------------------------------------------------------
* Data cache operations by set/way for level 2 cache * Data cache operations by set/way for level 2 cache
...@@ -199,6 +205,7 @@ func dcsw_op_level1 ...@@ -199,6 +205,7 @@ func dcsw_op_level1
*/ */
func dcsw_op_level2 func dcsw_op_level2
dcsw_op_level #(2 << LEVEL_SHIFT) dcsw_op_level #(2 << LEVEL_SHIFT)
endfunc dcsw_op_level2
/* --------------------------------------------------------------- /* ---------------------------------------------------------------
* Data cache operations by set/way for level 3 cache * Data cache operations by set/way for level 3 cache
...@@ -209,3 +216,4 @@ func dcsw_op_level2 ...@@ -209,3 +216,4 @@ func dcsw_op_level2
*/ */
func dcsw_op_level3 func dcsw_op_level3
dcsw_op_level #(3 << LEVEL_SHIFT) dcsw_op_level #(3 << LEVEL_SHIFT)
endfunc dcsw_op_level3
lib/aarch64/misc_helpers.S
View file @ 9c7eecce
...@@ -53,6 +53,7 @@ func get_afflvl_shift ...@@ -53,6 +53,7 @@ func get_afflvl_shift
mov x1, #MPIDR_AFFLVL_SHIFT mov x1, #MPIDR_AFFLVL_SHIFT
lsl x0, x0, x1 lsl x0, x0, x1
ret ret
endfunc get_afflvl_shift
func mpidr_mask_lower_afflvls func mpidr_mask_lower_afflvls
cmp x1, #3 cmp x1, #3
...@@ -62,14 +63,17 @@ func mpidr_mask_lower_afflvls ...@@ -62,14 +63,17 @@ func mpidr_mask_lower_afflvls
lsr x0, x0, x2 lsr x0, x0, x2
lsl x0, x0, x2 lsl x0, x0, x2
ret ret
endfunc mpidr_mask_lower_afflvls
func eret func eret
eret eret
endfunc eret
func smc func smc
smc #0 smc #0
endfunc smc
/* ----------------------------------------------------------------------- /* -----------------------------------------------------------------------
* void zeromem16(void *mem, unsigned int length); * void zeromem16(void *mem, unsigned int length);
...@@ -97,7 +101,9 @@ z_loop1: ...@@ -97,7 +101,9 @@ z_loop1:
b.eq z_end b.eq z_end
strb wzr, [x0], #1 strb wzr, [x0], #1
b z_loop1 b z_loop1
z_end: ret z_end:
ret
endfunc zeromem16
/* -------------------------------------------------------------------------- /* --------------------------------------------------------------------------
...@@ -129,7 +135,9 @@ m_loop1: ...@@ -129,7 +135,9 @@ m_loop1:
strb w3, [x0], #1 strb w3, [x0], #1
subs x2, x2, #1 subs x2, x2, #1
b.ne m_loop1 b.ne m_loop1
m_end: ret m_end:
ret
endfunc memcpy16
/* --------------------------------------------------------------------------- /* ---------------------------------------------------------------------------
* Disable the MMU at EL3 * Disable the MMU at EL3
...@@ -148,11 +156,13 @@ do_disable_mmu: ...@@ -148,11 +156,13 @@ do_disable_mmu:
isb // ensure MMU is off isb // ensure MMU is off
mov x0, #DCCISW // DCache clean and invalidate mov x0, #DCCISW // DCache clean and invalidate
b dcsw_op_all b dcsw_op_all
endfunc disable_mmu_el3
func disable_mmu_icache_el3 func disable_mmu_icache_el3
mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
b do_disable_mmu b do_disable_mmu
endfunc disable_mmu_icache_el3
/* --------------------------------------------------------------------------- /* ---------------------------------------------------------------------------
* Enable the use of VFP at EL3 * Enable the use of VFP at EL3
...@@ -169,4 +179,5 @@ func enable_vfp ...@@ -169,4 +179,5 @@ func enable_vfp
msr cptr_el3, x0 msr cptr_el3, x0
isb isb
ret ret
endfunc enable_vfp
#endif #endif
lib/cpus/aarch64/aem_generic.S
View file @ 9c7eecce
...@@ -49,6 +49,7 @@ func aem_generic_core_pwr_dwn ...@@ -49,6 +49,7 @@ func aem_generic_core_pwr_dwn
* --------------------------------------------- * ---------------------------------------------
*/ */
b dcsw_op_louis b dcsw_op_louis
endfunc aem_generic_core_pwr_dwn
func aem_generic_cluster_pwr_dwn func aem_generic_cluster_pwr_dwn
...@@ -67,6 +68,7 @@ func aem_generic_cluster_pwr_dwn ...@@ -67,6 +68,7 @@ func aem_generic_cluster_pwr_dwn
*/ */
mov x0, #DCCISW mov x0, #DCCISW
b dcsw_op_all b dcsw_op_all
endfunc aem_generic_cluster_pwr_dwn
/* --------------------------------------------- /* ---------------------------------------------
* This function provides cpu specific * This function provides cpu specific
...@@ -80,6 +82,7 @@ func aem_generic_cluster_pwr_dwn ...@@ -80,6 +82,7 @@ func aem_generic_cluster_pwr_dwn
func aem_generic_cpu_reg_dump func aem_generic_cpu_reg_dump
mov x6, #0 /* no registers to report */ mov x6, #0 /* no registers to report */
ret ret
endfunc aem_generic_cpu_reg_dump
/* cpu_ops for Base AEM FVP */ /* cpu_ops for Base AEM FVP */
......
lib/cpus/aarch64/cortex_a53.S
View file @ 9c7eecce
...@@ -44,6 +44,7 @@ func cortex_a53_disable_dcache ...@@ -44,6 +44,7 @@ func cortex_a53_disable_dcache
msr sctlr_el3, x1 msr sctlr_el3, x1
isb isb
ret ret
endfunc cortex_a53_disable_dcache
/* --------------------------------------------- /* ---------------------------------------------
* Disable intra-cluster coherency * Disable intra-cluster coherency
...@@ -56,6 +57,7 @@ func cortex_a53_disable_smp ...@@ -56,6 +57,7 @@ func cortex_a53_disable_smp
isb isb
dsb sy dsb sy
ret ret
endfunc cortex_a53_disable_smp
func cortex_a53_reset_func func cortex_a53_reset_func
/* --------------------------------------------- /* ---------------------------------------------
...@@ -72,6 +74,7 @@ func cortex_a53_reset_func ...@@ -72,6 +74,7 @@ func cortex_a53_reset_func
isb isb
skip_smp_setup: skip_smp_setup:
ret ret
endfunc cortex_a53_reset_func
func cortex_a53_core_pwr_dwn func cortex_a53_core_pwr_dwn
mov x18, x30 mov x18, x30
...@@ -95,6 +98,7 @@ func cortex_a53_core_pwr_dwn ...@@ -95,6 +98,7 @@ func cortex_a53_core_pwr_dwn
*/ */
mov x30, x18 mov x30, x18
b cortex_a53_disable_smp b cortex_a53_disable_smp
endfunc cortex_a53_core_pwr_dwn
func cortex_a53_cluster_pwr_dwn func cortex_a53_cluster_pwr_dwn
mov x18, x30 mov x18, x30
...@@ -131,6 +135,7 @@ func cortex_a53_cluster_pwr_dwn ...@@ -131,6 +135,7 @@ func cortex_a53_cluster_pwr_dwn
*/ */
mov x30, x18 mov x30, x18
b cortex_a53_disable_smp b cortex_a53_disable_smp
endfunc cortex_a53_cluster_pwr_dwn
/* --------------------------------------------- /* ---------------------------------------------
* This function provides cortex_a53 specific * This function provides cortex_a53 specific
...@@ -149,5 +154,6 @@ func cortex_a53_cpu_reg_dump ...@@ -149,5 +154,6 @@ func cortex_a53_cpu_reg_dump
adr x6, cortex_a53_regs adr x6, cortex_a53_regs
mrs x8, CPUECTLR_EL1 mrs x8, CPUECTLR_EL1
ret ret
endfunc cortex_a53_cpu_reg_dump
declare_cpu_ops cortex_a53, CORTEX_A53_MIDR declare_cpu_ops cortex_a53, CORTEX_A53_MIDR
lib/cpus/aarch64/cortex_a57.S
View file @ 9c7eecce
...@@ -45,6 +45,7 @@ func cortex_a57_disable_dcache ...@@ -45,6 +45,7 @@ func cortex_a57_disable_dcache
msr sctlr_el3, x1 msr sctlr_el3, x1
isb isb
ret ret
endfunc cortex_a57_disable_dcache
/* --------------------------------------------- /* ---------------------------------------------
* Disable all types of L2 prefetches. * Disable all types of L2 prefetches.
...@@ -60,6 +61,7 @@ func cortex_a57_disable_l2_prefetch ...@@ -60,6 +61,7 @@ func cortex_a57_disable_l2_prefetch
isb isb
dsb ish dsb ish
ret ret
endfunc cortex_a57_disable_l2_prefetch
/* --------------------------------------------- /* ---------------------------------------------
* Disable intra-cluster coherency * Disable intra-cluster coherency
...@@ -70,6 +72,7 @@ func cortex_a57_disable_smp ...@@ -70,6 +72,7 @@ func cortex_a57_disable_smp
bic x0, x0, #CPUECTLR_SMP_BIT bic x0, x0, #CPUECTLR_SMP_BIT
msr CPUECTLR_EL1, x0 msr CPUECTLR_EL1, x0
ret ret
endfunc cortex_a57_disable_smp
/* --------------------------------------------- /* ---------------------------------------------
* Disable debug interfaces * Disable debug interfaces
...@@ -81,6 +84,7 @@ func cortex_a57_disable_ext_debug ...@@ -81,6 +84,7 @@ func cortex_a57_disable_ext_debug
isb isb
dsb sy dsb sy
ret ret
endfunc cortex_a57_disable_ext_debug
/* -------------------------------------------------- /* --------------------------------------------------
* Errata Workaround for Cortex A57 Errata #806969. * Errata Workaround for Cortex A57 Errata #806969.
...@@ -113,6 +117,7 @@ apply_806969: ...@@ -113,6 +117,7 @@ apply_806969:
msr CPUACTLR_EL1, x1 msr CPUACTLR_EL1, x1
skip_806969: skip_806969:
ret ret
endfunc errata_a57_806969_wa
/* --------------------------------------------------- /* ---------------------------------------------------
...@@ -146,6 +151,7 @@ apply_813420: ...@@ -146,6 +151,7 @@ apply_813420:
msr CPUACTLR_EL1, x1 msr CPUACTLR_EL1, x1
skip_813420: skip_813420:
ret ret
endfunc errata_a57_813420_wa
/* ------------------------------------------------- /* -------------------------------------------------
* The CPU Ops reset function for Cortex-A57. * The CPU Ops reset function for Cortex-A57.
...@@ -188,6 +194,7 @@ func cortex_a57_reset_func ...@@ -188,6 +194,7 @@ func cortex_a57_reset_func
skip_smp_setup: skip_smp_setup:
isb isb
ret x19 ret x19
endfunc cortex_a57_reset_func
/* ---------------------------------------------------- /* ----------------------------------------------------
* The CPU Ops core power down function for Cortex-A57. * The CPU Ops core power down function for Cortex-A57.
...@@ -227,6 +234,7 @@ func cortex_a57_core_pwr_dwn ...@@ -227,6 +234,7 @@ func cortex_a57_core_pwr_dwn
*/ */
mov x30, x18 mov x30, x18
b cortex_a57_disable_ext_debug b cortex_a57_disable_ext_debug
endfunc cortex_a57_core_pwr_dwn
/* ------------------------------------------------------- /* -------------------------------------------------------
* The CPU Ops cluster power down function for Cortex-A57. * The CPU Ops cluster power down function for Cortex-A57.
...@@ -280,6 +288,7 @@ func cortex_a57_cluster_pwr_dwn ...@@ -280,6 +288,7 @@ func cortex_a57_cluster_pwr_dwn
*/ */
mov x30, x18 mov x30, x18
b cortex_a57_disable_ext_debug b cortex_a57_disable_ext_debug
endfunc cortex_a57_cluster_pwr_dwn
/* --------------------------------------------- /* ---------------------------------------------
* This function provides cortex_a57 specific * This function provides cortex_a57 specific
...@@ -298,6 +307,7 @@ func cortex_a57_cpu_reg_dump ...@@ -298,6 +307,7 @@ func cortex_a57_cpu_reg_dump
adr x6, cortex_a57_regs adr x6, cortex_a57_regs
mrs x8, CPUECTLR_EL1 mrs x8, CPUECTLR_EL1
ret ret
endfunc cortex_a57_cpu_reg_dump
declare_cpu_ops cortex_a57, CORTEX_A57_MIDR declare_cpu_ops cortex_a57, CORTEX_A57_MIDR
lib/cpus/aarch64/cortex_a72.S
View file @ 9c7eecce
...@@ -44,6 +44,7 @@ func cortex_a72_disable_dcache ...@@ -44,6 +44,7 @@ func cortex_a72_disable_dcache
msr sctlr_el3, x1 msr sctlr_el3, x1
isb isb
ret ret
endfunc cortex_a72_disable_dcache
/* --------------------------------------------- /* ---------------------------------------------
* Disable all types of L2 prefetches. * Disable all types of L2 prefetches.
...@@ -58,6 +59,7 @@ func cortex_a72_disable_l2_prefetch ...@@ -58,6 +59,7 @@ func cortex_a72_disable_l2_prefetch
msr CPUECTLR_EL1, x0 msr CPUECTLR_EL1, x0
isb isb
ret ret
endfunc cortex_a72_disable_l2_prefetch
/* --------------------------------------------- /* ---------------------------------------------
* Disable the load-store hardware prefetcher. * Disable the load-store hardware prefetcher.
...@@ -70,6 +72,7 @@ func cortex_a72_disable_hw_prefetcher ...@@ -70,6 +72,7 @@ func cortex_a72_disable_hw_prefetcher
isb isb
dsb ish dsb ish
ret ret
endfunc cortex_a72_disable_hw_prefetcher
/* --------------------------------------------- /* ---------------------------------------------
* Disable intra-cluster coherency * Disable intra-cluster coherency
...@@ -80,6 +83,7 @@ func cortex_a72_disable_smp ...@@ -80,6 +83,7 @@ func cortex_a72_disable_smp
bic x0, x0, #CPUECTLR_SMP_BIT bic x0, x0, #CPUECTLR_SMP_BIT
msr CPUECTLR_EL1, x0 msr CPUECTLR_EL1, x0
ret ret
endfunc cortex_a72_disable_smp
/* --------------------------------------------- /* ---------------------------------------------
* Disable debug interfaces * Disable debug interfaces
...@@ -91,6 +95,7 @@ func cortex_a72_disable_ext_debug ...@@ -91,6 +95,7 @@ func cortex_a72_disable_ext_debug
isb isb
dsb sy dsb sy
ret ret
endfunc cortex_a72_disable_ext_debug
/* ------------------------------------------------- /* -------------------------------------------------
* The CPU Ops reset function for Cortex-A72. * The CPU Ops reset function for Cortex-A72.
...@@ -106,6 +111,7 @@ func cortex_a72_reset_func ...@@ -106,6 +111,7 @@ func cortex_a72_reset_func
msr CPUECTLR_EL1, x0 msr CPUECTLR_EL1, x0
isb isb
ret ret
endfunc cortex_a72_reset_func
/* ---------------------------------------------------- /* ----------------------------------------------------
* The CPU Ops core power down function for Cortex-A72. * The CPU Ops core power down function for Cortex-A72.
...@@ -151,6 +157,7 @@ func cortex_a72_core_pwr_dwn ...@@ -151,6 +157,7 @@ func cortex_a72_core_pwr_dwn
*/ */
mov x30, x18 mov x30, x18
b cortex_a72_disable_ext_debug b cortex_a72_disable_ext_debug
endfunc cortex_a72_core_pwr_dwn
/* ------------------------------------------------------- /* -------------------------------------------------------
* The CPU Ops cluster power down function for Cortex-A72. * The CPU Ops cluster power down function for Cortex-A72.
...@@ -211,6 +218,7 @@ func cortex_a72_cluster_pwr_dwn ...@@ -211,6 +218,7 @@ func cortex_a72_cluster_pwr_dwn
*/ */
mov x30, x18 mov x30, x18
b cortex_a72_disable_ext_debug b cortex_a72_disable_ext_debug
endfunc cortex_a72_cluster_pwr_dwn
/* --------------------------------------------- /* ---------------------------------------------
* This function provides cortex_a72 specific * This function provides cortex_a72 specific
...@@ -229,6 +237,7 @@ func cortex_a72_cpu_reg_dump ...@@ -229,6 +237,7 @@ func cortex_a72_cpu_reg_dump
adr x6, cortex_a72_regs adr x6, cortex_a72_regs
mrs x8, CPUECTLR_EL1 mrs x8, CPUECTLR_EL1
ret ret
endfunc cortex_a72_cpu_reg_dump
declare_cpu_ops cortex_a72, CORTEX_A72_MIDR declare_cpu_ops cortex_a72, CORTEX_A72_MIDR
lib/cpus/aarch64/cpu_helpers.S
View file @ 9c7eecce
...@@ -67,6 +67,7 @@ func reset_handler ...@@ -67,6 +67,7 @@ func reset_handler
br x2 br x2
1: 1:
ret ret
endfunc reset_handler
#endif /* IMAGE_BL1 || IMAGE_BL31 */ #endif /* IMAGE_BL1 || IMAGE_BL31 */
...@@ -88,6 +89,7 @@ func prepare_core_pwr_dwn ...@@ -88,6 +89,7 @@ func prepare_core_pwr_dwn
/* Get the cpu_ops core_pwr_dwn handler */ /* Get the cpu_ops core_pwr_dwn handler */
ldr x1, [x0, #CPU_PWR_DWN_CORE] ldr x1, [x0, #CPU_PWR_DWN_CORE]
br x1 br x1
endfunc prepare_core_pwr_dwn
/* /*
* The prepare cluster power down function for all platforms. After * The prepare cluster power down function for all platforms. After
...@@ -106,6 +108,7 @@ func prepare_cluster_pwr_dwn ...@@ -106,6 +108,7 @@ func prepare_cluster_pwr_dwn
/* Get the cpu_ops cluster_pwr_dwn handler */ /* Get the cpu_ops cluster_pwr_dwn handler */
ldr x1, [x0, #CPU_PWR_DWN_CLUSTER] ldr x1, [x0, #CPU_PWR_DWN_CLUSTER]
br x1 br x1
endfunc prepare_cluster_pwr_dwn
/* /*
...@@ -129,6 +132,7 @@ func init_cpu_ops ...@@ -129,6 +132,7 @@ func init_cpu_ops
mov x30, x10 mov x30, x10
1: 1:
ret ret
endfunc init_cpu_ops
#endif /* IMAGE_BL31 */ #endif /* IMAGE_BL31 */
#if IMAGE_BL31 && CRASH_REPORTING #if IMAGE_BL31 && CRASH_REPORTING
...@@ -153,6 +157,7 @@ func do_cpu_reg_dump ...@@ -153,6 +157,7 @@ func do_cpu_reg_dump
1: 1:
mov x30, x16 mov x30, x16
ret ret
endfunc do_cpu_reg_dump
#endif #endif
/* /*
...@@ -197,6 +202,7 @@ func get_cpu_ops_ptr ...@@ -197,6 +202,7 @@ func get_cpu_ops_ptr
sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR) sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR)
error_exit: error_exit:
ret ret
endfunc get_cpu_ops_ptr
#if DEBUG #if DEBUG
/* /*
...@@ -221,5 +227,6 @@ func print_revision_warning ...@@ -221,5 +227,6 @@ func print_revision_warning
bl asm_print_str bl asm_print_str
1: 1:
ret x5 ret x5
endfunc print_revision_warning
#endif #endif
lib/locks/exclusive/spinlock.S
View file @ 9c7eecce
...@@ -43,8 +43,10 @@ l2: ldaxr w1, [x0] ...@@ -43,8 +43,10 @@ l2: ldaxr w1, [x0]
stxr w1, w2, [x0] stxr w1, w2, [x0]
cbnz w1, l2 cbnz w1, l2
ret ret
endfunc spin_lock
func spin_unlock func spin_unlock
stlr wzr, [x0] stlr wzr, [x0]
ret ret
endfunc spin_unlock
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