diff --git a/bl32/tsp/tsp-fvp.mk b/bl32/tsp/tsp-fvp.mk
index b1d0afef1beb96116b4e4ca9ab3b9fa0de21b653..21864d68da930da20b31d9eb967c842e3dc8cf6f 100644
--- a/bl32/tsp/tsp-fvp.mk
+++ b/bl32/tsp/tsp-fvp.mk
@@ -31,7 +31,7 @@
# TSP source files specific to FVP platform
BL32_SOURCES += drivers/arm/gic/gic_v2.c \
plat/common/aarch64/platform_mp_stack.S \
- plat/fvp/aarch64/plat_common.c \
- plat/fvp/aarch64/plat_helpers.S \
- plat/fvp/bl32_plat_setup.c \
- plat/fvp/plat_gic.c
+ plat/fvp/aarch64/fvp_common.c \
+ plat/fvp/aarch64/fvp_helpers.S \
+ plat/fvp/bl32_fvp_setup.c \
+ plat/fvp/fvp_gic.c
diff --git a/plat/fvp/aarch64/plat_common.c b/plat/fvp/aarch64/fvp_common.c
similarity index 98%
rename from plat/fvp/aarch64/plat_common.c
rename to plat/fvp/aarch64/fvp_common.c
index a5a9291fb0dd6d23f3f1acca06034fe2469513a9..b385cc62283c113a3fc38c7b9f308f3ec6b192b7 100644
--- a/plat/fvp/aarch64/plat_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -132,7 +132,7 @@ const mmap_region_t fvp_mmap[] = {
* the platform memory map & initialize the mmu, for the given exception level
******************************************************************************/
#define DEFINE_CONFIGURE_MMU_EL(_el) \
- void configure_mmu_el##_el(unsigned long total_base, \
+ void fvp_configure_mmu_el##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit, \
@@ -157,7 +157,7 @@ DEFINE_CONFIGURE_MMU_EL(1)
DEFINE_CONFIGURE_MMU_EL(3)
/* Simple routine which returns a configuration variable value */
-unsigned long platform_get_cfgvar(unsigned int var_id)
+unsigned long fvp_get_cfgvar(unsigned int var_id)
{
assert(var_id < CONFIG_LIMIT);
return platform_config[var_id];
@@ -170,7 +170,7 @@ unsigned long platform_get_cfgvar(unsigned int var_id)
* these platforms. This information is stored in a per-BL array to allow the
* code to take the correct path.Per BL platform configuration.
******************************************************************************/
-int platform_config_setup(void)
+int fvp_config_setup(void)
{
unsigned int rev, hbi, bld, arch, sys_id, midr_pn;
@@ -255,7 +255,7 @@ uint64_t plat_get_syscnt_freq(void)
return counter_base_frequency;
}
-void plat_cci_setup(void)
+void fvp_cci_setup(void)
{
unsigned long cci_setup;
@@ -264,7 +264,7 @@ void plat_cci_setup(void)
* for locks as no other cpu is active at the
* moment
*/
- cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+ cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
if (cci_setup)
cci_enable_coherency(read_mpidr());
}
diff --git a/plat/fvp/aarch64/plat_helpers.S b/plat/fvp/aarch64/fvp_helpers.S
similarity index 100%
rename from plat/fvp/aarch64/plat_helpers.S
rename to plat/fvp/aarch64/fvp_helpers.S
diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_fvp_setup.c
similarity index 95%
rename from plat/fvp/bl1_plat_setup.c
rename to plat/fvp/bl1_fvp_setup.c
index 49f21c7990a80c904ad68be791eedb673a56e391..2e9c31f501642fdf4ffd1343c4851893240617c8 100644
--- a/plat/fvp/bl1_plat_setup.c
+++ b/plat/fvp/bl1_fvp_setup.c
@@ -105,7 +105,7 @@ void bl1_early_platform_setup(void)
}
/* Initialize the platform config for future decision making */
- platform_config_setup();
+ fvp_config_setup();
}
/*******************************************************************************
@@ -116,7 +116,7 @@ void bl1_early_platform_setup(void)
void bl1_platform_setup(void)
{
/* Initialise the IO layer and register platform IO devices */
- io_setup();
+ fvp_io_setup();
}
@@ -127,15 +127,14 @@ void bl1_platform_setup(void)
******************************************************************************/
void bl1_plat_arch_setup(void)
{
- plat_cci_setup();
-
-
- configure_mmu_el3(bl1_tzram_layout.total_base,
- bl1_tzram_layout.total_size,
- TZROM_BASE,
- TZROM_BASE + TZROM_SIZE,
- BL1_COHERENT_RAM_BASE,
- BL1_COHERENT_RAM_LIMIT);
+ fvp_cci_setup();
+
+ fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
+ bl1_tzram_layout.total_size,
+ TZROM_BASE,
+ TZROM_BASE + TZROM_SIZE,
+ BL1_COHERENT_RAM_BASE,
+ BL1_COHERENT_RAM_LIMIT);
}
diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_fvp_setup.c
similarity index 97%
rename from plat/fvp/bl2_plat_setup.c
rename to plat/fvp/bl2_fvp_setup.c
index 0d3001d1676b5e8a9ee5f931299ab0254ee76c48..1ff5e5d3e1f5ea81d38cef3b5298f44aec703c38 100644
--- a/plat/fvp/bl2_plat_setup.c
+++ b/plat/fvp/bl2_fvp_setup.c
@@ -176,7 +176,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
bl2_tzram_layout.next = 0;
/* Initialize the platform config for future decision making */
- platform_config_setup();
+ fvp_config_setup();
}
/*******************************************************************************
@@ -191,10 +191,10 @@ void bl2_platform_setup(void)
* other platforms might have more programmable security devices
* present.
*/
- plat_security_setup();
+ fvp_security_setup();
/* Initialise the IO layer and register platform IO devices */
- io_setup();
+ fvp_io_setup();
}
/* Flush the TF params and the TF plat params */
@@ -211,12 +211,12 @@ extern void bl2_plat_flush_bl31_params(void)
******************************************************************************/
void bl2_plat_arch_setup()
{
- configure_mmu_el1(bl2_tzram_layout.total_base,
- bl2_tzram_layout.total_size,
- BL2_RO_BASE,
- BL2_RO_LIMIT,
- BL2_COHERENT_RAM_BASE,
- BL2_COHERENT_RAM_LIMIT);
+ fvp_configure_mmu_el1(bl2_tzram_layout.total_base,
+ bl2_tzram_layout.total_size,
+ BL2_RO_BASE,
+ BL2_RO_LIMIT,
+ BL2_COHERENT_RAM_BASE,
+ BL2_COHERENT_RAM_LIMIT);
}
/*******************************************************************************
diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_fvp_setup.c
similarity index 94%
rename from plat/fvp/bl31_plat_setup.c
rename to plat/fvp/bl31_fvp_setup.c
index 4d6e0f599139bec59f00d7b1b5cd56bb7d138b9d..848c4f287380dd3a61043200b2881e33f3f49fb4 100644
--- a/plat/fvp/bl31_plat_setup.c
+++ b/plat/fvp/bl31_fvp_setup.c
@@ -95,9 +95,9 @@ el_change_info_t *bl31_get_next_image_info(uint32_t type)
#if RESET_TO_BL31
if (type == NON_SECURE)
- plat_get_entry_point_info(NON_SECURE, &bl33_entrypoint_info);
+ fvp_get_entry_point_info(NON_SECURE, &bl33_entrypoint_info);
else
- plat_get_entry_point_info(SECURE, &bl32_entrypoint_info);
+ fvp_get_entry_point_info(SECURE, &bl32_entrypoint_info);
next_image_info = (type == NON_SECURE) ?
&bl33_entrypoint_info :
@@ -130,7 +130,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
void *plat_params_from_bl2)
{
/* Initialize the platform config for future decision making */
- platform_config_setup();
+ fvp_config_setup();
console_init(PL011_UART0_BASE);
@@ -142,7 +142,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
* other platforms might have more programmable security devices
* present.
*/
- plat_security_setup();
+ fvp_security_setup();
#else
assert(from_bl2->h.type == PARAM_BL31);
assert(from_bl2->h.version >= VERSION_1);
@@ -188,7 +188,7 @@ void bl31_platform_setup()
fvp_pwrc_setup();
/* Topologies are best known to the platform. */
- plat_setup_topology();
+ fvp_setup_topology();
}
/*******************************************************************************
@@ -198,15 +198,15 @@ void bl31_platform_setup()
void bl31_plat_arch_setup()
{
#if RESET_TO_BL31
- plat_cci_setup();
+ fvp_cci_setup();
#endif
- configure_mmu_el3(BL31_RO_BASE,
- (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
- BL31_RO_BASE,
- BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ fvp_configure_mmu_el3(BL31_RO_BASE,
+ (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
+ BL31_RO_BASE,
+ BL31_RO_LIMIT,
+ BL31_COHERENT_RAM_BASE,
+ BL31_COHERENT_RAM_LIMIT);
}
#if RESET_TO_BL31
@@ -214,7 +214,7 @@ void bl31_plat_arch_setup()
* Generate the entry point info for Non Secure and Secure images
* for transferring control from BL31
******************************************************************************/
-void plat_get_entry_point_info(unsigned long target_security,
+void fvp_get_entry_point_info(unsigned long target_security,
el_change_info_t *target_entry_info)
{
if (target_security == NON_SECURE) {
diff --git a/plat/fvp/bl32_plat_setup.c b/plat/fvp/bl32_fvp_setup.c
similarity index 94%
rename from plat/fvp/bl32_plat_setup.c
rename to plat/fvp/bl32_fvp_setup.c
index c12b19c88744ecac4a2db6f81c2fc766c598afd4..3228f9a309961580a3920a80faf6269e943705b0 100644
--- a/plat/fvp/bl32_plat_setup.c
+++ b/plat/fvp/bl32_fvp_setup.c
@@ -75,7 +75,7 @@ void bl32_early_platform_setup(void)
console_init(PL011_UART1_BASE);
/* Initialize the platform config for future decision making */
- platform_config_setup();
+ fvp_config_setup();
}
/*******************************************************************************
@@ -92,10 +92,10 @@ void bl32_platform_setup()
******************************************************************************/
void bl32_plat_arch_setup()
{
- configure_mmu_el1(BL32_RO_BASE,
- (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
- BL32_RO_BASE,
- BL32_RO_LIMIT,
- BL32_COHERENT_RAM_BASE,
- BL32_COHERENT_RAM_LIMIT);
+ fvp_configure_mmu_el1(BL32_RO_BASE,
+ (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
+ BL32_RO_BASE,
+ BL32_RO_LIMIT,
+ BL32_COHERENT_RAM_BASE,
+ BL32_COHERENT_RAM_LIMIT);
}
diff --git a/plat/fvp/plat_gic.c b/plat/fvp/fvp_gic.c
similarity index 96%
rename from plat/fvp/plat_gic.c
rename to plat/fvp/fvp_gic.c
index bbcd418579e3b68125bf20f60fce9c5279719625..24d836b82ca16acf51108ae6234f3fcf01982b5f 100644
--- a/plat/fvp/plat_gic.c
+++ b/plat/fvp/fvp_gic.c
@@ -277,8 +277,8 @@ void gic_setup(void)
{
unsigned int gicd_base, gicc_base;
- gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
gic_cpuif_setup(gicc_base);
gic_distif_setup(gicd_base);
@@ -298,7 +298,7 @@ void gic_setup(void)
******************************************************************************/
uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
{
- uint32_t gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ uint32_t gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
assert(type == INTR_TYPE_S_EL1 ||
type == INTR_TYPE_EL3 ||
@@ -328,7 +328,7 @@ uint32_t ic_get_pending_interrupt_type()
{
uint32_t id, gicc_base;
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
id = gicc_read_hppir(gicc_base);
/* Assume that all secure interrupts are S-EL1 interrupts */
@@ -350,7 +350,7 @@ uint32_t ic_get_pending_interrupt_id()
{
uint32_t id, gicc_base;
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
id = gicc_read_hppir(gicc_base);
if (id < 1022)
@@ -372,7 +372,7 @@ uint32_t ic_get_pending_interrupt_id()
******************************************************************************/
uint32_t ic_acknowledge_interrupt()
{
- return gicc_read_IAR(platform_get_cfgvar(CONFIG_GICC_ADDR));
+ return gicc_read_IAR(fvp_get_cfgvar(CONFIG_GICC_ADDR));
}
/*******************************************************************************
@@ -381,7 +381,7 @@ uint32_t ic_acknowledge_interrupt()
******************************************************************************/
void ic_end_of_interrupt(uint32_t id)
{
- gicc_write_EOIR(platform_get_cfgvar(CONFIG_GICC_ADDR), id);
+ gicc_write_EOIR(fvp_get_cfgvar(CONFIG_GICC_ADDR), id);
return;
}
@@ -394,7 +394,7 @@ uint32_t ic_get_interrupt_type(uint32_t id)
{
uint32_t group;
- group = gicd_get_igroupr(platform_get_cfgvar(CONFIG_GICD_ADDR), id);
+ group = gicd_get_igroupr(fvp_get_cfgvar(CONFIG_GICD_ADDR), id);
/* Assume that all secure interrupts are S-EL1 interrupts */
if (group == GRP0)
diff --git a/plat/fvp/plat_io_storage.c b/plat/fvp/fvp_io_storage.c
similarity index 99%
rename from plat/fvp/plat_io_storage.c
rename to plat/fvp/fvp_io_storage.c
index 0a034edbc7888d7a9fb6b65d0c75fcb323ccb6a5..13485ffc0464be23466dcc9969f3889413b6776d 100644
--- a/plat/fvp/plat_io_storage.c
+++ b/plat/fvp/fvp_io_storage.c
@@ -168,7 +168,7 @@ static int open_semihosting(const uintptr_t spec)
return result;
}
-void io_setup (void)
+void fvp_io_setup (void)
{
int io_result = IO_FAIL;
diff --git a/plat/fvp/plat_pm.c b/plat/fvp/fvp_pm.c
similarity index 96%
rename from plat/fvp/plat_pm.c
rename to plat/fvp/fvp_pm.c
index 5a88e87f39921f40ef0b9ea7e0b40c80533a378c..ef03e7f0efe51c715a6c2b6b08ce2ffb5acd3f7f 100644
--- a/plat/fvp/plat_pm.c
+++ b/plat/fvp/fvp_pm.c
@@ -139,7 +139,7 @@ int fvp_affinst_off(unsigned long mpidr,
* Disable coherency if this cluster is to be
* turned off
*/
- cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+ cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
if (cci_setup) {
cci_disable_coherency(mpidr);
}
@@ -160,7 +160,7 @@ int fvp_affinst_off(unsigned long mpidr,
* Take this cpu out of intra-cluster coherency if
* the FVP flavour supports the SMP bit.
*/
- cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
+ cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
if (cpu_setup) {
ectlr = read_cpuectlr();
ectlr &= ~CPUECTLR_SMP_BIT;
@@ -171,7 +171,7 @@ int fvp_affinst_off(unsigned long mpidr,
* Prevent interrupts from spuriously waking up
* this cpu
*/
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
gic_cpuif_deactivate(gicc_base);
/*
@@ -219,7 +219,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
* Disable coherency if this cluster is to be
* turned off
*/
- cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+ cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
if (cci_setup) {
cci_disable_coherency(mpidr);
}
@@ -239,7 +239,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
* Take this cpu out of intra-cluster coherency if
* the FVP flavour supports the SMP bit.
*/
- cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
+ cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
if (cpu_setup) {
ectlr = read_cpuectlr();
ectlr &= ~CPUECTLR_SMP_BIT;
@@ -257,7 +257,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
* Prevent interrupts from spuriously waking up
* this cpu
*/
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
gic_cpuif_deactivate(gicc_base);
/*
@@ -311,7 +311,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
*/
fvp_pwrc_write_pponr(mpidr);
- plat_cci_setup();
+ fvp_cci_setup();
}
break;
@@ -325,7 +325,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
* Turn on intra-cluster coherency if the FVP flavour supports
* it.
*/
- cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
+ cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
if (cpu_setup) {
ectlr = read_cpuectlr();
ectlr |= CPUECTLR_SMP_BIT;
@@ -345,8 +345,8 @@ int fvp_affinst_on_finish(unsigned long mpidr,
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
sizeof(unsigned long));
- gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
/* Enable the gic cpu interface */
gic_cpuif_setup(gicc_base);
diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h
index 5324b7cfaa867e3ef1775a54ac9809fe5960dfc7..067365e1c519f26f1c9b17da584d591215128821 100644
--- a/plat/fvp/fvp_private.h
+++ b/plat/fvp/fvp_private.h
@@ -63,26 +63,26 @@ struct meminfo;
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
-void configure_mmu_el1(unsigned long total_base,
- unsigned long total_size,
- unsigned long,
- unsigned long,
- unsigned long,
- unsigned long);
-void configure_mmu_el3(unsigned long total_base,
- unsigned long total_size,
- unsigned long,
- unsigned long,
- unsigned long,
- unsigned long);
-unsigned long platform_get_cfgvar(unsigned int);
-int platform_config_setup(void);
+void fvp_configure_mmu_el1(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long,
+ unsigned long,
+ unsigned long,
+ unsigned long);
+void fvp_configure_mmu_el3(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long,
+ unsigned long,
+ unsigned long,
+ unsigned long);
+unsigned long fvp_get_cfgvar(unsigned int);
+int fvp_config_setup(void);
#if RESET_TO_BL31
-void plat_get_entry_point_info(unsigned long target_security,
+void fvp_get_entry_point_info(unsigned long target_security,
el_change_info_t *target_entry_info);
#endif
-void plat_cci_setup(void);
+void fvp_cci_setup(void);
/* Declarations for fvp_gic.c */
void gic_cpuif_deactivate(unsigned int);
@@ -91,13 +91,13 @@ void gic_pcpu_distif_setup(unsigned int);
void gic_setup(void);
/* Declarations for fvp_topology.c */
-int plat_setup_topology(void);
+int fvp_setup_topology(void);
/* Declarations for plat_io_storage.c */
-void io_setup(void);
+void fvp_io_setup(void);
/* Declarations for plat_security.c */
-void plat_security_setup(void);
+void fvp_security_setup(void);
/* Sets the entrypoint for BL32 */
void fvp_set_bl32_entrypoint(el_change_info_t *bl32_ep);
diff --git a/plat/fvp/plat_security.c b/plat/fvp/fvp_security.c
similarity index 98%
rename from plat/fvp/plat_security.c
rename to plat/fvp/fvp_security.c
index 79dabe2a1045ed140ac6b9f0c4c2aab625b67c35..72e3bc96462877b934e5e41294e7541ecdde222d 100644
--- a/plat/fvp/plat_security.c
+++ b/plat/fvp/fvp_security.c
@@ -43,7 +43,7 @@
* TODO:
* Might want to enable interrupt on violations when supported?
*/
-void plat_security_setup(void)
+void fvp_security_setup(void)
{
tzc_instance_t controller;
@@ -56,7 +56,7 @@ void plat_security_setup(void)
* configurations, those would be configured here.
*/
- if (!platform_get_cfgvar(CONFIG_HAS_TZC))
+ if (!fvp_get_cfgvar(CONFIG_HAS_TZC))
return;
/*
diff --git a/plat/fvp/plat_topology.c b/plat/fvp/fvp_topology.c
similarity index 99%
rename from plat/fvp/plat_topology.c
rename to plat/fvp/fvp_topology.c
index f06b4f7470653b123b97f9af9c9ca9223ce10a09..cf21503773bf4964d221dc520a12304f640061ce 100644
--- a/plat/fvp/plat_topology.c
+++ b/plat/fvp/fvp_topology.c
@@ -190,7 +190,7 @@ int plat_get_max_afflvl()
* the FVP flavour its running on. We construct all the mpidrs we can handle
* and rely on the PWRC.PSYSR to flag absent cpus when their status is queried.
******************************************************************************/
-int plat_setup_topology()
+int fvp_setup_topology()
{
unsigned char aff0, aff1, aff_state, aff0_offset = 0;
unsigned long mpidr;
diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S
index 4f181dbfff24ede7d39ec89ed366a464cd58d0e4..b0eee9dff44a0e8cec5908734881a35149b0edf8 100644
--- a/plat/fvp/include/plat_macros.S
+++ b/plat/fvp/include/plat_macros.S
@@ -44,7 +44,7 @@ gic_regs: .asciz "gic_iar", "gic_ctlr", ""
*/
.macro plat_print_gic_regs
mov x0, #CONFIG_GICC_ADDR
- bl platform_get_cfgvar
+ bl fvp_get_cfgvar
/* gic base address is now in x0 */
ldr w1, [x0, #GICC_IAR]
ldr w2, [x0, #GICD_CTLR]
diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk
index d752d65d241eb2a09e7c322c61570d34955e82b9..35fa5bfc3248dd482eaad24bcecab197f4e8b87c 100644
--- a/plat/fvp/platform.mk
+++ b/plat/fvp/platform.mk
@@ -55,31 +55,31 @@ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011.c \
lib/aarch64/xlat_tables.c \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
- plat/fvp/plat_io_storage.c
+ plat/fvp/fvp_io_storage.c
BL1_SOURCES += drivers/arm/cci400/cci400.c \
plat/common/aarch64/platform_up_stack.S \
- plat/fvp/bl1_plat_setup.c \
- plat/fvp/aarch64/plat_common.c \
- plat/fvp/aarch64/plat_helpers.S
+ plat/fvp/bl1_fvp_setup.c \
+ plat/fvp/aarch64/fvp_common.c \
+ plat/fvp/aarch64/fvp_helpers.S
BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
plat/common/aarch64/platform_up_stack.S \
- plat/fvp/bl2_plat_setup.c \
- plat/fvp/plat_security.c \
- plat/fvp/aarch64/plat_common.c
+ plat/fvp/bl2_fvp_setup.c \
+ plat/fvp/fvp_security.c \
+ plat/fvp/aarch64/fvp_common.c
BL31_SOURCES += drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
drivers/arm/gic/aarch64/gic_v3_sysregs.S \
drivers/arm/cci400/cci400.c \
plat/common/aarch64/platform_mp_stack.S \
- plat/fvp/bl31_plat_setup.c \
- plat/fvp/plat_gic.c \
- plat/fvp/plat_pm.c \
- plat/fvp/plat_topology.c \
- plat/fvp/aarch64/plat_helpers.S \
- plat/fvp/aarch64/plat_common.c \
+ plat/fvp/bl31_fvp_setup.c \
+ plat/fvp/fvp_gic.c \
+ plat/fvp/fvp_pm.c \
+ plat/fvp/fvp_topology.c \
+ plat/fvp/aarch64/fvp_helpers.S \
+ plat/fvp/aarch64/fvp_common.c \
plat/fvp/drivers/pwrc/fvp_pwrc.c
ifeq (${RESET_TO_BL31}, 1)