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adam.huang
Arm Trusted Firmware
Commits
9f89feb9
Commit
9f89feb9
authored
Feb 01, 2016
by
danh-arm
Browse files
Merge pull request #504 from sandrine-bailleux/sb/fix-doc-mmap
Porting Guide: Clarify identity-mapping requirement
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6874e723
ef7fb9e4
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docs/porting-guide.md
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@@ -72,10 +72,20 @@ either mandatory or optional.
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@@ -72,10 +72,20 @@ either mandatory or optional.
2.1 Common mandatory modifications
2.1 Common mandatory modifications
----------------------------------
----------------------------------
A platform port must enable the Memory Management Unit (MMU) with identity
mapped page tables, and enable both the instruction and data caches for each BL
A platform port must enable the Memory Management Unit (MMU) as well as the
stage. In ARM standard platforms, each BL stage configures the MMU in
instruction and data caches for each BL stage. Setting up the translation
the platform-specific architecture setup function,
`blX_plat_arch_setup()`
.
tables is the responsibility of the platform port because memory maps differ
across platforms. A memory translation library (see
`lib/aarch64/xlat_helpers.c`
and
`lib/aarch64/xlat_tables.c`
) is provided to help in this setup. Note that
although this library supports non-identity mappings, this is intended only for
re-mapping peripheral physical addresses and allows platforms with high I/O
addresses to reduce their virtual address space. All other addresses
corresponding to code and data must currently use an identity mapping.
In ARM standard platforms, each BL stage configures the MMU in the
platform-specific architecture setup function,
`blX_plat_arch_setup()`
, and uses
an identity mapping for all addresses.
If the build option
`USE_COHERENT_MEM`
is enabled, each platform can allocate a
If the build option
`USE_COHERENT_MEM`
is enabled, each platform can allocate a
block of identity mapped secure memory with Device-nGnRE attributes aligned to
block of identity mapped secure memory with Device-nGnRE attributes aligned to
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