From a01b0f1619e90aa39e0b5232767269d083186d74 Mon Sep 17 00:00:00 2001
From: Varun Wadekar <vwadekar@nvidia.com>
Date: Mon, 12 Mar 2018 15:11:55 -0700
Subject: [PATCH] Tegra: restrict non-secure PMC accesses
Platforms that do not support bpmp firmware, do not need access
to the PMC block from outside of the CPU complex. The agents
running on the CPU can always access the PMC through the EL3
exception space.
This patch restricts non-secure world access to the PMC block on
such platforms.
Change-Id: I2c4318dc07ddf6407c1700595e0f4aac377ba258
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
---
plat/nvidia/tegra/include/t210/tegra_def.h | 2 ++
plat/nvidia/tegra/soc/t210/plat_psci_handlers.c | 5 +++++
plat/nvidia/tegra/soc/t210/plat_setup.c | 6 ++++++
3 files changed, 13 insertions(+)
diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h
index 7e3789c65..bbcfdc5c1 100644
--- a/plat/nvidia/tegra/include/t210/tegra_def.h
+++ b/plat/nvidia/tegra/include/t210/tegra_def.h
@@ -175,6 +175,8 @@
******************************************************************************/
#define TEGRA_MISC_BASE U(0x70000000)
#define HARDWARE_REVISION_OFFSET U(0x804)
+#define APB_SLAVE_SECURITY_ENABLE U(0xC00)
+#define PMC_SECURITY_EN_BIT (U(1) << 13)
#define PINMUX_AUX_DVFS_PWM U(0x3184)
#define PINMUX_PWM_TRISTATE (U(1) << 4)
diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index 7e176e6f4..b7d10af00 100644
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -473,6 +473,11 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
plat_params->tzdram_size + offset);
+
+ /* restrict PMC access to secure world */
+ val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
+ val |= PMC_SECURITY_EN_BIT;
+ mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
}
}
diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index d6b0853c5..9fb51690b 100644
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -157,6 +157,7 @@ void plat_late_platform_setup(void)
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
uint64_t sc7entry_end, offset;
int ret;
+ uint32_t val;
/* memmap TZDRAM area containing the SC7 Entry Firmware */
if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) {
@@ -193,6 +194,11 @@ void plat_late_platform_setup(void)
plat_params->sc7entry_fw_size,
MT_SECURE | MT_RO_DATA);
assert(ret == 0);
+
+ /* restrict PMC access to secure world */
+ val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
+ val |= PMC_SECURITY_EN_BIT;
+ mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
}
}
--
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