From a21185832f12f92abb8f8f86b96a12d1e0f79979 Mon Sep 17 00:00:00 2001
From: Sandrine Bailleux <sandrine.bailleux@arm.com>
Date: Thu, 8 May 2014 14:46:47 +0100
Subject: [PATCH] Enable Debug and SError exceptions on warm boot path

Enable Debug and SError exceptions:
 - when receiving an SMC;
 - when a CPU is physically powered up (upon resumption from suspend
   or in response to a PSCI cpu_on call)

Change-Id: I7e5613e34034be6ed68ec9e2aef4de66aa5ac65e
---
 include/cm_macros.S        | 6 ++++++
 services/psci/psci_entry.S | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/include/cm_macros.S b/include/cm_macros.S
index 9eeec1899..6901f7667 100644
--- a/include/cm_macros.S
+++ b/include/cm_macros.S
@@ -59,6 +59,12 @@
 	 * -----------------------------------------------------
 	 */
 	.macro	handle_sync_exception
+	/* ---------------------------------------------
+	 * Enable Debug and SError interrupts
+	 * ---------------------------------------------
+	 */
+	msr	daifclr, #(DAIF_ABT_BIT | DAIF_DBG_BIT)
+
 	stp	x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
 	mrs	x30, esr_el3
 	ubfx	x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
diff --git a/services/psci/psci_entry.S b/services/psci/psci_entry.S
index 361dfde45..32d5c5123 100644
--- a/services/psci/psci_entry.S
+++ b/services/psci/psci_entry.S
@@ -75,6 +75,12 @@ psci_aff_common_finish_entry:
 	msr	vbar_el3, x0
 	isb
 
+	/* ---------------------------------------------
+	 * Enable Debug and SError interrupts
+	 * ---------------------------------------------
+	 */
+	msr	daifclr, #(DAIF_ABT_BIT | DAIF_DBG_BIT)
+
 	/* ---------------------------------------------
 	 * Use SP_EL0 for the C runtime stack.
 	 * ---------------------------------------------
-- 
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