Merge "Switch AARCH32/AARCH64 to __aarch64__" into integration

plat/arm/common/arm_bl2_el3_setup.c

@@ -83,10 +83,10 @@ void arm_bl2_el3_plat_arch_setup(void)
 
 	setup_page_tables(bl_regions, plat_arm_get_mmap());
 
-#ifdef AARCH32
-	enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
 	enable_mmu_el3(0);
+#else
+	enable_mmu_svc_mon(0);
 #endif
 }
 

plat/arm/common/arm_bl2_setup.c

@@ -128,10 +128,10 @@ void arm_bl2_plat_arch_setup(void)
 
 	setup_page_tables(bl_regions, plat_arm_get_mmap());
 
-#ifdef AARCH32
-	enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
 	enable_mmu_el1(0);
+#else
+	enable_mmu_svc_mon(0);
 #endif
 
 	arm_setup_romlib();
@@ -153,7 +153,7 @@ int arm_bl2_handle_post_image_load(unsigned int image_id)
 	assert(bl_mem_params);
 
 	switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
 	case BL32_IMAGE_ID:
 #ifdef SPD_opteed
 		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);

plat/arm/common/arm_bl2u_setup.c

@@ -83,10 +83,10 @@ void arm_bl2u_plat_arch_setup(void)
 
 	setup_page_tables(bl_regions, plat_arm_get_mmap());
 
-#ifdef AARCH32
-	enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
 	enable_mmu_el1(0);
+#else
+	enable_mmu_svc_mon(0);
 #endif
 	arm_setup_romlib();
 }

plat/arm/common/arm_common.c

@@ -59,7 +59,7 @@ uint32_t arm_get_spsr_for_bl32_entry(void)
 /*******************************************************************************
  * Gets SPSR for BL33 entry
  ******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
 uint32_t arm_get_spsr_for_bl33_entry(void)
 {
 	unsigned int mode;
@@ -97,7 +97,7 @@ uint32_t arm_get_spsr_for_bl33_entry(void)
 			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
 	return spsr;
 }
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
 
 /*******************************************************************************
  * Configures access to the system counter timer module.

plat/arm/common/arm_gicv3.c

@@ -83,8 +83,8 @@ void __init plat_arm_gic_driver_init(void)
 	 * can use GIC system registers to manage interrupts and does
 	 * not need GIC interface base addresses to be configured.
 	 */
-#if (defined(AARCH32) && defined(IMAGE_BL32)) || \
-	(defined(IMAGE_BL31) && !defined(AARCH32))
+#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
+	(defined(__aarch64__) && defined(IMAGE_BL31))
 	gicv3_driver_init(&arm_gic_data);
 #endif
 }

plat/arm/common/arm_nor_psci_mem_protect.c

@@ -26,7 +26,7 @@
 
 static mem_region_t arm_ram_ranges[] = {
 	{DRAM1_NS_IMAGE_LIMIT, DRAM1_PROTECTED_SIZE},
-#ifdef AARCH64
+#ifdef __aarch64__
 	{ARM_DRAM2_BASE, 1u << ONE_GB_SHIFT},
 #endif
 };

plat/arm/common/arm_pm.c

@@ -116,7 +116,7 @@ int arm_validate_ns_entrypoint(uintptr_t entrypoint)
 			(ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
 		return 0;
 	}
-#ifndef AARCH32
+#ifdef __aarch64__
 	if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint <
 			(ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) {
 		return 0;

plat/arm/common/execution_state_switch.c

@@ -40,7 +40,7 @@ int arm_execution_state_switch(unsigned int smc_fid,
 		void *handle)
 {
 	/* Execution state can be switched only if EL3 is AArch64 */
-#ifdef AARCH64
+#ifdef __aarch64__
 	bool caller_64, thumb = false, from_el2;
 	unsigned int el, endianness;
 	u_register_t spsr, pc, scr, sctlr;
@@ -173,7 +173,7 @@ invalid_param:
 	SMC_RET1(handle, STATE_SW_E_PARAM);
 
 exec_denied:
-#endif
+#endif /* __aarch64__ */
 	/* State switch denied */
 	SMC_RET1(handle, STATE_SW_E_DENIED);
 }

plat/common/plat_gicv3.c

@@ -300,7 +300,7 @@ unsigned int plat_ic_get_interrupt_id(unsigned int raw)
 #pragma weak plat_ic_end_of_interrupt
 
 /* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */
-#ifdef AARCH32
+#ifndef __aarch64__
 #define IS_IN_EL1()	IS_IN_SECURE()
 #endif
 

plat/common/plat_psci_common.c

@@ -20,10 +20,10 @@
 #define MHZ_TICKS_PER_SEC 1000000U
 
 /* Maximum time-stamp value read from architectural counters */
-#ifdef AARCH32
-#define MAX_TS	UINT32_MAX
-#else
+#ifdef __aarch64__
 #define MAX_TS	UINT64_MAX
+#else
+#define MAX_TS	UINT32_MAX
 #endif
 
 /* Following are used as ID's to capture time-stamp */

plat/hisilicon/hikey/hikey_bl2_setup.c

@@ -77,7 +77,7 @@ uint32_t hikey_get_spsr_for_bl32_entry(void)
 /*******************************************************************************
  * Gets SPSR for BL33 entry
  ******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
 uint32_t hikey_get_spsr_for_bl33_entry(void)
 {
 	unsigned int mode;
@@ -112,7 +112,7 @@ uint32_t hikey_get_spsr_for_bl33_entry(void)
 			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
 	return spsr;
 }
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
 
 int hikey_bl2_handle_post_image_load(unsigned int image_id)
 {
@@ -125,7 +125,7 @@ int hikey_bl2_handle_post_image_load(unsigned int image_id)
 	assert(bl_mem_params);
 
 	switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
 	case BL32_IMAGE_ID:
 #ifdef SPD_opteed
 		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);

plat/hisilicon/hikey/include/hikey_layout.h

@@ -113,7 +113,7 @@
 #endif
 
 /* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
 #ifdef SPD_none
 #undef BL32_BASE
 #endif /* SPD_none */

plat/hisilicon/hikey960/hikey960_bl2_setup.c

@@ -168,7 +168,7 @@ uint32_t hikey960_get_spsr_for_bl32_entry(void)
 /*******************************************************************************
  * Gets SPSR for BL33 entry
  ******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
 uint32_t hikey960_get_spsr_for_bl33_entry(void)
 {
 	unsigned int mode;
@@ -203,7 +203,7 @@ uint32_t hikey960_get_spsr_for_bl33_entry(void)
 			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
 	return spsr;
 }
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
 
 int hikey960_bl2_handle_post_image_load(unsigned int image_id)
 {
@@ -216,7 +216,7 @@ int hikey960_bl2_handle_post_image_load(unsigned int image_id)
 	assert(bl_mem_params);
 
 	switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
 	case BL32_IMAGE_ID:
 #ifdef SPD_opteed
 		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);

plat/hisilicon/hikey960/include/platform_def.h

@@ -95,7 +95,7 @@
 #endif
 
 /* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
 #ifdef SPD_none
 #undef BL32_BASE
 #endif /* SPD_none */

plat/hisilicon/poplar/bl2_plat_setup.c

@@ -54,7 +54,7 @@ uint32_t poplar_get_spsr_for_bl32_entry(void)
 /*******************************************************************************
  * Gets SPSR for BL33 entry
  ******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
 uint32_t poplar_get_spsr_for_bl33_entry(void)
 {
 	unsigned long el_status;
@@ -93,7 +93,7 @@ uint32_t poplar_get_spsr_for_bl33_entry(void)
 			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
 	return spsr;
 }
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
 
 int poplar_bl2_handle_post_image_load(unsigned int image_id)
 {
@@ -107,7 +107,7 @@ int poplar_bl2_handle_post_image_load(unsigned int image_id)
 	assert(bl_mem_params);
 
 	switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
 	case BL32_IMAGE_ID:
 #ifdef SPD_opteed
 		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);

plat/hisilicon/poplar/include/platform_def.h

@@ -107,7 +107,7 @@
 #endif
 
 /* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
 #ifdef SPD_none
 #undef BL32_BASE
 #endif /* SPD_none */

plat/layerscape/common/ls_bl1_setup.c

@@ -59,11 +59,11 @@ void ls_bl1_plat_arch_setup(void)
 #endif
 			     );
 	VERBOSE("After setup the page tables\n");
-#ifdef AARCH32
-	enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
 	enable_mmu_el3(0);
-#endif /* AARCH32 */
+#else
+	enable_mmu_svc_mon(0);
+#endif /* __aarch64__ */
 	VERBOSE("After MMU enabled\n");
 }
 

plat/layerscape/common/ls_bl2_setup.c

@@ -54,10 +54,10 @@ void ls_bl2_plat_arch_setup(void)
 #endif
 			      );
 
-#ifdef AARCH32
-	enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
 	enable_mmu_el1(0);
+#else
+	enable_mmu_svc_mon(0);
 #endif
 }
 
@@ -74,7 +74,7 @@ int ls_bl2_handle_post_image_load(unsigned int image_id)
 	assert(bl_mem_params);
 
 	switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
 	case BL32_IMAGE_ID:
 		bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry();
 		break;

plat/layerscape/common/ls_common.c

@@ -143,7 +143,7 @@ uint32_t ls_get_spsr_for_bl32_entry(void)
 /*******************************************************************************
  * Gets SPSR for BL33 entry
  ******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
 uint32_t ls_get_spsr_for_bl33_entry(void)
 {
 	unsigned int mode;
@@ -181,7 +181,7 @@ uint32_t ls_get_spsr_for_bl33_entry(void)
 			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
 	return spsr;
 }
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
 
 /*******************************************************************************
  * Returns Layerscape platform specific memory map regions.

plat/qemu/qemu_bl1_setup.c

@@ -41,10 +41,10 @@ void bl1_early_platform_setup(void)
  * does basic initialization. Later architectural setup (bl1_arch_setup())
  * does not do anything platform specific.
  *****************************************************************************/
-#ifdef AARCH32
-#define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
-#else
+#ifdef __aarch64__
 #define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_el3(__VA_ARGS__)
+#else
+#define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
 #endif
 
 void bl1_plat_arch_setup(void)