diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
index ba8436be42eb1f94c852226c0ea75edaf832aaa7..c38099f050230df5c3c691e5861a7f49c4f6926d 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -186,6 +186,7 @@ void mce_verify_firmware_version(void)
 	}
 }
 
+#if ENABLE_STRICT_CHECKING_MODE
 /*******************************************************************************
  * Handler to enable the strict checking mode
  ******************************************************************************/
@@ -235,3 +236,4 @@ void mce_enable_strict_checking(void)
 		nvg_enable_strict_checking_mode();
 	}
 }
+#endif
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index 536ed57c009fda325b1d96a4d65bcf1f32fd3f77..d6b56871b917dfcb0a7b0ab89d74882bcd898a65 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -288,6 +288,7 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
 	return ret;
 }
 
+#if ENABLE_STRICT_CHECKING_MODE
 /*
  * Enable strict checking mode
  *
@@ -300,3 +301,4 @@ void nvg_enable_strict_checking_mode(void)
 
 	nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
 }
+#endif
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index 9a9113ec23ce9a50aa01e0f6c264cf911904b0b2..e2001b18e959c94d44cb53d99ca6a9f308079824 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -357,11 +357,13 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 	 */
 	if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
 
+#if ENABLE_STRICT_CHECKING_MODE
 		/*
 		 * Enable strict checking after programming the GSC for
 		 * enabling TZSRAM and TZDRAM
 		 */
 		mce_enable_strict_checking();
+#endif
 
 		/* Init SMMU */
 		tegra_smmu_init();
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index 7dde9dde5b77f7b00aec76ce88aa6f5194b04d57..3b582444c0c2362feffa50d19e24625278c3b3fa 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -293,9 +293,11 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
 
 void plat_late_platform_setup(void)
 {
+#if ENABLE_STRICT_CHECKING_MODE
 	/*
 	 * Enable strict checking after programming the GSC for
 	 * enabling TZSRAM and TZDRAM
 	 */
 	mce_enable_strict_checking();
+#endif
 }
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index 35b46a8003e5bd3e34a5ec90a1d0aa687f496360..f114b7e5be57db5a25e7da71bf465885e3865ef9 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -8,6 +8,9 @@
 ENABLE_CONSOLE_SPE			:= 0
 $(eval $(call add_define,ENABLE_CONSOLE_SPE))
 
+ENABLE_STRICT_CHECKING_MODE	:= 1
+$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE))
+
 RESET_TO_BL31				:= 1
 
 PROGRAMMABLE_RESET_ADDRESS		:= 1