drivers: renesas: rcar: eMMC driver code clean up

Fix checkpatch warnings and MISRA defects. There are no functional changes. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I349a8eaa7bd6182746ba5104ee9fe48a709c24fd

drivers: renesas: rcar: eMMC driver code clean up
Fix checkpatch warnings and MISRA defects. There are no functional changes. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I349a8eaa7bd6182746ba5104ee9fe48a709c24fd
a492527b · Biju Das · 2773536b · a492527b · a492527b · a492527b
Commit a492527b authored Dec 13, 2020 by Biju Das
--- a/drivers/renesas/rcar/emmc/emmc_cmd.c
+++ b/drivers/renesas/rcar/emmc/emmc_cmd.c
 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
@@ -7,10 +7,10 @@
 #include <common/debug.h>
 #include "emmc_config.h"
+#include "emmc_def.h"
 #include "emmc_hal.h"
-#include "emmc_std.h"
 #include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
 #include "micro_delay.h"
 static void emmc_little_to_big(uint8_t *p, uint32_t value)
@@ -22,6 +22,7 @@ static void emmc_little_to_big(uint8_t *p, uint32_t value)
 	p[1] = (uint8_t) (value >> 16);
 	p[2] = (uint8_t) (value >> 8);
 	p[3] = (uint8_t) value;
 }
 static void emmc_softreset(void)
@@ -64,7 +65,6 @@ reset:
 	SETR_32(SD_INFO2, SD_INFO2_CLEAR);
 	SETR_32(SD_INFO1_MASK, 0x00000000U);	/* all interrupt disable */
 	SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);	/* all interrupt disable */
 }
 static void emmc_read_response(uint32_t *response)
@@ -96,8 +96,7 @@ static EMMC_ERROR_CODE emmc_response_check(uint32_t *response,
 {
 	HAL_MEMCARD_RESPONSE_TYPE response_type =
-	    (HAL_MEMCARD_RESPONSE_TYPE) (mmc_drv_obj.cmd_info.
+	    ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
-					 cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
 	if (response == NULL)
 		return EMMC_ERR_PARAM;
@@ -117,7 +116,7 @@ static EMMC_ERROR_CODE emmc_response_check(uint32_t *response,
 			}
 			return EMMC_ERR_CARD_STATUS_BIT;
 		}
-		return EMMC_SUCCESS;;
+		return EMMC_SUCCESS;
 	}
 	if (response_type == HAL_MEMCARD_RESPONSE_R4) {
@@ -223,11 +222,11 @@ EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
 	state = ESTATE_BEGIN;
 	response_type =
-	    (HAL_MEMCARD_RESPONSE_TYPE) (mmc_drv_obj.cmd_info.
+	    ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd &
-					 cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
+					HAL_MEMCARD_RESPONSE_TYPE_MASK);
 	cmd_type =
-	    (HAL_MEMCARD_COMMAND_TYPE) (mmc_drv_obj.cmd_info.
+	    ((HAL_MEMCARD_COMMAND_TYPE) mmc_drv_obj.cmd_info.cmd &
-					cmd & HAL_MEMCARD_COMMAND_TYPE_MASK);
+					HAL_MEMCARD_COMMAND_TYPE_MASK);
 	/* state machine */
 	while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) {
@@ -427,8 +426,9 @@ EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
 		case ESTATE_ACCESS_END:
 			/* clear flag */
-			if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) {
+			if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
-				SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);	/* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+				/* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+				SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);
 				SETR_32(SD_STOP, 0x00000000U);
 				mmc_drv_obj.during_dma_transfer = FALSE;
 			}
@@ -448,8 +448,9 @@ EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
 		case ESTATE_TRANSFER_ERROR:
 			/* The error occurred in the Data transfer.  */
-			if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) {
+			if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
-				SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);	/* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+				/* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+				SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);
 				SETR_32(SD_STOP, 0x00000000U);
 				mmc_drv_obj.during_dma_transfer = FALSE;
 			}

--- a/drivers/renesas/rcar/emmc/emmc_config.h
+++ b/drivers/renesas/rcar/emmc/emmc_config.h
 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-/**
- * @file  emmc_config.h
- * @brief Configuration file
- *
- */
 #ifndef EMMC_CONFIG_H
 #define EMMC_CONFIG_H
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
+/* RCA */
+#define EMMC_RCA		1UL
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+/* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17)  */
+#define EMMC_RW_DATA_TIMEOUT	0x40UL
-/** @brief MMC driver config
+/* how many times to try after fail. Don't change. */
- */
+#define EMMC_RETRY_COUNT	0
-#define EMMC_RCA                1UL	/* RCA  */
-#define EMMC_RW_DATA_TIMEOUT    0x40UL	/* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17)  */
-#define EMMC_RETRY_COUNT        0	/* how many times to try after fail. Don't change. */
 #define EMMC_CMD_MAX		60UL	/* Don't change. */
-/** @brief etc
- */
 #define LOADIMAGE_FLAGS_DMA_ENABLE	0x00000001UL
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-/* ************************** FUNCTION PROTOTYPES ************************** */
-/* ********************************* CODE ********************************** */
 #endif /* EMMC_CONFIG_H */
-/* ******************************** END ************************************ */
--- a/drivers/renesas/rcar/emmc/emmc_hal.h
+++ b/drivers/renesas/rcar/emmc/emmc_hal.h
 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-/**
- * @file  emmc_hal.h
- * @brief emmc boot driver is expecting this header file
- *
- */
 #ifndef EMMC_HAL_H
 #define EMMC_HAL_H
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-#include <stdint.h>
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-/** @brief memory card error/status types
+/* memory card error/status types */
- */
 #define HAL_MEMCARD_OUT_OF_RANGE		0x80000000L
 #define HAL_MEMCARD_ADDRESS_ERROR		0x40000000L
 #define HAL_MEMCARD_BLOCK_LEN_ERROR		0x20000000L
@@ -44,57 +34,48 @@
 #define HAL_MEMCARD_AKE_SEQ_ERROR		0x00000008L
 #define HAL_MEMCARD_NO_ERRORS			0x00000000L
-/** @brief Memory card response types
+/* Memory card response types */
- */
 #define HAL_MEMCARD_COMMAND_INDEX_MASK		0x0003f
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+/* Type of the return value. */
-/** @brief Type of the return value.
- */
 typedef enum {
 	HAL_MEMCARD_FAIL = 0U,
 	HAL_MEMCARD_OK = 1U,
-	HAL_MEMCARD_DMA_ALLOC_FAIL = 2U,     /**< DMA channel allocation failed */
+	HAL_MEMCARD_DMA_ALLOC_FAIL = 2U,     /* DMA channel allocation failed */
-	HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U,  /**< DMA transfer failed */
+	HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U,  /* DMA transfer failed */
-	HAL_MEMCARD_CARD_STATUS_ERROR = 4U,  /**< A non-masked error bit was set in the card status */
+	HAL_MEMCARD_CARD_STATUS_ERROR = 4U,  /* card status non-masked error */
-	HAL_MEMCARD_CMD_TIMEOUT = 5U,	     /**< Command timeout occurred */
+	HAL_MEMCARD_CMD_TIMEOUT = 5U,	     /* Command timeout occurred */
-	HAL_MEMCARD_DATA_TIMEOUT = 6U,	     /**< Data timeout occurred */
+	HAL_MEMCARD_DATA_TIMEOUT = 6U,	     /* Data timeout occurred */
-	HAL_MEMCARD_CMD_CRC_ERROR = 7U,	     /**< Command CRC error occurred */
+	HAL_MEMCARD_CMD_CRC_ERROR = 7U,	     /* Command CRC error occurred */
-	HAL_MEMCARD_DATA_CRC_ERROR = 8U	     /**< Data CRC error occurred */
+	HAL_MEMCARD_DATA_CRC_ERROR = 8U	     /* Data CRC error occurred */
 } HAL_MEMCARD_RETURN;
-/** @brief memory access operation
+/* memory access operation */
- */
 typedef enum {
-	HAL_MEMCARD_READ = 0U,	 /**< read */
+	HAL_MEMCARD_READ = 0U,	 /* read */
-	HAL_MEMCARD_WRITE = 1U	 /**< write */
+	HAL_MEMCARD_WRITE = 1U	 /* write */
 } HAL_MEMCARD_OPERATION;
-/** @brief Type of data width on memorycard bus
+/* Type of data width on memorycard bus */
- */
 typedef enum {
 	HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U,
 	HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U,
 	HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U
-} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */
+} HAL_MEMCARD_DATA_WIDTH; /* data (bus) width types */
-/** @brief Presence of the memory card
+/* Presence of the memory card */
- */
 typedef enum {
 	HAL_MEMCARD_CARD_IS_IN = 0U,
 	HAL_MEMCARD_CARD_IS_OUT = 1U
 } HAL_MEMCARD_PRESENCE_STATUS;	/* presence status of the memory card */
-/** @brief mode of data transfer
+/* mode of data transfer */
- */
 typedef enum {
 	HAL_MEMCARD_DMA = 0U,
 	HAL_MEMCARD_NOT_DMA = 1U
 } HAL_MEMCARD_DATA_TRANSFER_MODE;
-/** @brief Memory card response types.
+/* Memory card response types. */
- */
 typedef enum hal_memcard_response_type {
 	HAL_MEMCARD_RESPONSE_NONE = 0x00000U,
 	HAL_MEMCARD_RESPONSE_R1 = 0x00100U,
@@ -108,8 +89,7 @@ typedef enum hal_memcard_response_type {
 	HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U
 } HAL_MEMCARD_RESPONSE_TYPE;
-/** @brief Memory card command types.
+/* Memory card command types. */
- */
 typedef enum hal_memcard_command_type {
 	HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U,
 	HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U,
@@ -119,8 +99,7 @@ typedef enum hal_memcard_command_type {
 	HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U
 } HAL_MEMCARD_COMMAND_TYPE;
-/** @brief Type of memory card
+/* Type of memory card */
- */
 typedef enum hal_memcard_command_card_type {
 	HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U,
 	HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U,
@@ -128,191 +107,429 @@ typedef enum hal_memcard_command_card_type {
 	HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U
 } HAL_MEMCARD_COMMAND_CARD_TYPE;
-/** @brief Memory card application command.
+/* Memory card application command. */
- */
 typedef enum hal_memcard_command_app_norm {
 	HAL_MEMCARD_COMMAND_NORMAL = 0x00000U,
 	HAL_MEMCARD_COMMAND_APP = 0x20000U,
 	HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U
 } HAL_MEMCARD_COMMAND_APP_NORM;
-/** @brief Memory card command codes.
+/* Memory card command codes. */
- */
 typedef enum {
 /* class 0 and class 1 */
-	CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD0 */
+	/* CMD0 */
-	CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD1 */
+	CMD0_GO_IDLE_STATE =
-	CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD2 */
+	    0U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC |
+	    (uint32_t) HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD1 */
+	CMD1_SEND_OP_COND =
+	    1U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD2 */
+	CMD2_ALL_SEND_CID_MMC =
+	    2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 	CMD2_ALL_SEND_CID_SD =
-	    2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR |
+	    2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
-	CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD3 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD3 */
+	CMD3_SET_RELATIVE_ADDR =
+	    3U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 	CMD3_SEND_RELATIVE_ADDR =
-	    3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    3U | (uint32_t)HAL_MEMCARD_RESPONSE_R6 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
-	CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD4 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
-	CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD5 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
-	CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD6 */
+	/* CMD4 */
+	CMD4_SET_DSR =
+	    4U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD5 */
+	CMD5_SLEEP_AWAKE =
+	    5U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD6 */
+	CMD6_SWITCH =
+	    6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 	CMD6_SWITCH_FUNC =
-	    6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 	ACMD6_SET_BUS_WIDTH =
-	    6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
-	CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD7 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
-	CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD7(from Disconnected State to Programming State) */
+	    (uint32_t)HAL_MEMCARD_COMMAND_APP,
+	/* CMD7 */
+	CMD7_SELECT_CARD =
+	    7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD7(from Disconnected State to Programming State) */
+	CMD7_SELECT_CARD_PROG =
+	    7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 	CMD7_DESELECT_CARD =
-	    7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
-	CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD8 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD8 */
+	CMD8_SEND_EXT_CSD =
+	    8U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 	CMD8_SEND_IF_COND =
-	    8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR |
+	    8U | (uint32_t)HAL_MEMCARD_RESPONSE_R7 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
-	CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD9 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
-	CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD10 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
-	CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD11 */
+	/* CMD9 */
-	CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD12 */
+	CMD9_SEND_CSD =
-	CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD12(R1b : write case) */
+	    9U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
-	CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD13 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD10 */
+	CMD10_SEND_CID =
+	    10U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD11 */
+	CMD11_READ_DAT_UNTIL_STOP =
+	    11U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD12 */
+	CMD12_STOP_TRANSMISSION =
+	    12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD12(R1b : write case) */
+	CMD12_STOP_TRANSMISSION_WRITE =
+	    12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD13 */
+	CMD13_SEND_STATUS =
+	    13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 	ACMD13_SD_STATUS =
-	    13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+	    13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
-	CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD14 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
-	CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD15 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_APP,
+	/* CMD14 */
+	CMD14_BUSTEST_R =
+	    14U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD15 */
+	CMD15_GO_INACTIVE_STATE =
+	    15U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 /* class 2 */
-	CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD16 */
+	/* CMD16 */
-	CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD17 */
+	CMD16_SET_BLOCKLEN =
-	CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD18 */
+	    16U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
-	CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD19 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD17 */
+	CMD17_READ_SINGLE_BLOCK =
+	     17U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	     (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+	     (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	     (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD18 */
+	CMD18_READ_MULTIPLE_BLOCK =
+	    18U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD19 */
+	CMD19_BUS_TEST_W =
+	    19U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 /* class 3 */
-	CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD20 */
+	/* CMD20 */
-	CMD21 = 21,		/* CMD21 */
+	CMD20_WRITE_DAT_UNTIL_STOP =
-	CMD22 = 22,		/* CMD22 */
+	    20U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD21 */
+	CMD21 = 21U,
+	/* CMD22 */
+	CMD22 = 22U,
 	ACMD22_SEND_NUM_WR_BLOCKS =
-	    22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    22U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+	    (uint32_t)HAL_MEMCARD_COMMAND_APP,
 /* class 4 */
-	CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD23 */
+	/* CMD23 */
+	CMD23_SET_BLOCK_COUNT =
+	    23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 	ACMD23_SET_WR_BLK_ERASE_COUNT =
-	    23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
-	CMD24_WRITE_BLOCK = 24 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD24 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
-	CMD25_WRITE_MULTIPLE_BLOCK = 25 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD25 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_APP,
-	CMD26_PROGRAM_CID = 26 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD26 */
+	/* CMD24 */
-	CMD27_PROGRAM_CSD = 27 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD27 */
+	CMD24_WRITE_BLOCK =
+	    24U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD25 */
+	CMD25_WRITE_MULTIPLE_BLOCK =
+	    25U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD26 */
+	CMD26_PROGRAM_CID =
+	    26U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD27 */
+	CMD27_PROGRAM_CSD =
+	    27U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 /* class 6 */
-	CMD28_SET_WRITE_PROT = 28 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD28 */
+	/* CMD28 */
-	CMD29_CLR_WRITE_PROT = 29 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD29 */
+	CMD28_SET_WRITE_PROT =
-	CMD30_SEND_WRITE_PROT = 30 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD30 */
+	    28U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
-	CMD30_SEND_WRITE_PROT_TYPE = 31 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD31 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD29 */
+	CMD29_CLR_WRITE_PROT =
+	    29U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD30 */
+	CMD30_SEND_WRITE_PROT =
+	    30U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD31 */
+	CMD30_SEND_WRITE_PROT_TYPE =
+	    31U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 /* class 5 */
-	CMD32_ERASE_WR_BLK_START = 32 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD32 */
+	/* CMD32 */
-	CMD33_ERASE_WR_BLK_END = 33 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD33 */
+	CMD32_ERASE_WR_BLK_START =
-	CMD34 = 34,		/* CMD34 */
+	    32U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
-	CMD35_ERASE_GROUP_START = 35 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD35 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
-	CMD36_ERASE_GROUP_END = 36 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD36 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
-	CMD37 = 37,		/* CMD37 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
-	CMD38_ERASE = 38 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD38 */
+	/* CMD33 */
+	CMD33_ERASE_WR_BLK_END =
+	    33U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD34 */
+	CMD34 = 34U,
+	/* CMD35 */
+	CMD35_ERASE_GROUP_START =
+	    35U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD36 */
+	CMD36_ERASE_GROUP_END =
+	    36U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD37 */
+	CMD37 = 37U,
+	/* CMD38 */
+	CMD38_ERASE =
+	    38U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 /* class 9 */
-	CMD39_FASTIO = 39 | HAL_MEMCARD_RESPONSE_R4 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD39 */
+	/* CMD39 */
-	CMD40_GO_IRQSTATE = 40 | HAL_MEMCARD_RESPONSE_R5 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD40 */
+	CMD39_FASTIO =
-	CMD41 = 41,		/* CMD41 */
+	    39U | (uint32_t)HAL_MEMCARD_RESPONSE_R4 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD40 */
+	CMD40_GO_IRQSTATE =
+	    40U | (uint32_t)HAL_MEMCARD_RESPONSE_R5 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	/* CMD41 */
+	CMD41 = 41,
 	ACMD41_SD_SEND_OP_COND =
-	    41 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR |
+	     41U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	     (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+	     (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+	     (uint32_t)HAL_MEMCARD_COMMAND_APP,
 /* class 7 */
-	CMD42_LOCK_UNLOCK = 42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD42 */
+	/* CMD42 */
+	CMD42_LOCK_UNLOCK =
+	    42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	    (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
 	ACMD42_SET_CLR_CARD_DETECT =
-	    42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
-	CMD43 = 43,		/* CMD43 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
-	CMD44 = 44,		/* CMD44 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_APP,
-	CMD45 = 45,		/* CMD45 */
+	CMD43 = 43U,		/* CMD43 */
-	CMD46 = 46,		/* CMD46 */
+	CMD44 = 44U,		/* CMD44 */
-	CMD47 = 47,		/* CMD47 */
+	CMD45 = 45U,		/* CMD45 */
-	CMD48 = 48,		/* CMD48 */
+	CMD46 = 46U,		/* CMD46 */
-	CMD49 = 49,		/* CMD49 */
+	CMD47 = 47U,		/* CMD47 */
-	CMD50 = 50,		/* CMD50 */
+	CMD48 = 48U,		/* CMD48 */
-	CMD51 = 51,		/* CMD51 */
+	CMD49 = 49U,		/* CMD49 */
+	CMD50 = 50U,		/* CMD50 */
+	CMD51 = 51U,		/* CMD51 */
 	ACMD51_SEND_SCR =
-	    51 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+	    51U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
-	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	    (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
-	CMD52 = 52,		/* CMD52 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
-	CMD53 = 53,		/* CMD53 */
+	    (uint32_t)HAL_MEMCARD_COMMAND_APP,
-	CMD54 = 54,		/* CMD54 */
+	CMD52 = 52U,		/* CMD52 */
+	CMD53 = 53U,		/* CMD53 */
+	CMD54 = 54U,		/* CMD54 */
 /* class 8 */
-	CMD55_APP_CMD = 55 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD55 */
+	/* CMD55 */
-	CMD56_GEN_CMD = 56 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD56 */
+	CMD55_APP_CMD =
-	CMD57 = 57,		/* CMD57 */
+	   55U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
-	CMD58 = 58,		/* CMD58 */
+	   (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
-	CMD59 = 59,		/* CMD59 */
+	   (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
-	CMD60 = 60,		/* CMD60 */
+	   (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
-	CMD61 = 61,		/* CMD61 */
+	/* CMD56 */
-	CMD62 = 62,		/* CMD62 */
+	CMD56_GEN_CMD =
-	CMD63 = 63		/* CMD63 */
+	   56U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+	   (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+	   (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+	   (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+	CMD57 = 57U,		/* CMD57 */
+	CMD58 = 58U,		/* CMD58 */
+	CMD59 = 59U,		/* CMD59 */
+	CMD60 = 60U,		/* CMD60 */
+	CMD61 = 61U,		/* CMD61 */
+	CMD62 = 62U,		/* CMD62 */
+	CMD63 = 63U		/* CMD63 */
 } HAL_MEMCARD_COMMAND;
-/** @brief Configuration structure from HAL layer.
+/*
+ * Configuration structure from HAL layer.
 *
 * If some field is not available it should be filled with 0xFF.
- * The API version is 32-bit unsigned integer telling the version of the API. The integer is divided to four sections which each can be treated as a 8-bit unsigned number:
+ * The API version is 32-bit unsigned integer telling the version of the API.
- * Bits 31-24 make the most significant part of the version number. This number starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This number changes only, if the API itself changes so much that it is not compatible anymore with older releases.
+ * The integer is divided to four sections which each can be treated as a 8-bit
- * Bits 23-16 API minor version number. For example API version 2.1 would be 0x0201xxxx.
+ * unsigned number:
- * Bits 15-8 are the number of the year when release is done. The 0 is year 2000, 1 is year 2001 and so on
+ * Bits 31-24 make the most significant part of the version number. This number
- * Bits 7- are the week number when release is done. First full week of the year is 1
+ * starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This
+ * number changes only, if the API itself changes so much that it is not
+ * compatible anymore with older releases.
+ * Bits 23-16 API minor version number. For example API version 2.1 would be
+ * 0x0201xxxx.
+ * Bits 15-8 are the number of the year when release is done. The 0 is year
+ * 2000, 1 is year 2001 and so on
+ * Bits 7- are the week number when release is done. First full week of the
+ * year is 1
 *
- * @note Example: let's assume that release 2.1 is done on week 10 year 2008 the version will get the value 0x0201080A
+ * Example: let's assume that release 2.1 is done on week 10 year 2008
+ * the version will get the value 0x0201080A
 */
 typedef struct {
-    /**
+	/*
 	 * Version of the chipset API implementation
 	 *
 	 * bits [31:24] API specification major version number.<br>
 	 * bits [23:16] API specification minor version number.<br>
-    * bits [15:8] API implemention year. (2000 = 0, 2001 = 1, ...)<br>
+	 * bits [15:8] API implementation year. (2000 = 0, 2001 = 1, ...)
-    * bits [7:0] API implemention week.<br>
+	 * bits [7:0] API implementation week.
-    * Example: API specification version 4.0, implementation w46 2008 => 0x0400082E
+	 * Example: API spec version 4.0, implementation w46 2008 => 0x0400082E
 	 */
 	uint32_t api_version;
-    /** maximum block count which can be transferred at once */
+	/* maximum block count which can be transferred at once */
 	uint32_t max_block_count;
-    /** maximum clock frequence in Hz supported by HW */
+	/* maximum clock frequence in Hz supported by HW */
 	uint32_t max_clock_freq;
-    /** maximum data bus width supported by HW */
+	/* maximum data bus width supported by HW */
 	uint16_t max_data_width;
-    /** Is high-speed mode supported by HW (yes=1, no=0) */
+	/* Is high-speed mode supported by HW (yes=1, no=0) */
 	uint8_t hs_mode_supported;
-    /** Is memory card removable (yes=1, no=0) */
+	/* Is memory card removable (yes=1, no=0) */
 	uint8_t card_removable;
 } HAL_MEMCARD_HW_CONF;
-/** @brief Configuration structure to HAL layer.
+/* Configuration structure to HAL layer. */
- */
 typedef struct {
-    /** how many times to try after fail, for instance sending command */
+	/* how many times to try after fail, for instance sending command */
 	uint32_t retries_after_fail;
 } HAL_MEMCARD_INIT_CONF;
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-/* ************************** FUNCTION PROTOTYPES ************************** */
-/* ********************************* CODE ********************************** */
 #endif /* EMMC_HAL_H */
-/* ******************************** END ************************************ */
--- a/drivers/renesas/rcar/emmc/emmc_init.c
+++ b/drivers/renesas/rcar/emmc/emmc_init.c
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
@@ -32,12 +32,12 @@ EMMC_ERROR_CODE rcar_emmc_memcard_power(uint8_t mode)
 	return EMMC_SUCCESS;
 }
-static __inline void emmc_set_retry_count(uint32_t retry)
+static inline void emmc_set_retry_count(uint32_t retry)
 {
 	mmc_drv_obj.retries_after_fail = retry;
 }
-static __inline void emmc_set_data_timeout(uint32_t data_timeout)
+static inline void emmc_set_data_timeout(uint32_t data_timeout)
 {
 	mmc_drv_obj.data_timeout = data_timeout;
 }
@@ -73,7 +73,8 @@ static EMMC_ERROR_CODE emmc_dev_finalize(void)
 	EMMC_ERROR_CODE result;
 	uint32_t dataL;
-	/* MMC power off
+	/*
+	 * MMC power off
 	 * the power supply of eMMC device is always turning on.
 	 * RST_n : Hi --> Low level.
 	 */
@@ -115,27 +116,25 @@ static EMMC_ERROR_CODE emmc_dev_init(void)
 	SETR_32(HOST_MODE, 0x00000000U);	/* SD_BUF access width = 64-bit */
 	SETR_32(SD_OPTION, 0x0000C0EEU);	/* Bus width = 1bit, timeout=MAX */
-	SETR_32(SD_CLK_CTRL, 0x00000000U);	/* Automatic Control=Disable, Clock Output=Disable */
+	SETR_32(SD_CLK_CTRL, 0x00000000U);	/* Disable Automatic Control & Clock Output */
 	return EMMC_SUCCESS;
 }
 static EMMC_ERROR_CODE emmc_reset_controller(void)
 {
-	EMMC_ERROR_CODE retult;
+	EMMC_ERROR_CODE result;
 	/* initialize mmc driver */
 	emmc_drv_init();
 	/* initialize H/W */
-	retult = emmc_dev_init();
+	result = emmc_dev_init();
-	if (EMMC_SUCCESS != retult) {
+	if (result == EMMC_SUCCESS) {
-		return retult;
-	}
 		mmc_drv_obj.initialize = TRUE;
+	}
-	return retult;
+	return result;
 }
@@ -152,14 +151,12 @@ EMMC_ERROR_CODE emmc_terminate(void)
 EMMC_ERROR_CODE rcar_emmc_init(void)
 {
-	EMMC_ERROR_CODE retult;
+	EMMC_ERROR_CODE result;
-	retult = emmc_reset_controller();
-	if (EMMC_SUCCESS != retult) {
-		return retult;
-	}
+	result = emmc_reset_controller();
+	if (result == EMMC_SUCCESS) {
 		emmc_driver_config();
+	}
-	return EMMC_SUCCESS;
+	return result;
 }
--- a/drivers/renesas/rcar/emmc/emmc_interrupt.c
+++ b/drivers/renesas/rcar/emmc/emmc_interrupt.c
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights
 * reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -118,7 +118,7 @@ uint32_t emmc_interrupt(void)
 		SETR_32(DM_CM_INFO2, 0x00000000U);
 		/* interrupt clear */
 		SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE));
-		/* DM_CM_INFO2:  DMA-ch0 error occured */
+		/* DM_CM_INFO2:  DMA-ch0 error occurred */
 		if ((BIT16 & mmc_drv_obj.dm_event2) != 0) {
 			mmc_drv_obj.dma_error_flag = TRUE;
 		} else {
@@ -128,13 +128,13 @@ uint32_t emmc_interrupt(void)
 		/* wait next interrupt */
 		mmc_drv_obj.state_machine_blocking = FALSE;
 	}
-	/* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */
+	/* DM_CM_INFO1: DMA-ch1 transfer complete or error occurred */
 	else if ((end_bit & mmc_drv_obj.dm_event1) != 0U) {
 		SETR_32(DM_CM_INFO1, 0x00000000U);
 		SETR_32(DM_CM_INFO2, 0x00000000U);
 		/* interrupt clear */
 		SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE));
-		/* DM_CM_INFO2: DMA-ch1 error occured */
+		/* DM_CM_INFO2: DMA-ch1 error occurred */
 		if ((BIT17 & mmc_drv_obj.dm_event2) != 0) {
 			mmc_drv_obj.dma_error_flag = TRUE;
 		} else {

--- a/drivers/renesas/rcar/emmc/emmc_mount.c
+++ b/drivers/renesas/rcar/emmc/emmc_mount.c
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
@@ -8,10 +8,10 @@
 #include <lib/mmio.h>
 #include "emmc_config.h"
+#include "emmc_def.h"
 #include "emmc_hal.h"
-#include "emmc_std.h"
 #include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
 #include "micro_delay.h"
 #include "rcar_def.h"
@@ -53,7 +53,7 @@ static EMMC_ERROR_CODE emmc_card_init(void)
 	int32_t retry;
 	uint32_t freq = MMC_400KHZ;	/* 390KHz */
 	EMMC_ERROR_CODE result;
-	uint32_t resultCalc;
+	uint32_t result_calc;
 	/* state check */
 	if ((mmc_drv_obj.initialize != TRUE)
@@ -161,9 +161,12 @@ static EMMC_ERROR_CODE emmc_card_init(void)
 	mmc_drv_obj.selected = TRUE;
-	/* card speed check */
+	/*
-	resultCalc = emmc_calc_tran_speed(&freq);	/* Card spec is calculated from TRAN_SPEED(CSD).  */
+	 * card speed check
-	if (resultCalc == 0) {
+	 * Card spec is calculated from TRAN_SPEED(CSD)
+	 */
+	result_calc = emmc_calc_tran_speed(&freq);
+	if (result_calc == 0) {
 		emmc_write_error_info(EMMC_FUNCNO_CARD_INIT,
 				      EMMC_ERR_ILLEGAL_CARD);
 		return EMMC_ERR_ILLEGAL_CARD;
@@ -201,7 +204,8 @@ static EMMC_ERROR_CODE emmc_card_init(void)
 			    HAL_MEMCARD_NOT_DMA);
 	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
 	if (result != EMMC_SUCCESS) {
-		/* CMD12 is not send.
+		/*
+		 * CMD12 is not send.
 		 * If BUS initialization is failed, user must be execute Bus initialization again.
 		 * Bus initialization is start CMD0(soft reset command).
 		 */
@@ -217,7 +221,7 @@ static EMMC_ERROR_CODE emmc_card_init(void)
 static EMMC_ERROR_CODE emmc_high_speed(void)
 {
-	uint32_t freq;	      /**< High speed mode clock frequency */
+	uint32_t freq;	      /* High speed mode clock frequency */
 	EMMC_ERROR_CODE result;
 	uint8_t cardType;
@@ -236,8 +240,8 @@ static EMMC_ERROR_CODE emmc_high_speed(void)
 	else
 		freq = MMC_20MHZ;
-	/* Hi-Speed-mode selction */
+	/* Hi-Speed-mode selection */
-	if ((MMC_52MHZ == freq) || (MMC_26MHZ == freq)) {
+	if ((freq == MMC_52MHZ) || (freq == MMC_26MHZ)) {
 		/* CMD6 */
 		emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING);
 		result =
@@ -322,7 +326,8 @@ static EMMC_ERROR_CODE emmc_bus_width(uint32_t width)
 		return EMMC_ERR_STATE;
 	}
-	mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH) (width >> 2);	/* 2 = 8bit, 1 = 4bit, 0 =1bit */
+	/* 2 = 8bit, 1 = 4bit, 0 =1bit */
+	mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH) (width >> 2);
 	/* CMD6 */
 	emmc_make_nontrans_cmd(CMD6_SWITCH,
@@ -371,7 +376,6 @@ static EMMC_ERROR_CODE emmc_bus_width(uint32_t width)
 	return EMMC_SUCCESS;
 EXIT:
 	emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, result);
 	ERROR("BL2: emmc bus_width error end\n");
 	return result;
@@ -489,82 +493,83 @@ static void emmc_get_partition_access(void)
 static uint32_t emmc_calc_tran_speed(uint32_t *freq)
 {
-	const uint32_t unit[8] = { 10000, 100000, 1000000, 10000000,
+	const uint32_t unit[8] = { 10000U, 100000U, 1000000U, 10000000U,
-				0, 0, 0, 0 };   /**< frequency unit (1/10) */
+				   0U, 0U, 0U, 0U }; /* frequency unit (1/10) */
-	const uint32_t mult[16] = { 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45,
+	const uint32_t mult[16] = { 0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, 35U,
-				52, 55, 60, 70, 80 };
+				    40U, 45U, 52U, 55U, 60U, 70U, 80U };
-	uint32_t maxFreq;
-	uint32_t result;
 	uint32_t tran_speed = EMMC_CSD_TRAN_SPEED();
+	uint32_t max_freq;
+	uint32_t result;
-	/* tran_speed = 0x32
+	/*
+	 * tran_speed = 0x32
 	 * unit[tran_speed&0x7] = uint[0x2] = 1000000
 	 * mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26
 	 * 1000000 * 26 = 26000000 (26MHz)
 	 */
 	result = 1;
-	maxFreq =
+	max_freq =
 	    unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] *
 	    mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >>
 		 EMMC_TRANSPEED_MULT_SHIFT];
-	if (maxFreq == 0) {
+	if (max_freq == 0) {
 		result = 0;
-	} else if (MMC_FREQ_52MHZ <= maxFreq)
+	} else if (max_freq >= MMC_FREQ_52MHZ) {
 		*freq = MMC_52MHZ;
-	else if (MMC_FREQ_26MHZ <= maxFreq)
+	} else if (max_freq >= MMC_FREQ_26MHZ) {
 		*freq = MMC_26MHZ;
-	else if (MMC_FREQ_20MHZ <= maxFreq)
+	} else if (max_freq >= MMC_FREQ_20MHZ) {
 		*freq = MMC_20MHZ;
-	else
+	} else {
 		*freq = MMC_400KHZ;
+	}
 	return result;
 }
 static uint32_t emmc_set_timeout_register_value(uint32_t freq)
 {
-	uint32_t timeoutCnt;	/* SD_OPTION   - Timeout Counter  */
+	uint32_t timeout_cnt;	/* SD_OPTION   - Timeout Counter  */
 	switch (freq) {
 	case 1U:
-		timeoutCnt = 0xE0U;
+		timeout_cnt = 0xE0U;
 		break;		/* SDCLK * 2^27 */
 	case 2U:
-		timeoutCnt = 0xE0U;
+		timeout_cnt = 0xE0U;
 		break;		/* SDCLK * 2^27 */
 	case 4U:
-		timeoutCnt = 0xD0U;
+		timeout_cnt = 0xD0U;
 		break;		/* SDCLK * 2^26 */
 	case 8U:
-		timeoutCnt = 0xC0U;
+		timeout_cnt = 0xC0U;
 		break;		/* SDCLK * 2^25 */
 	case 16U:
-		timeoutCnt = 0xB0U;
+		timeout_cnt = 0xB0U;
 		break;		/* SDCLK * 2^24 */
 	case 32U:
-		timeoutCnt = 0xA0U;
+		timeout_cnt = 0xA0U;
 		break;		/* SDCLK * 2^23 */
 	case 64U:
-		timeoutCnt = 0x90U;
+		timeout_cnt = 0x90U;
 		break;		/* SDCLK * 2^22 */
 	case 128U:
-		timeoutCnt = 0x80U;
+		timeout_cnt = 0x80U;
 		break;		/* SDCLK * 2^21 */
 	case 256U:
-		timeoutCnt = 0x70U;
+		timeout_cnt = 0x70U;
 		break;		/* SDCLK * 2^20 */
 	case 512U:
-		timeoutCnt = 0x70U;
+		timeout_cnt = 0x70U;
 		break;		/* SDCLK * 2^20 */
 	default:
-		timeoutCnt = 0xE0U;
+		timeout_cnt = 0xE0U;
 		break;		/* SDCLK * 2^27 */
 	}
-	return timeoutCnt;
+	return timeout_cnt;
 }
 EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg)

--- a/drivers/renesas/rcar/emmc/emmc_read.c
+++ b/drivers/renesas/rcar/emmc/emmc_read.c
 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
@@ -7,15 +7,15 @@
 #include <arch_helpers.h>
 #include "emmc_config.h"
+#include "emmc_def.h"
 #include "emmc_hal.h"
-#include "emmc_std.h"
 #include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
 #define MIN_EMMC(a, b)	(((a) < (b)) ? (a) : (b))
 #define EMMC_RW_SECTOR_COUNT_MAX	0x0000ffffU
-static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual,
+static EMMC_ERROR_CODE emmc_multiple_block_read(uint32_t *buff_address_virtual,
 		uint32_t sector_number, uint32_t count,
 		HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode)
 {
@@ -39,7 +39,8 @@ static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual,
 	}
 	SETR_32(SD_SECCNT, count);
 	SETR_32(SD_STOP, 0x00000100);
-	SETR_32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE));	/* SD_BUF Read/Write DMA Transfer enable */
+	/* SD_BUF Read/Write DMA Transfer enable */
+	SETR_32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE));
 	/* CMD18 */
 	emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number,

--- a/drivers/renesas/rcar/emmc/emmc_registers.h
+++ b/drivers/renesas/rcar/emmc/emmc_registers.h
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-/**
- * @file  emmc_registers.h
- * @brief emmc boot driver is expecting this header file. HS-MMC module header file.
- *
- */
 #ifndef EMMC_REGISTERS_H
 #define EMMC_REGISTERS_H
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
 /* MMC channel select */
 #define MMC_CH0		(0U)	/* SDHI2/MMC0 */
 #define MMC_CH1		(1U)	/* SDHI3/MMC1 */
@@ -60,18 +50,18 @@
 #define BIT30	(0x40000000U)
 #define BIT31	(0x80000000U)
-/** @brief Clock Pulse Generator (CPG) registers
+/* Clock Pulse Generator (CPG) registers */
- */
 #define CPG_BASE	(0xE6150000U)
+/* Module stop status register 3 */
-#define	CPG_MSTPSR3		(CPG_BASE+0x0048U)	/* Module stop status register 3 */
+#define CPG_MSTPSR3	(CPG_BASE + 0x0048U)
+/* System module stop control register 3 */
-#define	CPG_SMSTPCR3		(CPG_BASE+0x013CU)	/* System module stop control register 3 */
+#define CPG_SMSTPCR3	(CPG_BASE + 0x013CU)
+/* SDHI2 clock frequency control register */
-#define	CPG_SD2CKCR		(CPG_BASE+0x0268U)	/* SDHI2 clock frequency control register */
+#define CPG_SD2CKCR	(CPG_BASE + 0x0268U)
-#define CPG_SD3CKCR		(CPG_BASE+0x026CU)	/* SDHI3 clock frequency control register */
+/* SDHI3 clock frequency control register */
+#define CPG_SD3CKCR	(CPG_BASE + 0x026CU)
-#define	CPG_CPGWPR		(CPG_BASE+0x0900U)	/* CPG Write Protect Register */
+/* CPG Write Protect Register */
+#define CPG_CPGWPR	(CPG_BASE + 0x0900U)
 #if USE_MMC_CH == MMC_CH0
 #define CPG_SDxCKCR		(CPG_SD2CKCR)	/* SDHI2/MMC0 */
@@ -79,14 +69,12 @@
 #define CPG_SDxCKCR		(CPG_SD3CKCR)	/* SDHI3/MMC1 */
 #endif /* USE_MMC_CH == MMC_CH0 */
-/** Boot Status register
+/* Boot Status register */
- */
 #define  MFISBTSTSR			(0xE6260604U)
 #define  MFISBTSTSR_BOOT_PARTITION	(0x00000010U)
-/** brief eMMC registers
+/* eMMC registers */
- */
 #define MMC0_SD_BASE		(0xEE140000U)
 #define MMC1_SD_BASE		(0xEE160000U)
@@ -136,8 +124,7 @@
 #define DM_CM_INFO2_MASK	(MMC_SD_BASE + 0x0858U)
 #define DM_DTRAN_ADDR		(MMC_SD_BASE + 0x0880U)
-/** @brief SD_INFO1 Registers
+/* SD_INFO1 Registers */
- */
 #define SD_INFO1_HPIRES		0x00010000UL /* Response Reception Completion */
 #define SD_INFO1_INFO10		0x00000400UL /* Indicates the SDDAT3 state */
 #define SD_INFO1_INFO9		0x00000200UL /* SDDAT3 Card Insertion */
@@ -149,8 +136,7 @@
 #define SD_INFO1_INFO2		0x00000004UL /* Access end */
 #define SD_INFO1_INFO0		0x00000001UL /* Response end */
-/** @brief SD_INFO2 Registers
+/* SD_INFO2 Registers */
- */
 #define SD_INFO2_ILA		0x00008000UL /* Illegal Access Error */
 #define SD_INFO2_CBSY		0x00004000UL /* Command Type Register Busy */
 #define SD_INFO2_SCLKDIVEN	0x00002000UL
@@ -165,14 +151,12 @@
 #define SD_INFO2_ERR1		0x00000002UL /* CRC Error */
 #define SD_INFO2_ERR0		0x00000001UL /* CMD Error */
 #define SD_INFO2_ALL_ERR	0x0000807FUL
-#define SD_INFO2_CLEAR				0x00000800UL	/* BIT11 The write value should always be 1. HWM_0003 */
+#define SD_INFO2_CLEAR		0x00000800UL /* BIT11 write value should always be 1. HWM_0003 */
-/** @brief SOFT_RST
+/* SOFT_RST */
- */
 #define SOFT_RST_SDRST		0x00000001UL
-/** @brief SD_CLK_CTRL
+/* SD_CLK_CTRL */
- */
 #define SD_CLK_CTRL_SDCLKOFFEN		0x00000200UL
 #define SD_CLK_CTRL_SCLKEN		0x00000100UL
 #define SD_CLK_CTRL_CLKDIV_MASK		0x000000FFUL
@@ -181,18 +165,18 @@
 #define SD_CLK_WRITE_MASK		0x000003FFUL
 #define SD_CLK_CLKDIV_CLEAR_MASK	0xFFFFFF0FUL
-/** @brief SD_OPTION
+/* SD_OPTION */
- */
 #define SD_OPTION_TIMEOUT_CNT_MASK	0x000000F0UL
-/** @brief MMC Clock Frequency
+/*
+ * MMC Clock Frequency
 * 200MHz * 1/x = output clock
 */
 #define MMC_CLK_OFF		0UL   /* Clock output is disabled */
 #define MMC_400KHZ		512UL /* 200MHz * 1/512 = 390 KHz */
 #define MMC_20MHZ		16UL  /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */
-#define MMC_26MHZ			8UL	/* 200MHz * 1/8   = 25 MHz High speed mode 26Mhz        */
+#define MMC_26MHZ		8UL   /* 200MHz * 1/8 = 25 MHz HS mode 26Mhz */
-#define MMC_52MHZ			4UL	/* 200MHz * 1/4   = 50 MHz High speed mode 52Mhz        */
+#define MMC_52MHZ		4UL   /* 200MHz * 1/4 = 50 MHz HS mode 52Mhz */
 #define MMC_100MHZ		2UL   /* 200MHz * 1/2 = 100 MHz */
 #define MMC_200MHZ		1UL   /* 200MHz * 1/1 = 200 MHz */
@@ -200,8 +184,7 @@
 #define MMC_FREQ_26MHZ		26000000UL
 #define MMC_FREQ_20MHZ		20000000UL
-/** @brief MMC Clock DIV
+/* MMC Clock DIV */
- */
 #define MMC_SD_CLK_START	0x00000100UL	/* CLOCK On */
 #define MMC_SD_CLK_STOP		(~0x00000100UL)	/* CLOCK stop */
 #define MMC_SD_CLK_DIV1		0x000000FFUL	/* 1/1 */
@@ -215,46 +198,31 @@
 #define MMC_SD_CLK_DIV256	0x00000040UL	/* 1/256 */
 #define MMC_SD_CLK_DIV512	0x00000080UL	/* 1/512 */
-/** @brief DM_CM_DTRAN_MODE
+/* DM_CM_DTRAN_MODE */
- */
 #define DM_CM_DTRAN_MODE_CH0		0x00000000UL	/* CH0(downstream) */
 #define DM_CM_DTRAN_MODE_CH1		0x00010000UL	/* CH1(upstream)   */
 #define DM_CM_DTRAN_MODE_BIT_WIDTH	0x00000030UL
-/** @brief CC_EXT_MODE
+/* CC_EXT_MODE */
- */
 #define CC_EXT_MODE_DMASDRW_ENABLE	0x00000002UL	/* SD_BUF Read/Write DMA Transfer */
 #define CC_EXT_MODE_CLEAR		0x00001010UL	/* BIT 12 & 4 always 1. */
-/** @brief DM_CM_INFO_MASK
+/* DM_CM_INFO_MASK */
- */
 #define DM_CM_INFO_MASK_CLEAR		0xFFFCFFFEUL
 #define DM_CM_INFO_CH0_ENABLE		0x00010001UL
 #define DM_CM_INFO_CH1_ENABLE		0x00020001UL
-/** @brief DM_DTRAN_ADDR
+/* DM_DTRAN_ADDR */
- */
 #define DM_DTRAN_ADDR_WRITE_MASK	0xFFFFFFF8UL
-/** @brief DM_CM_DTRAN_CTRL
+/* DM_CM_DTRAN_CTRL */
- */
 #define DM_CM_DTRAN_CTRL_START		0x00000001UL
-/** @brief SYSC Registers
+/* SYSC Registers */
- */
 #if USE_MMC_CH == MMC_CH0
 #define CPG_MSTP_MMC		(BIT12)	/* SDHI2/MMC0 */
 #else /* USE_MMC_CH == MMC_CH0 */
 #define CPG_MSTP_MMC		(BIT11)	/* SDHI3/MMC1 */
 #endif /* USE_MMC_CH == MMC_CH0 */
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-/* ************************** FUNCTION PROTOTYPES ************************** */
-/* ********************************* CODE ********************************** */
 #endif /* EMMC_REGISTERS_H */
-/* ******************************** END ************************************ */
--- a/drivers/renesas/rcar/emmc/emmc_std.h
+++ b/drivers/renesas/rcar/emmc/emmc_std.h
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-/**
- * @file  emmc_std.h
- * @brief eMMC boot is expecting this header file
- *
- */
 #ifndef EMMC_STD_H
 #define EMMC_STD_H
 #include "emmc_hal.h"
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
 #ifndef FALSE
 #define FALSE	0U
 #endif
@@ -25,28 +16,23 @@
 #define TRUE	1U
 #endif
-/** @brief 64bit registers
+/* 64bit registers */
- **/
 #define SETR_64(r, v)			(*(volatile uint64_t *)(r) = (v))
 #define GETR_64(r)			(*(volatile uint64_t *)(r))
-/** @brief 32bit registers
+/* 32bit registers */
- **/
 #define SETR_32(r, v)			(*(volatile uint32_t *)(r) = (v))
 #define GETR_32(r)			(*(volatile uint32_t *)(r))
-/** @brief 16bit registers
+/* 16bit registers */
- */
 #define SETR_16(r, v)			(*(volatile uint16_t *)(r) = (v))
 #define GETR_16(r)			(*(volatile uint16_t *)(r))
-/** @brief 8bit registers
+/* 8bit registers */
- */
 #define SETR_8(r, v)			(*(volatile uint8_t *)(r) = (v))
 #define GETR_8(r)			(*(volatile uint8_t *)(r))
-/** @brief CSD register Macros
+/* CSD register Macros */
- */
 #define EMMC_GET_CID(x, y)	(emmc_bit_field(mmc_drv_obj.cid_data, (x), (y)))
 #define EMMC_CID_MID()			(EMMC_GET_CID(127, 120))
@@ -59,8 +45,7 @@
 #define EMMC_CID_MDT()			(EMMC_GET_CID(15, 8))
 #define EMMC_CID_CRC()			(EMMC_GET_CID(7, 1))
-/** @brief CSD register Macros
+/* CSD register Macros */
- */
 #define EMMC_GET_CSD(x, y)	(emmc_bit_field(mmc_drv_obj.csd_data, (x), (y)))
 #define EMMC_CSD_CSD_STRUCTURE()	(EMMC_GET_CSD(127, 126))
@@ -97,8 +82,7 @@
 #define EMMC_CSD_ECC()			(EMMC_GET_CSD(9, 8))
 #define EMMC_CSD_CRC()			(EMMC_GET_CSD(7, 1))
-/** @brief for sector access
+/* sector access */
- */
 #define EMMC_4B_BOUNDARY_CHECK_MASK	0x00000003
 #define EMMC_SECTOR_SIZE_SHIFT		9U	/* 512 = 2^9 */
 #define EMMC_SECTOR_SIZE		512
@@ -106,46 +90,44 @@
 #define EMMC_BLOCK_LENGTH_DW		128
 #define EMMC_BUF_SIZE_SHIFT		3U	/* 8byte = 2^3 */
-/** @brief eMMC specification clock
+/* eMMC specification clock */
- */
+#define EMMC_CLOCK_SPEC_400K		400000UL	 /* initialize clock 400KHz */
-#define EMMC_CLOCK_SPEC_400K                400000UL	 /**< initialize clock 400KHz */
+#define EMMC_CLOCK_SPEC_20M		20000000UL	 /* normal speed 20MHz */
-#define EMMC_CLOCK_SPEC_20M                 20000000UL	 /**< normal speed 20MHz */
+#define EMMC_CLOCK_SPEC_26M		26000000UL	 /* high speed 26MHz */
-#define EMMC_CLOCK_SPEC_26M                 26000000UL	 /**< high speed 26MHz */
+#define EMMC_CLOCK_SPEC_52M		52000000UL	 /* high speed 52MHz */
-#define EMMC_CLOCK_SPEC_52M                 52000000UL	 /**< high speed 52MHz */
+#define EMMC_CLOCK_SPEC_100M		100000000UL	 /* high speed 100MHz */
-#define EMMC_CLOCK_SPEC_100M                100000000UL	 /**< high speed 100MHz */
-/** @brief EMMC driver error code. (extended HAL_MEMCARD_RETURN)
+/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */
- */
 typedef enum {
-	EMMC_ERR = 0,				/**< unknown error */
+	EMMC_ERR = 0,				/* unknown error */
-	EMMC_SUCCESS,				/**< OK */
+	EMMC_SUCCESS,				/* OK */
-	EMMC_ERR_FROM_DMAC,			/**< DMAC allocation error */
+	EMMC_ERR_FROM_DMAC,			/* DMAC allocation error */
-	EMMC_ERR_FROM_DMAC_TRANSFER,		/**< DMAC transfer error */
+	EMMC_ERR_FROM_DMAC_TRANSFER,		/* DMAC transfer error */
-	EMMC_ERR_CARD_STATUS_BIT,		/**< card status error. Non-masked error bit was set in the card status */
+	EMMC_ERR_CARD_STATUS_BIT,		/* card status error */
-	EMMC_ERR_CMD_TIMEOUT,			/**< command timeout error */
+	EMMC_ERR_CMD_TIMEOUT,			/* command timeout error */
-	EMMC_ERR_DATA_TIMEOUT,			/**< data timeout error */
+	EMMC_ERR_DATA_TIMEOUT,			/* data timeout error */
-	EMMC_ERR_CMD_CRC,			/**< command CRC error */
+	EMMC_ERR_CMD_CRC,			/* command CRC error */
-	EMMC_ERR_DATA_CRC,			/**< data CRC error */
+	EMMC_ERR_DATA_CRC,			/* data CRC error */
-	EMMC_ERR_PARAM,				/**< parameter error */
+	EMMC_ERR_PARAM,				/* parameter error */
-	EMMC_ERR_RESPONSE,			/**< response error */
+	EMMC_ERR_RESPONSE,			/* response error */
-	EMMC_ERR_RESPONSE_BUSY,			/**< response busy error */
+	EMMC_ERR_RESPONSE_BUSY,			/* response busy error */
-	EMMC_ERR_TRANSFER,			/**< data transfer error */
+	EMMC_ERR_TRANSFER,			/* data transfer error */
-	EMMC_ERR_READ_SECTOR,			/**< read sector error */
+	EMMC_ERR_READ_SECTOR,			/* read sector error */
-	EMMC_ERR_WRITE_SECTOR,			/**< write sector error */
+	EMMC_ERR_WRITE_SECTOR,			/* write sector error */
-	EMMC_ERR_STATE,				/**< state error */
+	EMMC_ERR_STATE,				/* state error */
-	EMMC_ERR_TIMEOUT,			/**< timeout error */
+	EMMC_ERR_TIMEOUT,			/* timeout error */
-	EMMC_ERR_ILLEGAL_CARD,			/**< illegal card */
+	EMMC_ERR_ILLEGAL_CARD,			/* illegal card */
-	EMMC_ERR_CARD_BUSY,			/**< Busy state */
+	EMMC_ERR_CARD_BUSY,			/* Busy state */
-	EMMC_ERR_CARD_STATE,			/**< card state error */
+	EMMC_ERR_CARD_STATE,			/* card state error */
-	EMMC_ERR_SET_TRACE,			/**< trace information error */
+	EMMC_ERR_SET_TRACE,			/* trace information error */
-	EMMC_ERR_FROM_TIMER,			/**< Timer error */
+	EMMC_ERR_FROM_TIMER,			/* Timer error */
-	EMMC_ERR_FORCE_TERMINATE,		/**< Force terminate */
+	EMMC_ERR_FORCE_TERMINATE,		/* Force terminate */
-	EMMC_ERR_CARD_POWER,			/**< card power fail */
+	EMMC_ERR_CARD_POWER,			/* card power fail */
-	EMMC_ERR_ERASE_SECTOR,			/**< erase sector error */
+	EMMC_ERR_ERASE_SECTOR,			/* erase sector error */
-	EMMC_ERR_INFO2				    /**< exec cmd error info2 */
+	EMMC_ERR_INFO2				/* exec cmd error info2 */
 } EMMC_ERROR_CODE;
-/** @brief Function number */
+/* Function number */
 #define EMMC_FUNCNO_NONE				0U
 #define EMMC_FUNCNO_DRIVER_INIT				1U
 #define EMMC_FUNCNO_CARD_POWER_ON			2U
@@ -164,33 +146,36 @@ typedef enum {
 #define EMMC_FUNCNO_WRITE_SECTOR			15U
 #define EMMC_FUNCNO_ERASE_SECTOR			16U
 #define EMMC_FUNCNO_GET_PERTITION_ACCESS		17U
-/** @brief Response
+/*
+ * Response
+ * R1
+ * Type 'E' bit and bit14(must be 0). ignore bit22
 */
-/** R1 */
+#define EMMC_R1_ERROR_MASK			0xFDBFE080U
-#define EMMC_R1_ERROR_MASK                      0xFDBFE080U	/* Type 'E' bit and bit14(must be 0). ignore bit22 */
+/* Ignore bit23 (Not check CRC error) */
-#define EMMC_R1_ERROR_MASK_WITHOUT_CRC          (0xFD3FE080U)	/* Ignore bit23 (Not check CRC error) */
+#define EMMC_R1_ERROR_MASK_WITHOUT_CRC		(0xFD3FE080U)
 #define EMMC_R1_STATE_MASK			0x00001E00U	/* [12:9] */
 #define EMMC_R1_READY				0x00000100U	/* bit8 */
 #define EMMC_R1_STATE_SHIFT			9
-/** R4 */
+/* R4 */
 #define EMMC_R4_RCA_MASK			0xFFFF0000UL
 #define EMMC_R4_STATUS				0x00008000UL
-/** CSD */
+/* CSD */
 #define EMMC_TRANSPEED_FREQ_UNIT_MASK		0x07	/* bit[2:0] */
 #define EMMC_TRANSPEED_FREQ_UNIT_SHIFT		0
 #define EMMC_TRANSPEED_MULT_MASK		0x78	/* bit[6:3] */
 #define EMMC_TRANSPEED_MULT_SHIFT		3
-/** OCR */
+/* OCR */
 #define EMMC_HOST_OCR_VALUE			0x40FF8080
 #define EMMC_OCR_STATUS_BIT			0x80000000L	/* Card power up status bit */
 #define EMMC_OCR_ACCESS_MODE_MASK		0x60000000L	/* bit[30:29] */
 #define EMMC_OCR_ACCESS_MODE_SECT		0x40000000L
 #define EMMC_OCR_ACCESS_MODE_BYTE		0x00000000L
-/** EXT_CSD */
+/* EXT_CSD */
 #define EMMC_EXT_CSD_S_CMD_SET				504
 #define EMMC_EXT_CSD_INI_TIMEOUT_AP			241
 #define EMMC_EXT_CSD_PWR_CL_DDR_52_360			239
@@ -254,42 +239,50 @@ typedef enum {
 #define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V		0x08
 #define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK		0x0e
-/** SWITCH (CMD6) argument */
+/* SWITCH (CMD6) argument */
-#define	EXTCSD_ACCESS_BYTE	(BIT25|BIT24)
+#define EXTCSD_ACCESS_BYTE	(BIT25 | BIT24)
 #define EXTCSD_SET_BITS		BIT24
-#define	HS_TIMING_ADD		(185<<16)	/* H'b9 */
+#define HS_TIMING_ADD		(185 << 16)	/* H'b9 */
-#define	HS_TIMING_1			(1<<8)
+#define HS_TIMING_1		(1 << 8)
-#define	HS_TIMING_HS200		(2<<8)
+#define HS_TIMING_HS200		(2 << 8)
-#define	HS_TIMING_HS400		(3<<8)
+#define HS_TIMING_HS400		(3 << 8)
-#define	BUS_WIDTH_ADD		(183<<16)	/* H'b7 */
+#define BUS_WIDTH_ADD		(183 << 16)	/* H'b7 */
-#define	BUS_WIDTH_1			(0<<8)
+#define BUS_WIDTH_1		(0 << 8)
-#define	BUS_WIDTH_4			(1<<8)
+#define BUS_WIDTH_4		(1 << 8)
-#define	BUS_WIDTH_8			(2<<8)
+#define BUS_WIDTH_8		(2 << 8)
-#define	BUS_WIDTH_4DDR		(5<<8)
+#define BUS_WIDTH_4DDR		(5 << 8)
-#define	BUS_WIDTH_8DDR		(6<<8)
+#define BUS_WIDTH_8DDR		(6 << 8)
-#define EMMC_SWITCH_HS_TIMING           (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1)		/**< H'03b90100 */
+#define EMMC_SWITCH_HS_TIMING		(EXTCSD_ACCESS_BYTE | HS_TIMING_ADD |\
-#define	EMMC_SWITCH_HS_TIMING_OFF	    (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD)					/**< H'03b90000 */
+					 HS_TIMING_1)		/* H'03b90100 */
+#define EMMC_SWITCH_HS_TIMING_OFF	(EXTCSD_ACCESS_BYTE |\
-#define EMMC_SWITCH_BUS_WIDTH_1         (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1)		/**< H'03b70000 */
+					 HS_TIMING_ADD)		/* H'03b90000 */
-#define EMMC_SWITCH_BUS_WIDTH_4         (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4)		/**< H'03b70100 */
-#define EMMC_SWITCH_BUS_WIDTH_8         (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8)		/**< H'03b70200 */
+#define EMMC_SWITCH_BUS_WIDTH_1		(EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
-#define	EMMC_SWITCH_BUS_WIDTH_4DDR      (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4DDR)	/**< H'03b70500 */
+					 BUS_WIDTH_1)		/* H'03b70000 */
-#define	EMMC_SWITCH_BUS_WIDTH_8DDR      (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8DDR)	/**< H'03b70600 */
+#define EMMC_SWITCH_BUS_WIDTH_4		(EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
-#define EMMC_SWITCH_PARTITION_CONFIG    0x03B30000UL	/**< Partition config = 0x00 */
+					 BUS_WIDTH_4)		/* H'03b70100 */
+#define EMMC_SWITCH_BUS_WIDTH_8		(EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+					 BUS_WIDTH_8)		/* H'03b70200 */
+#define EMMC_SWITCH_BUS_WIDTH_4DDR	(EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+					 BUS_WIDTH_4DDR)	/* H'03b70500 */
+#define EMMC_SWITCH_BUS_WIDTH_8DDR	(EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+					 BUS_WIDTH_8DDR)	/* H'03b70600 */
+/* Partition config = 0x00 */
+#define EMMC_SWITCH_PARTITION_CONFIG	0x03B30000UL
 #define TIMING_HIGH_SPEED		1UL
 #define EMMC_BOOT_PARTITION_EN_MASK	0x38U
 #define EMMC_BOOT_PARTITION_EN_SHIFT	3U
-/** Bus width */
+/* Bus width */
 #define EMMC_BUSWIDTH_1BIT		CE_CMD_SET_DATW_1BIT
 #define EMMC_BUSWIDTH_4BIT		CE_CMD_SET_DATW_4BIT
 #define EMMC_BUSWIDTH_8BIT		CE_CMD_SET_DATW_8BIT
-/** for st_mmc_base */
+/* for st_mmc_base */
 #define EMMC_MAX_RESPONSE_LENGTH	17
 #define EMMC_MAX_CID_LENGTH		16
 #define EMMC_MAX_CSD_LENGTH		16
@@ -297,29 +290,24 @@ typedef enum {
 #define EMMC_RES_REG_ALIGNED		4U
 #define EMMC_BUF_REG_ALIGNED		8U
-/** @brief for TAAC mask
+/* TAAC mask */
- */
 #define TAAC_TIME_UNIT_MASK		(0x07)
 #define TAAC_MULTIPLIER_FACTOR_MASK	(0x0F)
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+/* Partition id */
-/** @brief Partition id
- */
 typedef enum {
-	PARTITION_ID_USER = 0x0,    /**< User Area */
+	PARTITION_ID_USER = 0x0,	/* User Area */
-	PARTITION_ID_BOOT_1 = 0x1,  /**< boot partition 1 */
+	PARTITION_ID_BOOT_1 = 0x1,	/* boot partition 1 */
-	PARTITION_ID_BOOT_2 = 0x2,  /**< boot partition 2 */
+	PARTITION_ID_BOOT_2 = 0x2,	/* boot partition 2 */
-	PARTITION_ID_RPMB = 0x3,    /**< Replay Protected Memory Block */
+	PARTITION_ID_RPMB = 0x3,	/* Replay Protected Memory Block */
-	PARTITION_ID_GP_1 = 0x4,    /**< General Purpose partition 1 */
+	PARTITION_ID_GP_1 = 0x4,	/* General Purpose partition 1 */
-	PARTITION_ID_GP_2 = 0x5,    /**< General Purpose partition 2 */
+	PARTITION_ID_GP_2 = 0x5,	/* General Purpose partition 2 */
-	PARTITION_ID_GP_3 = 0x6,    /**< General Purpose partition 3 */
+	PARTITION_ID_GP_3 = 0x6,	/* General Purpose partition 3 */
-	PARTITION_ID_GP_4 = 0x7,    /**< General Purpose partition 4 */
+	PARTITION_ID_GP_4 = 0x7,	/* General Purpose partition 4 */
-	PARTITION_ID_MASK = 0x7	    /**< [2:0] */
+	PARTITION_ID_MASK = 0x7		/* [2:0] */
 } EMMC_PARTITION_ID;
-/** @brief card state in R1 response [12:9]
+/* card state in R1 response [12:9] */
- */
 typedef enum {
 	EMMC_R1_STATE_IDLE = 0,
 	EMMC_R1_STATE_READY,
@@ -349,126 +337,139 @@ typedef enum {
 	ESTATE_END
 } EMMC_INT_STATE;
-/** @brief eMMC boot driver error information
+/* eMMC boot driver error information */
- */
 typedef struct {
-	uint16_t num;		  /**< error no */
+	uint16_t num;			/* error no */
-	uint16_t code;		  /**< error code */
+	uint16_t code;			/* error code */
-	volatile uint32_t info1;  /**< SD_INFO1 register value. (hardware dependence) */
-	volatile uint32_t info2;  /**< SD_INFO2 register value. (hardware dependence) */
+	volatile uint32_t info1;	/* SD_INFO1. (hw dependent) */
-	volatile uint32_t status1;/**< SD_ERR_STS1 register value. (hardware dependence) */
+	volatile uint32_t info2;	/* SD_INFO2. (hw dependent) */
-	volatile uint32_t status2;/**< SD_ERR_STS2 register value. (hardware dependence) */
+	volatile uint32_t status1;	/* SD_ERR_STS1. (hw dependent) */
-	volatile uint32_t dm_info1;/**< DM_CM_INFO1 register value. (hardware dependence) */
+	volatile uint32_t status2;	/* SD_ERR_STS2. (hw dependent) */
-	volatile uint32_t dm_info2;/**< DM_CM_INFO2 register value. (hardware dependence) */
+	volatile uint32_t dm_info1;	/* DM_CM_INFO1. (hw dependent) */
+	volatile uint32_t dm_info2;	/* DM_CM_INFO2. (hw dependent) */
 } st_error_info;
-/** @brief Command information
+/* Command information */
- */
 typedef struct {
-	HAL_MEMCARD_COMMAND cmd;	/**< Command information */
+	HAL_MEMCARD_COMMAND cmd;	/* Command information */
-	uint32_t arg;			  /**< argument */
+	uint32_t arg;			/* argument */
-	HAL_MEMCARD_OPERATION dir;	/**< direction */
+	HAL_MEMCARD_OPERATION dir;	/* direction */
-	uint32_t hw;			  /**< H/W dependence. SD_CMD register value. */
+	uint32_t hw;			/* SD_CMD register value. */
 } st_command_info;
-/** @brief MMC driver base
+/* MMC driver base */
- */
 typedef struct {
-	st_error_info error_info;	/**< error information */
+	st_error_info error_info;	/* error information */
-	st_command_info cmd_info;	/**< command information */
+	st_command_info cmd_info;	/* command information */
 	/* for data transfer */
-	uint32_t *buff_address_virtual;	   /**< Dest or Src buff */
+	uint32_t *buff_address_virtual;		/* Dest or Src buff */
-	uint32_t *buff_address_physical;   /**< Dest or Src buff */
+	uint32_t *buff_address_physical;	/* Dest or Src buff */
-	HAL_MEMCARD_DATA_WIDTH bus_width;
+	HAL_MEMCARD_DATA_WIDTH bus_width;	/* bus width */
-					/**< bus width */
-	uint32_t trans_size;		  /**< transfer size for this command */
+	uint32_t trans_size;		/* transfer size for this command */
-	uint32_t remain_size;		  /**< remain size for this command */
+	uint32_t remain_size;		/* remain size for this command */
-	uint32_t response_length;	  /**< response length for this command */
+	uint32_t response_length;	/* response length for this command */
-	uint32_t sector_size;		   /**< sector_size */
+	uint32_t sector_size;		/* sector_size */
 	/* clock */
-	uint32_t base_clock;		  /**< MMC host controller clock */
+	uint32_t base_clock;		/* MMC host controller clock */
-	uint32_t max_freq;		  /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */
+	/*
-	uint32_t request_freq;		  /**< request freq [Hz] (400K, 26MHz, 52MHz, etc) */
+	 * Max freq (Card Spec)[Hz]. It changes dynamically by CSD and
-	uint32_t current_freq;		  /**< current MMC clock[Hz] (the closest frequency supported by HW) */
+	 * EXT_CSD.
+	 */
+	uint32_t max_freq;
+	/* request freq [Hz] (400K, 26MHz, 52MHz, etc) */
+	uint32_t request_freq;
+	/* current MMC clock[Hz] (the closest frequency supported by HW) */
+	uint32_t current_freq;
 	/* state flag */
+	/* presence status of the memory card */
 	HAL_MEMCARD_PRESENCE_STATUS card_present;
-						/**< presence status of the memory card */
-	uint32_t card_power_enable;		  /**< True : Power ON */
+	uint32_t card_power_enable;
-	uint32_t clock_enable;			  /**< True : Clock ON */
+	uint32_t clock_enable;
-	uint32_t initialize;			  /**< True : initialize complete. */
+	/* True : initialize complete. */
-	uint32_t access_mode;			  /**< True : sector access, FALSE : byte access */
+	uint32_t initialize;
-	uint32_t mount;				  /**< True : mount complete. */
+	/* True : sector access, FALSE : byte access */
-	uint32_t selected;			  /**< True : selected card. */
+	uint32_t access_mode;
+	/* True : mount complete. */
+	uint32_t mount;
+	/* True : selected card. */
+	uint32_t selected;
+	/* 0: DMA, 1:PIO */
 	HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode;
-						    /**< 0: DMA, 1:PIO */
-	uint32_t image_num;			  /**< loaded ISSW image No. ISSW have copy image. */
+	/* loaded ISSW image No. ISSW have copy image. */
-	EMMC_R1_STATE current_state;		/**< card state */
+	uint32_t image_num;
-	volatile uint32_t during_cmd_processing;  /**< True : during command processing */
+	/* card state */
-	volatile uint32_t during_transfer;	  /**< True : during transfer */
+	EMMC_R1_STATE current_state;
-	volatile uint32_t during_dma_transfer;	  /**< True : during transfer (DMA)*/
+	/* True : during command processing */
-	volatile uint32_t dma_error_flag;	  /**< True : occurred DMAC error */
+	volatile uint32_t during_cmd_processing;
-	volatile uint32_t force_terminate;	  /**< force terminate flag */
+	/* True : during transfer */
-	volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */
+	volatile uint32_t during_transfer;
+	/* True : during transfer (DMA) */
+	volatile uint32_t during_dma_transfer;
+	/* True : occurred DMAC error */
+	volatile uint32_t dma_error_flag;
+	/* force terminate flag */
+	volatile uint32_t force_terminate;
+	/* state machine blocking flag : True or False */
+	volatile uint32_t state_machine_blocking;
+	/* True : get partition access processing */
 	volatile uint32_t get_partition_access_flag;
-						  /**< True : get partition access processing */
-	EMMC_PARTITION_ID boot_partition_en;	/**< Boot partition */
+	EMMC_PARTITION_ID boot_partition_en;	/* Boot partition */
-	EMMC_PARTITION_ID partition_access;	/**< Current access partition */
+	EMMC_PARTITION_ID partition_access;	/* Current access partition */
 	/* timeout */
-	uint32_t hs_timing;			/**< high speed */
+	uint32_t hs_timing;
-	/* timeout */
+	/* read and write data timeout */
-	uint32_t data_timeout;			  /**< read and write data timeout.*/
+	uint32_t data_timeout;
 	/* retry */
-	uint32_t retries_after_fail;  /**< how many times to try after fail, for instance sending command */
+	uint32_t retries_after_fail;
 	/* interrupt */
-	volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */
+	volatile uint32_t int_event1;	/* interrupt SD_INFO1 Event */
-	volatile uint32_t int_event2;	  /**< interrupt SD_INFO2 Event */
+	volatile uint32_t int_event2;	/* interrupt SD_INFO2 Event */
-	volatile uint32_t dm_event1;  /**< interrupt DM_CM_INFO1 Event */
+	volatile uint32_t dm_event1;	/* interrupt DM_CM_INFO1 Event */
-	volatile uint32_t dm_event2;	  /**< interrupt DM_CM_INFO2 Event */
+	volatile uint32_t dm_event2;	/* interrupt DM_CM_INFO2 Event */
 	/* response */
-	uint32_t *response;	      /**< pointer to buffer for executing command. */
+	uint32_t *response;		/* buffer ptr for executing command. */
-	uint32_t r1_card_status;      /**< R1 response data */
+	uint32_t r1_card_status;	/* R1 response data */
-	uint32_t r3_ocr;	      /**< R3 response data */
+	uint32_t r3_ocr;		/* R3 response data */
-	uint32_t r4_resp;	      /**< R4 response data */
+	uint32_t r4_resp;		/* R4 response data */
-	uint32_t r5_resp;	      /**< R5 response data */
+	uint32_t r5_resp;		/* R5 response data */
+	/* True : clock mode is low. (MMC clock = Max26MHz) */
 	uint32_t low_clock_mode_enable;
-				      /**< True : clock mode is low. (MMC clock = Max26MHz) */
 	uint32_t reserved2;
 	uint32_t reserved3;
 	uint32_t reserved4;
 	/* CSD registers (4byte align) */
-	uint8_t csd_data[EMMC_MAX_CSD_LENGTH]		      /**< CSD */
+	uint8_t csd_data[EMMC_MAX_CSD_LENGTH]			/* CSD */
 	    __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
 	/* CID registers (4byte align) */
-	uint8_t cid_data[EMMC_MAX_CID_LENGTH]		      /**< CID */
+	uint8_t cid_data[EMMC_MAX_CID_LENGTH]			/* CID */
 	    __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
 	/* EXT CSD registers (8byte align) */
-	uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH]	      /**< EXT_CSD */
+	uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH]		/* EXT_CSD */
 	    __attribute__ ((aligned(EMMC_BUF_REG_ALIGNED)));
 	/* Response registers (4byte align) */
-	uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH]	      /**< other response */
+	uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH]		/* other response */
 	    __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
 } st_mmc_base;
 typedef int (*func) (void);
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-/* ************************** FUNCTION PROTOTYPES ************************** */
 uint32_t emmc_get_csd_time(void);
 #define MMC_DEBUG
-/* ********************************* CODE ********************************** */
-/* ******************************** END ************************************ */
 #endif /* EMMC_STD_H */
--- a/drivers/renesas/rcar/emmc/emmc_utility.c
+++ b/drivers/renesas/rcar/emmc/emmc_utility.c
 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
@@ -7,10 +7,10 @@
 #include <common/debug.h>
 #include "emmc_config.h"
+#include "emmc_def.h"
 #include "emmc_hal.h"
-#include "emmc_std.h"
 #include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
 static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1] = {
 	0x00000000,		/* CMD0 */
@@ -97,8 +97,8 @@ uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom)
 		value =
 		    (uint32_t) ((data[index_top] << 24) |
 				(data[index_top + 1] << 16) |
-				(data[index_top + 2] << 8) | data[index_top +
+				(data[index_top + 2] << 8) |
-								  3]);
+				data[index_top + 3]);
 	}
 	value = ((value >> (bottom & 0x07)) & ((1 << (top - bottom + 1)) - 1));