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adam.huang
Arm Trusted Firmware
Commits
a51443fa
Unverified
Commit
a51443fa
authored
Oct 18, 2018
by
Soby Mathew
Committed by
GitHub
Oct 18, 2018
Browse files
Merge pull request #1582 from ldts/rcar_gen3/upstream
rcar_gen3: initial support
parents
0059be2d
84433c50
Changes
147
Show whitespace changes
Inline
Side-by-side
drivers/staging/renesas/rcar/ddr/dram_sub_func.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <mmio.h>
#include <debug.h>
#include "dram_sub_func.h"
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_H3 (0x00004F00U)
/* R-Car H3 */
#define PRR_PRODUCT_M3 (0x00005200U)
/* R-Car M3 */
#define PRR_PRODUCT_M3N (0x00005500U)
/* R-Car M3N */
#define PRR_PRODUCT_E3 (0x00005700U)
/* R-Car E3 */
#define PRR_PRODUCT_V3H (0x00005600U)
/* R-Car V3H */
#if RCAR_SYSTEM_SUSPEND
#include "iic_dvfs.h"
#define DRAM_BACKUP_GPIO_USE (0)
#if PMIC_ROHM_BD9571
#define PMIC_BKUP_MODE_CNT (0x20U)
#define PMIC_QLLM_CNT (0x27U)
#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U))
#define BIT_QLLM_DDR0_EN ((uint8_t)(1U << 0U))
#define BIT_QLLM_DDR1_EN ((uint8_t)(1U << 1U))
#endif
#define GPIO_OUTDT1 (0xE6051008U)
#define GPIO_INDT1 (0xE605100CU)
#define GPIO_OUTDT3 (0xE6053008U)
#define GPIO_INDT3 (0xE605300CU)
#define GPIO_OUTDT6 (0xE6055408U)
#define GPIO_INDT6 (0xE605540CU)
#if DRAM_BACKUP_GPIO_USE == 1
#define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U)
/* GP1_9 (BKUP_REQB) */
#define GPIO_BKUP_REQB_SHIFT_EBISU (14U)
/* GP6_14(BKUP_REQB) */
#define GPIO_BKUP_REQB_SHIFT_CONDOR (1U)
/* GP3_1 (BKUP_REQB) */
#endif
#define GPIO_BKUP_TRG_SHIFT_SALVATOR (8U)
/* GP1_8 (BKUP_TRG) */
#define GPIO_BKUP_TRG_SHIFT_EBISU (13U)
/* GP6_13(BKUP_TRG) */
#define GPIO_BKUP_TRG_SHIFT_CONDOR (0U)
/* GP3_0 (BKUP_TRG) */
#define DRAM_BKUP_TRG_LOOP_CNT (1000U)
#endif
void
rcar_dram_get_boot_status
(
uint32_t
*
status
)
{
#if RCAR_SYSTEM_SUSPEND
uint32_t
shift
=
GPIO_BKUP_TRG_SHIFT_SALVATOR
;
uint32_t
gpio
=
GPIO_INDT1
;
uint32_t
reg
,
product
;
product
=
mmio_read_32
(
PRR
)
&
PRR_PRODUCT_MASK
;
if
(
product
==
PRR_PRODUCT_V3H
)
{
shift
=
GPIO_BKUP_TRG_SHIFT_CONDOR
;
gpio
=
GPIO_INDT3
;
}
else
if
(
product
==
PRR_PRODUCT_E3
)
{
shift
=
GPIO_BKUP_TRG_SHIFT_EBISU
;
gpio
=
GPIO_INDT6
;
}
reg
=
mmio_read_32
(
gpio
)
&
(
1U
<<
shift
);
*
status
=
reg
?
DRAM_BOOT_STATUS_WARM
:
DRAM_BOOT_STATUS_COLD
;
#else
*
status
=
DRAM_BOOT_STATUS_COLD
;
#endif
}
int32_t
rcar_dram_update_boot_status
(
uint32_t
status
)
{
int32_t
ret
=
0
;
#if RCAR_SYSTEM_SUSPEND
#if PMIC_ROHM_BD9571
#if DRAM_BACKUP_GPIO_USE == 0
uint8_t
mode
=
0U
;
#else
uint32_t
reqb
,
outd
;
#endif
uint8_t
qllm
=
0
;
#endif
uint32_t
i
,
product
,
trg
,
gpio
;
product
=
mmio_read_32
(
PRR
)
&
PRR_PRODUCT_MASK
;
if
(
product
==
PRR_PRODUCT_V3H
)
{
#if DRAM_BACKUP_GPIO_USE == 1
reqb
=
GPIO_BKUP_REQB_SHIFT_CONDOR
;
outd
=
GPIO_OUTDT3
;
#endif
trg
=
GPIO_BKUP_TRG_SHIFT_CONDOR
;
gpio
=
GPIO_INDT3
;
}
else
if
(
product
==
PRR_PRODUCT_E3
)
{
#if DRAM_BACKUP_GPIO_USE == 1
reqb
=
GPIO_BKUP_REQB_SHIFT_EBISU
;
outd
=
GPIO_OUTDT6
;
#endif
trg
=
GPIO_BKUP_TRG_SHIFT_EBISU
;
gpio
=
GPIO_INDT6
;
}
else
{
#if DRAM_BACKUP_GPIO_USE == 1
reqb
=
GPIO_BKUP_REQB_SHIFT_SALVATOR
;
outd
=
GPIO_OUTDT1
;
#endif
trg
=
GPIO_BKUP_TRG_SHIFT_SALVATOR
;
gpio
=
GPIO_INDT1
;
}
if
(
status
!=
DRAM_BOOT_STATUS_WARM
)
goto
cold
;
#if DRAM_BACKUP_GPIO_USE==1
mmio_setbits_32
(
outd
,
1U
<<
reqb
);
#else
#if PMIC_ROHM_BD9571
if
(
rcar_iic_dvfs_receive
(
PMIC
,
PMIC_BKUP_MODE_CNT
,
&
mode
))
{
ERROR
(
"BKUP mode cnt READ ERROR.
\n
"
);
return
DRAM_UPDATE_STATUS_ERR
;
}
mode
&=
~
BIT_BKUP_CTRL_OUT
;
if
(
rcar_iic_dvfs_send
(
PMIC
,
PMIC_BKUP_MODE_CNT
,
mode
))
{
ERROR
(
"BKUP mode cnt WRITE ERROR. value = %d
\n
"
,
mode
);
return
DRAM_UPDATE_STATUS_ERR
;
}
#endif
#endif
for
(
i
=
0
;
i
<
DRAM_BKUP_TRG_LOOP_CNT
;
i
++
)
{
if
(
mmio_read_32
(
gpio
)
&
(
1U
<<
trg
))
continue
;
goto
cold
;
}
ERROR
(
"
\n
Warm booting Error...
\n
"
" The potential of BKUP_TRG did not switch "
"to Low.
\n
If you expect the operation of "
"cold boot,
\n
check the board configuration"
" (ex, Dip-SW) and/or the H/W failure.
\n
"
);
return
DRAM_UPDATE_STATUS_ERR
;
cold:
#if PMIC_ROHM_BD9571
if
(
ret
)
return
ret
;
qllm
=
(
BIT_QLLM_DDR0_EN
|
BIT_QLLM_DDR1_EN
);
if
(
rcar_iic_dvfs_send
(
PMIC
,
PMIC_QLLM_CNT
,
qllm
))
{
ERROR
(
"QLLM cnt WRITE ERROR. value = %d
\n
"
,
qllm
);
ret
=
DRAM_UPDATE_STATUS_ERR
;
}
#endif
#endif
return
ret
;
}
drivers/staging/renesas/rcar/ddr/dram_sub_func.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef DRAM_SUB_FUNC_H_
#define DRAM_SUB_FUNC_H_
#define DRAM_UPDATE_STATUS_ERR (-1)
#define DRAM_BOOT_STATUS_COLD (0)
#define DRAM_BOOT_STATUS_WARM (1)
int32_t
rcar_dram_update_boot_status
(
uint32_t
status
);
void
rcar_dram_get_boot_status
(
uint32_t
*
status
);
#endif
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
/* for uint32_t */
#include <mmio.h>
#include "pfc_init_e3.h"
#include "rcar_def.h"
/* GPIO base address */
#define GPIO_BASE (0xE6050000U)
/* GPIO registers */
#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U)
#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U)
#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U)
#define GPIO_INDT0 (GPIO_BASE + 0x000CU)
#define GPIO_INTDT0 (GPIO_BASE + 0x0010U)
#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U)
#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U)
#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU)
#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U)
#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U)
#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U)
#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U)
#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU)
#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U)
#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U)
#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U)
#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU)
#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U)
#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U)
#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
#define GPIO_INTDT1 (GPIO_BASE + 0x1010U)
#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U)
#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U)
#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU)
#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U)
#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U)
#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U)
#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U)
#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU)
#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U)
#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U)
#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U)
#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU)
#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U)
#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U)
#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U)
#define GPIO_INDT2 (GPIO_BASE + 0x200CU)
#define GPIO_INTDT2 (GPIO_BASE + 0x2010U)
#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U)
#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U)
#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU)
#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U)
#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U)
#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U)
#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U)
#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU)
#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U)
#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U)
#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U)
#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU)
#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U)
#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U)
#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
#define GPIO_INTDT3 (GPIO_BASE + 0x3010U)
#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U)
#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U)
#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU)
#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U)
#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U)
#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U)
#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U)
#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU)
#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U)
#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U)
#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U)
#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU)
#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U)
#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U)
#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U)
#define GPIO_INDT4 (GPIO_BASE + 0x400CU)
#define GPIO_INTDT4 (GPIO_BASE + 0x4010U)
#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U)
#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U)
#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU)
#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U)
#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U)
#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U)
#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U)
#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU)
#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U)
#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U)
#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U)
#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU)
#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U)
#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U)
#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U)
#define GPIO_INDT5 (GPIO_BASE + 0x500CU)
#define GPIO_INTDT5 (GPIO_BASE + 0x5010U)
#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U)
#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U)
#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU)
#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U)
#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U)
#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U)
#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U)
#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU)
#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U)
#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U)
#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U)
#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU)
#define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U)
#define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U)
#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
#define GPIO_INTDT6 (GPIO_BASE + 0x5410U)
#define GPIO_INTCLR6 (GPIO_BASE + 0x5414U)
#define GPIO_INTMSK6 (GPIO_BASE + 0x5418U)
#define GPIO_MSKCLR6 (GPIO_BASE + 0x541CU)
#define GPIO_POSNEG6 (GPIO_BASE + 0x5420U)
#define GPIO_EDGLEVEL6 (GPIO_BASE + 0x5424U)
#define GPIO_FILONOFF6 (GPIO_BASE + 0x5428U)
#define GPIO_INTMSKS6 (GPIO_BASE + 0x5438U)
#define GPIO_MSKCLRS6 (GPIO_BASE + 0x543CU)
#define GPIO_OUTDTSEL6 (GPIO_BASE + 0x5440U)
#define GPIO_OUTDTH6 (GPIO_BASE + 0x5444U)
#define GPIO_OUTDTL6 (GPIO_BASE + 0x5448U)
#define GPIO_BOTHEDGE6 (GPIO_BASE + 0x544CU)
/* Pin functon base address */
#define PFC_BASE (0xE6060000U)
/* Pin functon registers */
#define PFC_PMMR (PFC_BASE + 0x0000U)
#define PFC_GPSR0 (PFC_BASE + 0x0100U)
#define PFC_GPSR1 (PFC_BASE + 0x0104U)
#define PFC_GPSR2 (PFC_BASE + 0x0108U)
#define PFC_GPSR3 (PFC_BASE + 0x010CU)
#define PFC_GPSR4 (PFC_BASE + 0x0110U)
#define PFC_GPSR5 (PFC_BASE + 0x0114U)
#define PFC_GPSR6 (PFC_BASE + 0x0118U)
#define PFC_IPSR0 (PFC_BASE + 0x0200U)
#define PFC_IPSR1 (PFC_BASE + 0x0204U)
#define PFC_IPSR2 (PFC_BASE + 0x0208U)
#define PFC_IPSR3 (PFC_BASE + 0x020CU)
#define PFC_IPSR4 (PFC_BASE + 0x0210U)
#define PFC_IPSR5 (PFC_BASE + 0x0214U)
#define PFC_IPSR6 (PFC_BASE + 0x0218U)
#define PFC_IPSR7 (PFC_BASE + 0x021CU)
#define PFC_IPSR8 (PFC_BASE + 0x0220U)
#define PFC_IPSR9 (PFC_BASE + 0x0224U)
#define PFC_IPSR10 (PFC_BASE + 0x0228U)
#define PFC_IPSR11 (PFC_BASE + 0x022CU)
#define PFC_IPSR12 (PFC_BASE + 0x0230U)
#define PFC_IPSR13 (PFC_BASE + 0x0234U)
#define PFC_IPSR14 (PFC_BASE + 0x0238U)
#define PFC_IPSR15 (PFC_BASE + 0x023CU)
#define PFC_IOCTRL30 (PFC_BASE + 0x0380U)
#define PFC_IOCTRL32 (PFC_BASE + 0x0388U)
#define PFC_IOCTRL40 (PFC_BASE + 0x03C0U)
#define PFC_PUEN0 (PFC_BASE + 0x0400U)
#define PFC_PUEN1 (PFC_BASE + 0x0404U)
#define PFC_PUEN2 (PFC_BASE + 0x0408U)
#define PFC_PUEN3 (PFC_BASE + 0x040CU)
#define PFC_PUEN4 (PFC_BASE + 0x0410U)
#define PFC_PUEN5 (PFC_BASE + 0x0414U)
#define PFC_PUD0 (PFC_BASE + 0x0440U)
#define PFC_PUD1 (PFC_BASE + 0x0444U)
#define PFC_PUD2 (PFC_BASE + 0x0448U)
#define PFC_PUD3 (PFC_BASE + 0x044CU)
#define PFC_PUD4 (PFC_BASE + 0x0450U)
#define PFC_PUD5 (PFC_BASE + 0x0454U)
#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U)
#define PFC_MOD_SEL1 (PFC_BASE + 0x0504U)
#define GPSR0_SDA4 ((uint32_t)1U << 17U)
#define GPSR0_SCL4 ((uint32_t)1U << 16U)
#define GPSR0_D15 ((uint32_t)1U << 15U)
#define GPSR0_D14 ((uint32_t)1U << 14U)
#define GPSR0_D13 ((uint32_t)1U << 13U)
#define GPSR0_D12 ((uint32_t)1U << 12U)
#define GPSR0_D11 ((uint32_t)1U << 11U)
#define GPSR0_D10 ((uint32_t)1U << 10U)
#define GPSR0_D9 ((uint32_t)1U << 9U)
#define GPSR0_D8 ((uint32_t)1U << 8U)
#define GPSR0_D7 ((uint32_t)1U << 7U)
#define GPSR0_D6 ((uint32_t)1U << 6U)
#define GPSR0_D5 ((uint32_t)1U << 5U)
#define GPSR0_D4 ((uint32_t)1U << 4U)
#define GPSR0_D3 ((uint32_t)1U << 3U)
#define GPSR0_D2 ((uint32_t)1U << 2U)
#define GPSR0_D1 ((uint32_t)1U << 1U)
#define GPSR0_D0 ((uint32_t)1U << 0U)
#define GPSR1_WE0 ((uint32_t)1U << 22U)
#define GPSR1_CS0 ((uint32_t)1U << 21U)
#define GPSR1_CLKOUT ((uint32_t)1U << 20U)
#define GPSR1_A19 ((uint32_t)1U << 19U)
#define GPSR1_A18 ((uint32_t)1U << 18U)
#define GPSR1_A17 ((uint32_t)1U << 17U)
#define GPSR1_A16 ((uint32_t)1U << 16U)
#define GPSR1_A15 ((uint32_t)1U << 15U)
#define GPSR1_A14 ((uint32_t)1U << 14U)
#define GPSR1_A13 ((uint32_t)1U << 13U)
#define GPSR1_A12 ((uint32_t)1U << 12U)
#define GPSR1_A11 ((uint32_t)1U << 11U)
#define GPSR1_A10 ((uint32_t)1U << 10U)
#define GPSR1_A9 ((uint32_t)1U << 9U)
#define GPSR1_A8 ((uint32_t)1U << 8U)
#define GPSR1_A7 ((uint32_t)1U << 7U)
#define GPSR1_A6 ((uint32_t)1U << 6U)
#define GPSR1_A5 ((uint32_t)1U << 5U)
#define GPSR1_A4 ((uint32_t)1U << 4U)
#define GPSR1_A3 ((uint32_t)1U << 3U)
#define GPSR1_A2 ((uint32_t)1U << 2U)
#define GPSR1_A1 ((uint32_t)1U << 1U)
#define GPSR1_A0 ((uint32_t)1U << 0U)
#define GPSR2_BIT27_REVERCED ((uint32_t)1U << 27U)
#define GPSR2_BIT26_REVERCED ((uint32_t)1U << 26U)
#define GPSR2_EX_WAIT0 ((uint32_t)1U << 25U)
#define GPSR2_RD_WR ((uint32_t)1U << 24U)
#define GPSR2_RD ((uint32_t)1U << 23U)
#define GPSR2_BS ((uint32_t)1U << 22U)
#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 21U)
#define GPSR2_AVB_TXCREFCLK ((uint32_t)1U << 20U)
#define GPSR2_AVB_RD3 ((uint32_t)1U << 19U)
#define GPSR2_AVB_RD2 ((uint32_t)1U << 18U)
#define GPSR2_AVB_RD1 ((uint32_t)1U << 17U)
#define GPSR2_AVB_RD0 ((uint32_t)1U << 16U)
#define GPSR2_AVB_RXC ((uint32_t)1U << 15U)
#define GPSR2_AVB_RX_CTL ((uint32_t)1U << 14U)
#define GPSR2_RPC_RESET ((uint32_t)1U << 13U)
#define GPSR2_RPC_RPC_INT ((uint32_t)1U << 12U)
#define GPSR2_QSPI1_SSL ((uint32_t)1U << 11U)
#define GPSR2_QSPI1_IO3 ((uint32_t)1U << 10U)
#define GPSR2_QSPI1_IO2 ((uint32_t)1U << 9U)
#define GPSR2_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
#define GPSR2_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
#define GPSR2_QSPI1_SPCLK ((uint32_t)1U << 6U)
#define GPSR2_QSPI0_SSL ((uint32_t)1U << 5U)
#define GPSR2_QSPI0_IO3 ((uint32_t)1U << 4U)
#define GPSR2_QSPI0_IO2 ((uint32_t)1U << 3U)
#define GPSR2_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
#define GPSR2_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
#define GPSR2_QSPI0_SPCLK ((uint32_t)1U << 0U)
#define GPSR3_SD1_WP ((uint32_t)1U << 15U)
#define GPSR3_SD1_CD ((uint32_t)1U << 14U)
#define GPSR3_SD0_WP ((uint32_t)1U << 13U)
#define GPSR3_SD0_CD ((uint32_t)1U << 12U)
#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U)
#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U)
#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U)
#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U)
#define GPSR3_SD1_CMD ((uint32_t)1U << 7U)
#define GPSR3_SD1_CLK ((uint32_t)1U << 6U)
#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U)
#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U)
#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U)
#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U)
#define GPSR3_SD0_CMD ((uint32_t)1U << 1U)
#define GPSR3_SD0_CLK ((uint32_t)1U << 0U)
#define GPSR4_SD3_DS ((uint32_t)1U << 10U)
#define GPSR4_SD3_DAT7 ((uint32_t)1U << 9U)
#define GPSR4_SD3_DAT6 ((uint32_t)1U << 8U)
#define GPSR4_SD3_DAT5 ((uint32_t)1U << 7U)
#define GPSR4_SD3_DAT4 ((uint32_t)1U << 6U)
#define GPSR4_SD3_DAT3 ((uint32_t)1U << 5U)
#define GPSR4_SD3_DAT2 ((uint32_t)1U << 4U)
#define GPSR4_SD3_DAT1 ((uint32_t)1U << 3U)
#define GPSR4_SD3_DAT0 ((uint32_t)1U << 2U)
#define GPSR4_SD3_CMD ((uint32_t)1U << 1U)
#define GPSR4_SD3_CLK ((uint32_t)1U << 0U)
#define GPSR5_MLB_DAT ((uint32_t)1U << 19U)
#define GPSR5_MLB_SIG ((uint32_t)1U << 18U)
#define GPSR5_MLB_CLK ((uint32_t)1U << 17U)
#define GPSR5_SSI_SDATA9 ((uint32_t)1U << 16U)
#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 15U)
#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 14U)
#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 13U)
#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 12U)
#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 11U)
#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 10U)
#define GPSR5_RX2_A ((uint32_t)1U << 9U)
#define GPSR5_TX2_A ((uint32_t)1U << 8U)
#define GPSR5_SCK2_A ((uint32_t)1U << 7U)
#define GPSR5_TX1 ((uint32_t)1U << 6U)
#define GPSR5_RX1 ((uint32_t)1U << 5U)
#define GPSR5_RTS0_TANS_A ((uint32_t)1U << 4U)
#define GPSR5_CTS0_A ((uint32_t)1U << 3U)
#define GPSR5_TX0_A ((uint32_t)1U << 2U)
#define GPSR5_RX0_A ((uint32_t)1U << 1U)
#define GPSR5_SCK0_A ((uint32_t)1U << 0U)
#define GPSR6_USB30_PWEN ((uint32_t)1U << 17U)
#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U)
#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U)
#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U)
#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U)
#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U)
#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U)
#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U)
#define GPSR6_USB30_OVC ((uint32_t)1U << 9U)
#define GPSR6_AUDIO_CLKA ((uint32_t)1U << 8U)
#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U)
#define GPSR6_SSI_WS349 ((uint32_t)1U << 6U)
#define GPSR6_SSI_SCK349 ((uint32_t)1U << 5U)
#define GPSR6_SSI_SDATA2 ((uint32_t)1U << 4U)
#define GPSR6_SSI_SDATA1 ((uint32_t)1U << 3U)
#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U)
#define GPSR6_SSI_WS01239 ((uint32_t)1U << 1U)
#define GPSR6_SSI_SCK01239 ((uint32_t)1U << 0U)
#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
#define IOCTRL30_MASK (0x0007F000U)
#define POC_SD3_DS_33V ((uint32_t)1U << 29U)
#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U)
#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U)
#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U)
#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U)
#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U)
#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U)
#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U)
#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U)
#define POC_SD3_CMD_33V ((uint32_t)1U << 20U)
#define POC_SD3_CLK_33V ((uint32_t)1U << 19U)
#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U)
#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U)
#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U)
#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U)
#define POC_SD1_CMD_33V ((uint32_t)1U << 7U)
#define POC_SD1_CLK_33V ((uint32_t)1U << 6U)
#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U)
#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U)
#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U)
#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U)
#define POC_SD0_CMD_33V ((uint32_t)1U << 1U)
#define POC_SD0_CLK_33V ((uint32_t)1U << 0U)
#define IOCTRL32_MASK (0xFFFFFFFEU)
#define POC2_VREF_33V ((uint32_t)1U << 0U)
#define MOD_SEL0_ADGB_A ((uint32_t)0U << 29U)
#define MOD_SEL0_ADGB_B ((uint32_t)1U << 29U)
#define MOD_SEL0_ADGB_C ((uint32_t)2U << 29U)
#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 28U)
#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 28U)
#define MOD_SEL0_FM_A ((uint32_t)0U << 26U)
#define MOD_SEL0_FM_B ((uint32_t)1U << 26U)
#define MOD_SEL0_FM_C ((uint32_t)2U << 26U)
#define MOD_SEL0_FSO_A ((uint32_t)0U << 25U)
#define MOD_SEL0_FSO_B ((uint32_t)1U << 25U)
#define MOD_SEL0_HSCIF0_A ((uint32_t)0U << 24U)
#define MOD_SEL0_HSCIF0_B ((uint32_t)1U << 24U)
#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 23U)
#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 23U)
#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 22U)
#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 22U)
#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
#define MOD_SEL0_I2C1_C ((uint32_t)2U << 20U)
#define MOD_SEL0_I2C1_D ((uint32_t)3U << 20U)
#define MOD_SEL0_I2C2_A ((uint32_t)0U << 17U)
#define MOD_SEL0_I2C2_B ((uint32_t)1U << 17U)
#define MOD_SEL0_I2C2_C ((uint32_t)2U << 17U)
#define MOD_SEL0_I2C2_D ((uint32_t)3U << 17U)
#define MOD_SEL0_I2C2_E ((uint32_t)4U << 17U)
#define MOD_SEL0_NDFC_A ((uint32_t)0U << 16U)
#define MOD_SEL0_NDFC_B ((uint32_t)1U << 16U)
#define MOD_SEL0_PWM0_A ((uint32_t)0U << 15U)
#define MOD_SEL0_PWM0_B ((uint32_t)1U << 15U)
#define MOD_SEL0_PWM1_A ((uint32_t)0U << 14U)
#define MOD_SEL0_PWM1_B ((uint32_t)1U << 14U)
#define MOD_SEL0_PWM2_A ((uint32_t)0U << 12U)
#define MOD_SEL0_PWM2_B ((uint32_t)1U << 12U)
#define MOD_SEL0_PWM2_C ((uint32_t)2U << 12U)
#define MOD_SEL0_PWM3_A ((uint32_t)0U << 10U)
#define MOD_SEL0_PWM3_B ((uint32_t)1U << 10U)
#define MOD_SEL0_PWM3_C ((uint32_t)2U << 10U)
#define MOD_SEL0_PWM4_A ((uint32_t)0U << 9U)
#define MOD_SEL0_PWM4_B ((uint32_t)1U << 9U)
#define MOD_SEL0_PWM5_A ((uint32_t)0U << 8U)
#define MOD_SEL0_PWM5_B ((uint32_t)1U << 8U)
#define MOD_SEL0_PWM6_A ((uint32_t)0U << 7U)
#define MOD_SEL0_PWM6_B ((uint32_t)1U << 7U)
#define MOD_SEL0_REMOCON_A ((uint32_t)0U << 5U)
#define MOD_SEL0_REMOCON_B ((uint32_t)1U << 5U)
#define MOD_SEL0_REMOCON_C ((uint32_t)2U << 5U)
#define MOD_SEL0_SCIF_A ((uint32_t)0U << 4U)
#define MOD_SEL0_SCIF_B ((uint32_t)1U << 4U)
#define MOD_SEL0_SCIF0_A ((uint32_t)0U << 3U)
#define MOD_SEL0_SCIF0_B ((uint32_t)1U << 3U)
#define MOD_SEL0_SCIF2_A ((uint32_t)0U << 2U)
#define MOD_SEL0_SCIF2_B ((uint32_t)1U << 2U)
#define MOD_SEL0_SPEED_PULSE_IF_A ((uint32_t)0U << 0U)
#define MOD_SEL0_SPEED_PULSE_IF_B ((uint32_t)1U << 0U)
#define MOD_SEL0_SPEED_PULSE_IF_C ((uint32_t)2U << 0U)
#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 31U)
#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 31U)
#define MOD_SEL1_SSI2_A ((uint32_t)0U << 30U)
#define MOD_SEL1_SSI2_B ((uint32_t)1U << 30U)
#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 29U)
#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 29U)
#define MOD_SEL1_USB20_CH0_A ((uint32_t)0U << 28U)
#define MOD_SEL1_USB20_CH0_B ((uint32_t)1U << 28U)
#define MOD_SEL1_DRIF2_A ((uint32_t)0U << 26U)
#define MOD_SEL1_DRIF2_B ((uint32_t)1U << 26U)
#define MOD_SEL1_DRIF3_A ((uint32_t)0U << 25U)
#define MOD_SEL1_DRIF3_B ((uint32_t)1U << 25U)
#define MOD_SEL1_HSCIF3_A ((uint32_t)0U << 22U)
#define MOD_SEL1_HSCIF3_B ((uint32_t)1U << 22U)
#define MOD_SEL1_HSCIF3_C ((uint32_t)2U << 22U)
#define MOD_SEL1_HSCIF3_D ((uint32_t)3U << 22U)
#define MOD_SEL1_HSCIF3_E ((uint32_t)4U << 22U)
#define MOD_SEL1_HSCIF4_A ((uint32_t)0U << 19U)
#define MOD_SEL1_HSCIF4_B ((uint32_t)1U << 19U)
#define MOD_SEL1_HSCIF4_C ((uint32_t)2U << 19U)
#define MOD_SEL1_HSCIF4_D ((uint32_t)3U << 19U)
#define MOD_SEL1_HSCIF4_E ((uint32_t)4U << 19U)
#define MOD_SEL1_I2C6_A ((uint32_t)0U << 18U)
#define MOD_SEL1_I2C6_B ((uint32_t)1U << 18U)
#define MOD_SEL1_I2C7_A ((uint32_t)0U << 17U)
#define MOD_SEL1_I2C7_B ((uint32_t)1U << 17U)
#define MOD_SEL1_MSIOF2_A ((uint32_t)0U << 16U)
#define MOD_SEL1_MSIOF2_B ((uint32_t)1U << 16U)
#define MOD_SEL1_MSIOF3_A ((uint32_t)0U << 15U)
#define MOD_SEL1_MSIOF3_B ((uint32_t)1U << 15U)
#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
#define MOD_SEL1_SCIF3_C ((uint32_t)2U << 13U)
#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 11U)
#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 11U)
#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 11U)
#define MOD_SEL1_SCIF5_A ((uint32_t)0U << 9U)
#define MOD_SEL1_SCIF5_B ((uint32_t)1U << 9U)
#define MOD_SEL1_SCIF5_C ((uint32_t)2U << 9U)
#define MOD_SEL1_VIN4_A ((uint32_t)0U << 8U)
#define MOD_SEL1_VIN4_B ((uint32_t)1U << 8U)
#define MOD_SEL1_VIN5_A ((uint32_t)0U << 7U)
#define MOD_SEL1_VIN5_B ((uint32_t)1U << 7U)
#define MOD_SEL1_ADGC_A ((uint32_t)0U << 5U)
#define MOD_SEL1_ADGC_B ((uint32_t)1U << 5U)
#define MOD_SEL1_ADGC_C ((uint32_t)2U << 5U)
#define MOD_SEL1_SSI9_A ((uint32_t)0U << 4U)
#define MOD_SEL1_SSI9_B ((uint32_t)1U << 4U)
static
void
pfc_reg_write
(
uint32_t
addr
,
uint32_t
data
);
static
void
pfc_reg_write
(
uint32_t
addr
,
uint32_t
data
)
{
mmio_write_32
(
PFC_PMMR
,
~
data
);
mmio_write_32
((
uintptr_t
)
addr
,
data
);
}
void
pfc_init_e3
(
void
)
{
uint32_t
reg
;
/* initialize module select */
pfc_reg_write
(
PFC_MOD_SEL0
,
MOD_SEL0_ADGB_A
|
MOD_SEL0_DRIF0_A
|
MOD_SEL0_FM_A
|
MOD_SEL0_FSO_A
|
MOD_SEL0_HSCIF0_A
|
MOD_SEL0_HSCIF1_A
|
MOD_SEL0_HSCIF2_A
|
MOD_SEL0_I2C1_A
|
MOD_SEL0_I2C2_A
|
MOD_SEL0_NDFC_A
|
MOD_SEL0_PWM0_A
|
MOD_SEL0_PWM1_A
|
MOD_SEL0_PWM2_A
|
MOD_SEL0_PWM3_A
|
MOD_SEL0_PWM4_A
|
MOD_SEL0_PWM5_A
|
MOD_SEL0_PWM6_A
|
MOD_SEL0_REMOCON_A
|
MOD_SEL0_SCIF_A
|
MOD_SEL0_SCIF0_A
|
MOD_SEL0_SCIF2_A
|
MOD_SEL0_SPEED_PULSE_IF_A
);
pfc_reg_write
(
PFC_MOD_SEL1
,
MOD_SEL1_SIMCARD_A
|
MOD_SEL1_SSI2_A
|
MOD_SEL1_TIMER_TMU_A
|
MOD_SEL1_USB20_CH0_B
|
MOD_SEL1_DRIF2_A
|
MOD_SEL1_DRIF3_A
|
MOD_SEL1_HSCIF3_A
|
MOD_SEL1_HSCIF4_A
|
MOD_SEL1_I2C6_A
|
MOD_SEL1_I2C7_A
|
MOD_SEL1_MSIOF2_A
|
MOD_SEL1_MSIOF3_A
|
MOD_SEL1_SCIF3_A
|
MOD_SEL1_SCIF4_A
|
MOD_SEL1_SCIF5_A
|
MOD_SEL1_VIN4_A
|
MOD_SEL1_VIN5_A
|
MOD_SEL1_ADGC_A
|
MOD_SEL1_SSI9_A
);
/* initialize peripheral function select */
pfc_reg_write
(
PFC_IPSR0
,
IPSR_28_FUNC
(
0
)
/* QSPI1_MISO/IO1 */
|
IPSR_24_FUNC
(
0
)
/* QSPI1_MOSI/IO0 */
|
IPSR_20_FUNC
(
0
)
/* QSPI1_SPCLK */
|
IPSR_16_FUNC
(
0
)
/* QSPI0_IO3 */
|
IPSR_12_FUNC
(
0
)
/* QSPI0_IO2 */
|
IPSR_8_FUNC
(
0
)
/* QSPI0_MISO/IO1 */
|
IPSR_4_FUNC
(
0
)
/* QSPI0_MOSI/IO0 */
|
IPSR_0_FUNC
(
0
));
/* QSPI0_SPCLK */
pfc_reg_write
(
PFC_IPSR1
,
IPSR_28_FUNC
(
0
)
/* AVB_RD2 */
|
IPSR_24_FUNC
(
0
)
/* AVB_RD1 */
|
IPSR_20_FUNC
(
0
)
/* AVB_RD0 */
|
IPSR_16_FUNC
(
0
)
/* RPC_RESET# */
|
IPSR_12_FUNC
(
0
)
/* RPC_INT# */
|
IPSR_8_FUNC
(
0
)
/* QSPI1_SSL */
|
IPSR_4_FUNC
(
0
)
/* QSPI1_IO3 */
|
IPSR_0_FUNC
(
0
));
/* QSPI1_IO2 */
pfc_reg_write
(
PFC_IPSR2
,
IPSR_28_FUNC
(
1
)
/* IRQ0 */
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
2
)
/* AVB_LINK */
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
/* AVB_MDC */
|
IPSR_4_FUNC
(
0
)
/* AVB_MDIO */
|
IPSR_0_FUNC
(
0
));
/* AVB_TXCREFCLK */
pfc_reg_write
(
PFC_IPSR3
,
IPSR_28_FUNC
(
5
)
/* DU_HSYNC */
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
5
)
/* DU_DG4 */
|
IPSR_8_FUNC
(
5
)
/* DU_DOTCLKOUT0 */
|
IPSR_4_FUNC
(
5
)
/* DU_DISP */
|
IPSR_0_FUNC
(
1
));
/* IRQ1 */
pfc_reg_write
(
PFC_IPSR4
,
IPSR_28_FUNC
(
5
)
/* DU_DB5 */
|
IPSR_24_FUNC
(
5
)
/* DU_DB4 */
|
IPSR_20_FUNC
(
5
)
/* DU_DB3 */
|
IPSR_16_FUNC
(
5
)
/* DU_DB2 */
|
IPSR_12_FUNC
(
5
)
/* DU_DG6 */
|
IPSR_8_FUNC
(
5
)
/* DU_VSYNC */
|
IPSR_4_FUNC
(
5
)
/* DU_DG5 */
|
IPSR_0_FUNC
(
5
));
/* DU_DG7 */
pfc_reg_write
(
PFC_IPSR5
,
IPSR_28_FUNC
(
5
)
/* DU_DR3 */
|
IPSR_24_FUNC
(
5
)
/* DU_DB7 */
|
IPSR_20_FUNC
(
5
)
/* DU_DR2 */
|
IPSR_16_FUNC
(
5
)
/* DU_DR1 */
|
IPSR_12_FUNC
(
5
)
/* DU_DR0 */
|
IPSR_8_FUNC
(
5
)
/* DU_DB1 */
|
IPSR_4_FUNC
(
5
)
/* DU_DB0 */
|
IPSR_0_FUNC
(
5
));
/* DU_DB6 */
pfc_reg_write
(
PFC_IPSR6
,
IPSR_28_FUNC
(
5
)
/* DU_DG1 */
|
IPSR_24_FUNC
(
5
)
/* DU_DG0 */
|
IPSR_20_FUNC
(
5
)
/* DU_DR7 */
|
IPSR_16_FUNC
(
2
)
/* IRQ5 */
|
IPSR_12_FUNC
(
5
)
/* DU_DR6 */
|
IPSR_8_FUNC
(
5
)
/* DU_DR5 */
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
5
));
/* DU_DR4 */
pfc_reg_write
(
PFC_IPSR7
,
IPSR_28_FUNC
(
0
)
/* SD0_CLK */
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
5
)
/* DU_DOTCLKIN0 */
|
IPSR_16_FUNC
(
5
)
/* DU_DG3 */
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
5
));
/* DU_DG2 */
pfc_reg_write
(
PFC_IPSR8
,
IPSR_28_FUNC
(
0
)
/* SD1_DAT0 */
|
IPSR_24_FUNC
(
0
)
/* SD1_CMD */
|
IPSR_20_FUNC
(
0
)
/* SD1_CLK */
|
IPSR_16_FUNC
(
0
)
/* SD0_DAT3 */
|
IPSR_12_FUNC
(
0
)
/* SD0_DAT2 */
|
IPSR_8_FUNC
(
0
)
/* SD0_DAT1 */
|
IPSR_4_FUNC
(
0
)
/* SD0_DAT0 */
|
IPSR_0_FUNC
(
0
));
/* SD0_CMD */
pfc_reg_write
(
PFC_IPSR9
,
IPSR_28_FUNC
(
0
)
/* SD3_DAT2 */
|
IPSR_24_FUNC
(
0
)
/* SD3_DAT1 */
|
IPSR_20_FUNC
(
0
)
/* SD3_DAT0 */
|
IPSR_16_FUNC
(
0
)
/* SD3_CMD */
|
IPSR_12_FUNC
(
0
)
/* SD3_CLK */
|
IPSR_8_FUNC
(
0
)
/* SD1_DAT3 */
|
IPSR_4_FUNC
(
0
)
/* SD1_DAT2 */
|
IPSR_0_FUNC
(
0
));
/* SD1_DAT1 */
pfc_reg_write
(
PFC_IPSR10
,
IPSR_28_FUNC
(
0
)
/* SD0_WP */
|
IPSR_24_FUNC
(
0
)
/* SD0_CD */
|
IPSR_20_FUNC
(
0
)
/* SD3_DS */
|
IPSR_16_FUNC
(
0
)
/* SD3_DAT7 */
|
IPSR_12_FUNC
(
0
)
/* SD3_DAT6 */
|
IPSR_8_FUNC
(
0
)
/* SD3_DAT5 */
|
IPSR_4_FUNC
(
0
)
/* SD3_DAT4 */
|
IPSR_0_FUNC
(
0
));
/* SD3_DAT3 */
pfc_reg_write
(
PFC_IPSR11
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
2
)
/* AUDIO_CLKOUT1_A */
|
IPSR_16_FUNC
(
2
)
/* AUDIO_CLKOUT_A */
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
/* SD1_WP */
|
IPSR_0_FUNC
(
0
));
/* SD1_CD */
pfc_reg_write
(
PFC_IPSR12
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
/* RX2_A */
|
IPSR_8_FUNC
(
0
)
/* TX2_A */
|
IPSR_4_FUNC
(
2
)
/* AUDIO_CLKB_A */
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR13
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
2
)
/* AUDIO_CLKC_A */
|
IPSR_4_FUNC
(
1
)
/* HTX2_A */
|
IPSR_0_FUNC
(
1
));
/* HRX2_A */
pfc_reg_write
(
PFC_IPSR14
,
IPSR_28_FUNC
(
3
)
/* USB0_PWEN_B */
|
IPSR_24_FUNC
(
0
)
/* SSI_SDATA4 */
|
IPSR_20_FUNC
(
0
)
/* SSI_SDATA3 */
|
IPSR_16_FUNC
(
0
)
/* SSI_WS349 */
|
IPSR_12_FUNC
(
0
)
/* SSI_SCK349 */
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
/* SSI_SDATA1 */
|
IPSR_0_FUNC
(
0
));
/* SSI_SDATA0 */
pfc_reg_write
(
PFC_IPSR15
,
IPSR_28_FUNC
(
0
)
/* USB30_OVC */
|
IPSR_24_FUNC
(
0
)
/* USB30_PWEN */
|
IPSR_20_FUNC
(
0
)
/* AUDIO_CLKA */
|
IPSR_16_FUNC
(
1
)
/* HRTS2#_A */
|
IPSR_12_FUNC
(
1
)
/* HCTS2#_A */
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
3
));
/* USB0_OVC_B */
/* initialize GPIO/perihperal function select */
pfc_reg_write
(
PFC_GPSR0
,
GPSR0_SCL4
|
GPSR0_D15
|
GPSR0_D11
|
GPSR0_D10
|
GPSR0_D9
|
GPSR0_D8
|
GPSR0_D7
|
GPSR0_D6
|
GPSR0_D5
|
GPSR0_D3
|
GPSR0_D2
|
GPSR0_D1
|
GPSR0_D0
);
pfc_reg_write
(
PFC_GPSR1
,
GPSR1_WE0
|
GPSR1_CS0
|
GPSR1_A19
|
GPSR1_A18
|
GPSR1_A17
|
GPSR1_A16
|
GPSR1_A15
|
GPSR1_A14
|
GPSR1_A13
|
GPSR1_A12
|
GPSR1_A11
|
GPSR1_A10
|
GPSR1_A9
|
GPSR1_A8
|
GPSR1_A4
|
GPSR1_A3
|
GPSR1_A2
|
GPSR1_A1
|
GPSR1_A0
);
pfc_reg_write
(
PFC_GPSR2
,
GPSR2_BIT27_REVERCED
|
GPSR2_BIT26_REVERCED
|
GPSR2_RD
|
GPSR2_AVB_PHY_INT
|
GPSR2_AVB_TXCREFCLK
|
GPSR2_AVB_RD3
|
GPSR2_AVB_RD2
|
GPSR2_AVB_RD1
|
GPSR2_AVB_RD0
|
GPSR2_AVB_RXC
|
GPSR2_AVB_RX_CTL
|
GPSR2_RPC_RESET
|
GPSR2_RPC_RPC_INT
|
GPSR2_QSPI1_SSL
|
GPSR2_QSPI1_IO3
|
GPSR2_QSPI1_IO2
|
GPSR2_QSPI1_MISO_IO1
|
GPSR2_QSPI1_MOSI_IO0
|
GPSR2_QSPI1_SPCLK
|
GPSR2_QSPI0_SSL
|
GPSR2_QSPI0_IO3
|
GPSR2_QSPI0_IO2
|
GPSR2_QSPI0_MISO_IO1
|
GPSR2_QSPI0_MOSI_IO0
|
GPSR2_QSPI0_SPCLK
);
pfc_reg_write
(
PFC_GPSR3
,
GPSR3_SD1_WP
|
GPSR3_SD1_CD
|
GPSR3_SD0_WP
|
GPSR3_SD0_CD
|
GPSR3_SD1_DAT3
|
GPSR3_SD1_DAT2
|
GPSR3_SD1_DAT1
|
GPSR3_SD1_DAT0
|
GPSR3_SD1_CMD
|
GPSR3_SD1_CLK
|
GPSR3_SD0_DAT3
|
GPSR3_SD0_DAT2
|
GPSR3_SD0_DAT1
|
GPSR3_SD0_DAT0
|
GPSR3_SD0_CMD
|
GPSR3_SD0_CLK
);
pfc_reg_write
(
PFC_GPSR4
,
GPSR4_SD3_DS
|
GPSR4_SD3_DAT7
|
GPSR4_SD3_DAT6
|
GPSR4_SD3_DAT5
|
GPSR4_SD3_DAT4
|
GPSR4_SD3_DAT3
|
GPSR4_SD3_DAT2
|
GPSR4_SD3_DAT1
|
GPSR4_SD3_DAT0
|
GPSR4_SD3_CMD
|
GPSR4_SD3_CLK
);
pfc_reg_write
(
PFC_GPSR5
,
GPSR5_SSI_SDATA9
|
GPSR5_MSIOF0_SS2
|
GPSR5_MSIOF0_SS1
|
GPSR5_RX2_A
|
GPSR5_TX2_A
|
GPSR5_SCK2_A
|
GPSR5_RTS0_TANS_A
|
GPSR5_CTS0_A
);
pfc_reg_write
(
PFC_GPSR6
,
GPSR6_USB30_PWEN
|
GPSR6_SSI_SDATA6
|
GPSR6_SSI_WS6
|
GPSR6_SSI_WS5
|
GPSR6_SSI_SCK5
|
GPSR6_SSI_SDATA4
|
GPSR6_USB30_OVC
|
GPSR6_AUDIO_CLKA
|
GPSR6_SSI_SDATA3
|
GPSR6_SSI_WS349
|
GPSR6_SSI_SCK349
|
GPSR6_SSI_SDATA1
|
GPSR6_SSI_SDATA0
|
GPSR6_SSI_WS01239
|
GPSR6_SSI_SCK01239
);
/* initialize POC control */
reg
=
mmio_read_32
(
PFC_IOCTRL30
);
reg
=
((
reg
&
IOCTRL30_MASK
)
|
POC_SD1_DAT3_33V
|
POC_SD1_DAT2_33V
|
POC_SD1_DAT1_33V
|
POC_SD1_DAT0_33V
|
POC_SD1_CMD_33V
|
POC_SD1_CLK_33V
|
POC_SD0_DAT3_33V
|
POC_SD0_DAT2_33V
|
POC_SD0_DAT1_33V
|
POC_SD0_DAT0_33V
|
POC_SD0_CMD_33V
|
POC_SD0_CLK_33V
);
pfc_reg_write
(
PFC_IOCTRL30
,
reg
);
reg
=
mmio_read_32
(
PFC_IOCTRL32
);
reg
=
(
reg
&
IOCTRL32_MASK
);
pfc_reg_write
(
PFC_IOCTRL32
,
reg
);
/* initialize LSI pin pull-up/down control */
pfc_reg_write
(
PFC_PUD0
,
0xFDF80000U
);
pfc_reg_write
(
PFC_PUD1
,
0xCE298464U
);
pfc_reg_write
(
PFC_PUD2
,
0xA4C380F4U
);
pfc_reg_write
(
PFC_PUD3
,
0x0000079FU
);
pfc_reg_write
(
PFC_PUD4
,
0xFFF0FFFFU
);
pfc_reg_write
(
PFC_PUD5
,
0x40000000U
);
/* initialize LSI pin pull-enable register */
pfc_reg_write
(
PFC_PUEN0
,
0xFFF00000U
);
pfc_reg_write
(
PFC_PUEN1
,
0x00000000U
);
pfc_reg_write
(
PFC_PUEN2
,
0x00000004U
);
pfc_reg_write
(
PFC_PUEN3
,
0x00000000U
);
pfc_reg_write
(
PFC_PUEN4
,
0x07800010U
);
pfc_reg_write
(
PFC_PUEN5
,
0x00000000U
);
/* initialize positive/negative logic select */
mmio_write_32
(
GPIO_POSNEG0
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG1
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG2
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG3
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG4
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG5
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG6
,
0x00000000U
);
/* initialize general IO/interrupt switching */
mmio_write_32
(
GPIO_IOINTSEL0
,
0x00020000U
);
mmio_write_32
(
GPIO_IOINTSEL1
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL2
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL3
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL4
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL5
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL6
,
0x00000000U
);
/* initialize general output register */
mmio_write_32
(
GPIO_OUTDT0
,
0x00000010U
);
mmio_write_32
(
GPIO_OUTDT1
,
0x00100000U
);
mmio_write_32
(
GPIO_OUTDT2
,
0x00000000U
);
mmio_write_32
(
GPIO_OUTDT3
,
0x00008000U
);
mmio_write_32
(
GPIO_OUTDT5
,
0x00060000U
);
mmio_write_32
(
GPIO_OUTDT6
,
0x00000000U
);
/* initialize general input/output switching */
mmio_write_32
(
GPIO_INOUTSEL0
,
0x00000010U
);
mmio_write_32
(
GPIO_INOUTSEL1
,
0x00100020U
);
mmio_write_32
(
GPIO_INOUTSEL2
,
0x03000000U
);
mmio_write_32
(
GPIO_INOUTSEL3
,
0x00008000U
);
mmio_write_32
(
GPIO_INOUTSEL4
,
0x00000000U
);
mmio_write_32
(
GPIO_INOUTSEL5
,
0x00060000U
);
mmio_write_32
(
GPIO_INOUTSEL6
,
0x00004000U
);
}
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PFC_INIT_E3_H__
#define PFC_INIT_E3_H__
void
pfc_init_e3
(
void
);
#endif
/* PFC_INIT_E3_H__ */
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
/* for uint32_t */
#include <mmio.h>
/* GPIO base address */
#define GPIO_BASE (0xE6050000U)
/* GPIO registers */
#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U)
#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U)
#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U)
#define GPIO_INDT0 (GPIO_BASE + 0x000CU)
#define GPIO_INTDT0 (GPIO_BASE + 0x0010U)
#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U)
#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U)
#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU)
#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U)
#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U)
#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U)
#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U)
#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU)
#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U)
#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U)
#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U)
#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU)
#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U)
#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U)
#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
#define GPIO_INTDT1 (GPIO_BASE + 0x1010U)
#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U)
#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U)
#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU)
#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U)
#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U)
#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U)
#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U)
#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU)
#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U)
#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U)
#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U)
#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU)
#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U)
#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U)
#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U)
#define GPIO_INDT2 (GPIO_BASE + 0x200CU)
#define GPIO_INTDT2 (GPIO_BASE + 0x2010U)
#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U)
#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U)
#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU)
#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U)
#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U)
#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U)
#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U)
#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU)
#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U)
#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U)
#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U)
#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU)
#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U)
#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U)
#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
#define GPIO_INTDT3 (GPIO_BASE + 0x3010U)
#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U)
#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U)
#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU)
#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U)
#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U)
#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U)
#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U)
#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU)
#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U)
#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U)
#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U)
#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU)
#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U)
#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U)
#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U)
#define GPIO_INDT4 (GPIO_BASE + 0x400CU)
#define GPIO_INTDT4 (GPIO_BASE + 0x4010U)
#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U)
#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U)
#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU)
#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U)
#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U)
#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U)
#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U)
#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU)
#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U)
#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U)
#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U)
#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU)
#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U)
#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U)
#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U)
#define GPIO_INDT5 (GPIO_BASE + 0x500CU)
#define GPIO_INTDT5 (GPIO_BASE + 0x5010U)
#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U)
#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U)
#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU)
#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U)
#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U)
#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U)
#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U)
#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU)
#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U)
#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U)
#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U)
#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU)
#define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U)
#define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U)
#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
#define GPIO_INTDT6 (GPIO_BASE + 0x5410U)
#define GPIO_INTCLR6 (GPIO_BASE + 0x5414U)
#define GPIO_INTMSK6 (GPIO_BASE + 0x5418U)
#define GPIO_MSKCLR6 (GPIO_BASE + 0x541CU)
#define GPIO_POSNEG6 (GPIO_BASE + 0x5420U)
#define GPIO_EDGLEVEL6 (GPIO_BASE + 0x5424U)
#define GPIO_FILONOFF6 (GPIO_BASE + 0x5428U)
#define GPIO_INTMSKS6 (GPIO_BASE + 0x5438U)
#define GPIO_MSKCLRS6 (GPIO_BASE + 0x543CU)
#define GPIO_OUTDTSEL6 (GPIO_BASE + 0x5440U)
#define GPIO_OUTDTH6 (GPIO_BASE + 0x5444U)
#define GPIO_OUTDTL6 (GPIO_BASE + 0x5448U)
#define GPIO_BOTHEDGE6 (GPIO_BASE + 0x544CU)
#define GPIO_IOINTSEL7 (GPIO_BASE + 0x5800U)
#define GPIO_INOUTSEL7 (GPIO_BASE + 0x5804U)
#define GPIO_OUTDT7 (GPIO_BASE + 0x5808U)
#define GPIO_INDT7 (GPIO_BASE + 0x580CU)
#define GPIO_INTDT7 (GPIO_BASE + 0x5810U)
#define GPIO_INTCLR7 (GPIO_BASE + 0x5814U)
#define GPIO_INTMSK7 (GPIO_BASE + 0x5818U)
#define GPIO_MSKCLR7 (GPIO_BASE + 0x581CU)
#define GPIO_POSNEG7 (GPIO_BASE + 0x5820U)
#define GPIO_EDGLEVEL7 (GPIO_BASE + 0x5824U)
#define GPIO_FILONOFF7 (GPIO_BASE + 0x5828U)
#define GPIO_INTMSKS7 (GPIO_BASE + 0x5838U)
#define GPIO_MSKCLRS7 (GPIO_BASE + 0x583CU)
#define GPIO_OUTDTSEL7 (GPIO_BASE + 0x5840U)
#define GPIO_OUTDTH7 (GPIO_BASE + 0x5844U)
#define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U)
#define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU)
/* Pin functon base address */
#define PFC_BASE (0xE6060000U)
/* Pin functon registers */
#define PFC_PMMR (PFC_BASE + 0x0000U)
#define PFC_GPSR0 (PFC_BASE + 0x0100U)
#define PFC_GPSR1 (PFC_BASE + 0x0104U)
#define PFC_GPSR2 (PFC_BASE + 0x0108U)
#define PFC_GPSR3 (PFC_BASE + 0x010CU)
#define PFC_GPSR4 (PFC_BASE + 0x0110U)
#define PFC_GPSR5 (PFC_BASE + 0x0114U)
#define PFC_GPSR6 (PFC_BASE + 0x0118U)
#define PFC_GPSR7 (PFC_BASE + 0x011CU)
#define PFC_IPSR0 (PFC_BASE + 0x0200U)
#define PFC_IPSR1 (PFC_BASE + 0x0204U)
#define PFC_IPSR2 (PFC_BASE + 0x0208U)
#define PFC_IPSR3 (PFC_BASE + 0x020CU)
#define PFC_IPSR4 (PFC_BASE + 0x0210U)
#define PFC_IPSR5 (PFC_BASE + 0x0214U)
#define PFC_IPSR6 (PFC_BASE + 0x0218U)
#define PFC_IPSR7 (PFC_BASE + 0x021CU)
#define PFC_IPSR8 (PFC_BASE + 0x0220U)
#define PFC_IPSR9 (PFC_BASE + 0x0224U)
#define PFC_IPSR10 (PFC_BASE + 0x0228U)
#define PFC_IPSR11 (PFC_BASE + 0x022CU)
#define PFC_IPSR12 (PFC_BASE + 0x0230U)
#define PFC_IPSR13 (PFC_BASE + 0x0234U)
#define PFC_IPSR14 (PFC_BASE + 0x0238U)
#define PFC_IPSR15 (PFC_BASE + 0x023CU)
#define PFC_IPSR16 (PFC_BASE + 0x0240U)
#define PFC_IPSR17 (PFC_BASE + 0x0244U)
#define PFC_DRVCTRL0 (PFC_BASE + 0x0300U)
#define PFC_DRVCTRL1 (PFC_BASE + 0x0304U)
#define PFC_DRVCTRL2 (PFC_BASE + 0x0308U)
#define PFC_DRVCTRL3 (PFC_BASE + 0x030CU)
#define PFC_DRVCTRL4 (PFC_BASE + 0x0310U)
#define PFC_DRVCTRL5 (PFC_BASE + 0x0314U)
#define PFC_DRVCTRL6 (PFC_BASE + 0x0318U)
#define PFC_DRVCTRL7 (PFC_BASE + 0x031CU)
#define PFC_DRVCTRL8 (PFC_BASE + 0x0320U)
#define PFC_DRVCTRL9 (PFC_BASE + 0x0324U)
#define PFC_DRVCTRL10 (PFC_BASE + 0x0328U)
#define PFC_DRVCTRL11 (PFC_BASE + 0x032CU)
#define PFC_DRVCTRL12 (PFC_BASE + 0x0330U)
#define PFC_DRVCTRL13 (PFC_BASE + 0x0334U)
#define PFC_DRVCTRL14 (PFC_BASE + 0x0338U)
#define PFC_DRVCTRL15 (PFC_BASE + 0x033CU)
#define PFC_DRVCTRL16 (PFC_BASE + 0x0340U)
#define PFC_DRVCTRL17 (PFC_BASE + 0x0344U)
#define PFC_DRVCTRL18 (PFC_BASE + 0x0348U)
#define PFC_DRVCTRL19 (PFC_BASE + 0x034CU)
#define PFC_DRVCTRL20 (PFC_BASE + 0x0350U)
#define PFC_DRVCTRL21 (PFC_BASE + 0x0354U)
#define PFC_DRVCTRL22 (PFC_BASE + 0x0358U)
#define PFC_DRVCTRL23 (PFC_BASE + 0x035CU)
#define PFC_DRVCTRL24 (PFC_BASE + 0x0360U)
#define PFC_POCCTRL0 (PFC_BASE + 0x0380U)
#define PFC_TDSELCTRL0 (PFC_BASE + 0x03C0U)
#define PFC_IOCTRL (PFC_BASE + 0x03E0U)
#define PFC_TSREG (PFC_BASE + 0x03E4U)
#define PFC_PUEN0 (PFC_BASE + 0x0400U)
#define PFC_PUEN1 (PFC_BASE + 0x0404U)
#define PFC_PUEN2 (PFC_BASE + 0x0408U)
#define PFC_PUEN3 (PFC_BASE + 0x040CU)
#define PFC_PUEN4 (PFC_BASE + 0x0410U)
#define PFC_PUEN5 (PFC_BASE + 0x0414U)
#define PFC_PUEN6 (PFC_BASE + 0x0418U)
#define PFC_PUD0 (PFC_BASE + 0x0440U)
#define PFC_PUD1 (PFC_BASE + 0x0444U)
#define PFC_PUD2 (PFC_BASE + 0x0448U)
#define PFC_PUD3 (PFC_BASE + 0x044CU)
#define PFC_PUD4 (PFC_BASE + 0x0450U)
#define PFC_PUD5 (PFC_BASE + 0x0454U)
#define PFC_PUD6 (PFC_BASE + 0x0458U)
#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U)
#define PFC_MOD_SEL1 (PFC_BASE + 0x0504U)
#define PFC_MOD_SEL2 (PFC_BASE + 0x0508U)
#define GPSR0_D15 ((uint32_t)1U << 15U)
#define GPSR0_D14 ((uint32_t)1U << 14U)
#define GPSR0_D13 ((uint32_t)1U << 13U)
#define GPSR0_D12 ((uint32_t)1U << 12U)
#define GPSR0_D11 ((uint32_t)1U << 11U)
#define GPSR0_D10 ((uint32_t)1U << 10U)
#define GPSR0_D9 ((uint32_t)1U << 9U)
#define GPSR0_D8 ((uint32_t)1U << 8U)
#define GPSR0_D7 ((uint32_t)1U << 7U)
#define GPSR0_D6 ((uint32_t)1U << 6U)
#define GPSR0_D5 ((uint32_t)1U << 5U)
#define GPSR0_D4 ((uint32_t)1U << 4U)
#define GPSR0_D3 ((uint32_t)1U << 3U)
#define GPSR0_D2 ((uint32_t)1U << 2U)
#define GPSR0_D1 ((uint32_t)1U << 1U)
#define GPSR0_D0 ((uint32_t)1U << 0U)
#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U)
#define GPSR1_WE1 ((uint32_t)1U << 26U)
#define GPSR1_WE0 ((uint32_t)1U << 25U)
#define GPSR1_RD_WR ((uint32_t)1U << 24U)
#define GPSR1_RD ((uint32_t)1U << 23U)
#define GPSR1_BS ((uint32_t)1U << 22U)
#define GPSR1_CS1_A26 ((uint32_t)1U << 21U)
#define GPSR1_CS0 ((uint32_t)1U << 20U)
#define GPSR1_A19 ((uint32_t)1U << 19U)
#define GPSR1_A18 ((uint32_t)1U << 18U)
#define GPSR1_A17 ((uint32_t)1U << 17U)
#define GPSR1_A16 ((uint32_t)1U << 16U)
#define GPSR1_A15 ((uint32_t)1U << 15U)
#define GPSR1_A14 ((uint32_t)1U << 14U)
#define GPSR1_A13 ((uint32_t)1U << 13U)
#define GPSR1_A12 ((uint32_t)1U << 12U)
#define GPSR1_A11 ((uint32_t)1U << 11U)
#define GPSR1_A10 ((uint32_t)1U << 10U)
#define GPSR1_A9 ((uint32_t)1U << 9U)
#define GPSR1_A8 ((uint32_t)1U << 8U)
#define GPSR1_A7 ((uint32_t)1U << 7U)
#define GPSR1_A6 ((uint32_t)1U << 6U)
#define GPSR1_A5 ((uint32_t)1U << 5U)
#define GPSR1_A4 ((uint32_t)1U << 4U)
#define GPSR1_A3 ((uint32_t)1U << 3U)
#define GPSR1_A2 ((uint32_t)1U << 2U)
#define GPSR1_A1 ((uint32_t)1U << 1U)
#define GPSR1_A0 ((uint32_t)1U << 0U)
#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U)
#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U)
#define GPSR2_AVB_LINK ((uint32_t)1U << 12U)
#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U)
#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U)
#define GPSR2_AVB_MDC ((uint32_t)1U << 9U)
#define GPSR2_PWM2_A ((uint32_t)1U << 8U)
#define GPSR2_PWM1_A ((uint32_t)1U << 7U)
#define GPSR2_PWM0 ((uint32_t)1U << 6U)
#define GPSR2_IRQ5 ((uint32_t)1U << 5U)
#define GPSR2_IRQ4 ((uint32_t)1U << 4U)
#define GPSR2_IRQ3 ((uint32_t)1U << 3U)
#define GPSR2_IRQ2 ((uint32_t)1U << 2U)
#define GPSR2_IRQ1 ((uint32_t)1U << 1U)
#define GPSR2_IRQ0 ((uint32_t)1U << 0U)
#define GPSR3_SD1_WP ((uint32_t)1U << 15U)
#define GPSR3_SD1_CD ((uint32_t)1U << 14U)
#define GPSR3_SD0_WP ((uint32_t)1U << 13U)
#define GPSR3_SD0_CD ((uint32_t)1U << 12U)
#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U)
#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U)
#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U)
#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U)
#define GPSR3_SD1_CMD ((uint32_t)1U << 7U)
#define GPSR3_SD1_CLK ((uint32_t)1U << 6U)
#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U)
#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U)
#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U)
#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U)
#define GPSR3_SD0_CMD ((uint32_t)1U << 1U)
#define GPSR3_SD0_CLK ((uint32_t)1U << 0U)
#define GPSR4_SD3_DS ((uint32_t)1U << 17U)
#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U)
#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U)
#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U)
#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U)
#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U)
#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U)
#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U)
#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U)
#define GPSR4_SD3_CMD ((uint32_t)1U << 8U)
#define GPSR4_SD3_CLK ((uint32_t)1U << 7U)
#define GPSR4_SD2_DS ((uint32_t)1U << 6U)
#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U)
#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U)
#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U)
#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U)
#define GPSR4_SD2_CMD ((uint32_t)1U << 1U)
#define GPSR4_SD2_CLK ((uint32_t)1U << 0U)
#define GPSR5_MLB_DAT ((uint32_t)1U << 25U)
#define GPSR5_MLB_SIG ((uint32_t)1U << 24U)
#define GPSR5_MLB_CLK ((uint32_t)1U << 23U)
#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U)
#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U)
#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U)
#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U)
#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U)
#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U)
#define GPSR5_HRTS0 ((uint32_t)1U << 16U)
#define GPSR5_HCTS0 ((uint32_t)1U << 15U)
#define GPSR5_HTX0 ((uint32_t)1U << 14U)
#define GPSR5_HRX0 ((uint32_t)1U << 13U)
#define GPSR5_HSCK0 ((uint32_t)1U << 12U)
#define GPSR5_RX2_A ((uint32_t)1U << 11U)
#define GPSR5_TX2_A ((uint32_t)1U << 10U)
#define GPSR5_SCK2 ((uint32_t)1U << 9U)
#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U)
#define GPSR5_CTS1 ((uint32_t)1U << 7U)
#define GPSR5_TX1_A ((uint32_t)1U << 6U)
#define GPSR5_RX1_A ((uint32_t)1U << 5U)
#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U)
#define GPSR5_CTS0 ((uint32_t)1U << 3U)
#define GPSR5_TX0 ((uint32_t)1U << 2U)
#define GPSR5_RX0 ((uint32_t)1U << 1U)
#define GPSR5_SCK0 ((uint32_t)1U << 0U)
#define GPSR6_USB31_OVC ((uint32_t)1U << 31U)
#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U)
#define GPSR6_USB30_OVC ((uint32_t)1U << 29U)
#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U)
#define GPSR6_USB1_OVC ((uint32_t)1U << 27U)
#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U)
#define GPSR6_USB0_OVC ((uint32_t)1U << 25U)
#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U)
#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U)
#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U)
#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U)
#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U)
#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U)
#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U)
#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U)
#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U)
#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U)
#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U)
#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U)
#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U)
#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U)
#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U)
#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U)
#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U)
#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U)
#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U)
#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U)
#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U)
#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U)
#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U)
#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U)
#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U)
#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U)
#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U)
#define GPSR7_AVS2 ((uint32_t)1U << 1U)
#define GPSR7_AVS1 ((uint32_t)1U << 0U)
#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
#define POC_SD3_DS_33V ((uint32_t)1U << 29U)
#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U)
#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U)
#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U)
#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U)
#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U)
#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U)
#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U)
#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U)
#define POC_SD3_CMD_33V ((uint32_t)1U << 20U)
#define POC_SD3_CLK_33V ((uint32_t)1U << 19U)
#define POC_SD2_DS_33V ((uint32_t)1U << 18U)
#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U)
#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U)
#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U)
#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U)
#define POC_SD2_CMD_33V ((uint32_t)1U << 13U)
#define POC_SD2_CLK_33V ((uint32_t)1U << 12U)
#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U)
#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U)
#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U)
#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U)
#define POC_SD1_CMD_33V ((uint32_t)1U << 7U)
#define POC_SD1_CLK_33V ((uint32_t)1U << 6U)
#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U)
#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U)
#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U)
#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U)
#define POC_SD0_CMD_33V ((uint32_t)1U << 1U)
#define POC_SD0_CLK_33V ((uint32_t)1U << 0U)
#define DRVCTRL0_MASK (0xCCCCCCCCU)
#define DRVCTRL1_MASK (0xCCCCCCC8U)
#define DRVCTRL2_MASK (0x88888888U)
#define DRVCTRL3_MASK (0x88888888U)
#define DRVCTRL4_MASK (0x88888888U)
#define DRVCTRL5_MASK (0x88888888U)
#define DRVCTRL6_MASK (0x88888888U)
#define DRVCTRL7_MASK (0x88888888U)
#define DRVCTRL8_MASK (0x88888888U)
#define DRVCTRL9_MASK (0x88888888U)
#define DRVCTRL10_MASK (0x88888888U)
#define DRVCTRL11_MASK (0x888888CCU)
#define DRVCTRL12_MASK (0xCCCFFFCFU)
#define DRVCTRL13_MASK (0xCC888888U)
#define DRVCTRL14_MASK (0x88888888U)
#define DRVCTRL15_MASK (0x88888888U)
#define DRVCTRL16_MASK (0x88888888U)
#define DRVCTRL17_MASK (0x88888888U)
#define DRVCTRL18_MASK (0x88888888U)
#define DRVCTRL19_MASK (0x88888888U)
#define DRVCTRL20_MASK (0x88888888U)
#define DRVCTRL21_MASK (0x88888888U)
#define DRVCTRL22_MASK (0x88888888U)
#define DRVCTRL23_MASK (0x88888888U)
#define DRVCTRL24_MASK (0x8888888FU)
#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
#define MOD_SEL0_I2C6_A ((uint32_t)0U << 20U)
#define MOD_SEL0_I2C6_B ((uint32_t)1U << 20U)
#define MOD_SEL0_I2C6_C ((uint32_t)2U << 20U)
#define MOD_SEL0_I2C2_A ((uint32_t)0U << 19U)
#define MOD_SEL0_I2C2_B ((uint32_t)1U << 19U)
#define MOD_SEL0_I2C1_A ((uint32_t)0U << 18U)
#define MOD_SEL0_I2C1_B ((uint32_t)1U << 18U)
#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 17U)
#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 17U)
#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 15U)
#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 15U)
#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 15U)
#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 15U)
#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 14U)
#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 14U)
#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 13U)
#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 13U)
#define MOD_SEL0_FSO_A ((uint32_t)0U << 12U)
#define MOD_SEL0_FSO_B ((uint32_t)1U << 12U)
#define MOD_SEL0_FM_A ((uint32_t)0U << 11U)
#define MOD_SEL0_FM_B ((uint32_t)1U << 11U)
#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 10U)
#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 10U)
#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 9U)
#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 9U)
#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 8U)
#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 8U)
#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 6U)
#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 6U)
#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 6U)
#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 4U)
#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 4U)
#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 4U)
#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 3U)
#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 3U)
#define MOD_SEL0_ADG_A ((uint32_t)0U << 1U)
#define MOD_SEL0_ADG_B ((uint32_t)1U << 1U)
#define MOD_SEL0_ADG_C ((uint32_t)2U << 1U)
#define MOD_SEL0_ADG_D ((uint32_t)3U << 1U)
#define MOD_SEL0_5LINE_A ((uint32_t)0U << 0U)
#define MOD_SEL0_5LINE_B ((uint32_t)1U << 0U)
#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
static
void
pfc_reg_write
(
uint32_t
addr
,
uint32_t
data
);
static
void
pfc_reg_write
(
uint32_t
addr
,
uint32_t
data
)
{
mmio_write_32
(
PFC_PMMR
,
~
data
);
mmio_write_32
((
uintptr_t
)
addr
,
data
);
}
void
pfc_init_h3_v1
(
void
)
{
uint32_t
reg
;
/* initialize module select */
pfc_reg_write
(
PFC_MOD_SEL0
,
MOD_SEL0_MSIOF3_A
|
MOD_SEL0_MSIOF2_A
|
MOD_SEL0_MSIOF1_A
|
MOD_SEL0_LBSC_A
|
MOD_SEL0_IEBUS_A
|
MOD_SEL0_I2C6_A
|
MOD_SEL0_I2C2_A
|
MOD_SEL0_I2C1_A
|
MOD_SEL0_HSCIF4_A
|
MOD_SEL0_HSCIF3_A
|
MOD_SEL0_HSCIF2_A
|
MOD_SEL0_HSCIF1_A
|
MOD_SEL0_FM_A
|
MOD_SEL0_ETHERAVB_A
|
MOD_SEL0_DRIF3_A
|
MOD_SEL0_DRIF2_A
|
MOD_SEL0_DRIF1_A
|
MOD_SEL0_DRIF0_A
|
MOD_SEL0_CANFD0_A
|
MOD_SEL0_ADG_A
|
MOD_SEL0_5LINE_A
);
pfc_reg_write
(
PFC_MOD_SEL1
,
MOD_SEL1_TSIF1_A
|
MOD_SEL1_TSIF0_A
|
MOD_SEL1_TIMER_TMU_A
|
MOD_SEL1_SSP1_1_A
|
MOD_SEL1_SSP1_0_A
|
MOD_SEL1_SSI_A
|
MOD_SEL1_SPEED_PULSE_IF_A
|
MOD_SEL1_SIMCARD_A
|
MOD_SEL1_SDHI2_A
|
MOD_SEL1_SCIF4_A
|
MOD_SEL1_SCIF3_A
|
MOD_SEL1_SCIF2_A
|
MOD_SEL1_SCIF1_A
|
MOD_SEL1_SCIF_A
|
MOD_SEL1_REMOCON_A
|
MOD_SEL1_RCAN0_A
|
MOD_SEL1_PWM6_A
|
MOD_SEL1_PWM5_A
|
MOD_SEL1_PWM4_A
|
MOD_SEL1_PWM3_A
|
MOD_SEL1_PWM2_A
|
MOD_SEL1_PWM1_A
);
pfc_reg_write
(
PFC_MOD_SEL2
,
MOD_SEL2_I2C_5_A
|
MOD_SEL2_I2C_3_A
|
MOD_SEL2_I2C_0_A
|
MOD_SEL2_VIN4_A
);
/* initialize peripheral function select */
pfc_reg_write
(
PFC_IPSR0
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR1
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
3
)
|
IPSR_8_FUNC
(
3
)
|
IPSR_4_FUNC
(
3
)
|
IPSR_0_FUNC
(
3
));
pfc_reg_write
(
PFC_IPSR2
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR3
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR4
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR5
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR6
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR7
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR8
,
IPSR_28_FUNC
(
1
)
|
IPSR_24_FUNC
(
1
)
|
IPSR_20_FUNC
(
1
)
|
IPSR_16_FUNC
(
1
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR9
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR10
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
4
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
1
)
|
IPSR_0_FUNC
(
1
));
pfc_reg_write
(
PFC_IPSR11
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
4
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR12
,
IPSR_28_FUNC
(
8
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
3
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR13
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
3
)
|
IPSR_0_FUNC
(
8
));
pfc_reg_write
(
PFC_IPSR14
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR15
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
1
)
|
IPSR_0_FUNC
(
1
));
pfc_reg_write
(
PFC_IPSR16
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
1
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR17
,
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
/* initialize GPIO/perihperal function select */
pfc_reg_write
(
PFC_GPSR0
,
GPSR0_D15
|
GPSR0_D14
|
GPSR0_D13
|
GPSR0_D12
|
GPSR0_D11
|
GPSR0_D10
|
GPSR0_D9
|
GPSR0_D8
);
pfc_reg_write
(
PFC_GPSR1
,
GPSR1_EX_WAIT0_A
|
GPSR1_A19
|
GPSR1_A18
|
GPSR1_A17
|
GPSR1_A16
|
GPSR1_A15
|
GPSR1_A14
|
GPSR1_A13
|
GPSR1_A12
|
GPSR1_A7
|
GPSR1_A6
|
GPSR1_A5
|
GPSR1_A4
|
GPSR1_A3
|
GPSR1_A2
|
GPSR1_A1
|
GPSR1_A0
);
pfc_reg_write
(
PFC_GPSR2
,
GPSR2_AVB_AVTP_CAPTURE_A
|
GPSR2_AVB_AVTP_MATCH_A
|
GPSR2_AVB_LINK
|
GPSR2_AVB_PHY_INT
|
GPSR2_AVB_MDC
|
GPSR2_PWM2_A
|
GPSR2_PWM1_A
|
GPSR2_IRQ5
|
GPSR2_IRQ4
|
GPSR2_IRQ3
|
GPSR2_IRQ2
|
GPSR2_IRQ1
|
GPSR2_IRQ0
);
pfc_reg_write
(
PFC_GPSR3
,
GPSR3_SD0_WP
|
GPSR3_SD0_CD
|
GPSR3_SD1_DAT3
|
GPSR3_SD1_DAT2
|
GPSR3_SD1_DAT1
|
GPSR3_SD1_DAT0
|
GPSR3_SD0_DAT3
|
GPSR3_SD0_DAT2
|
GPSR3_SD0_DAT1
|
GPSR3_SD0_DAT0
|
GPSR3_SD0_CMD
|
GPSR3_SD0_CLK
);
pfc_reg_write
(
PFC_GPSR4
,
GPSR4_SD3_DAT7
|
GPSR4_SD3_DAT6
|
GPSR4_SD3_DAT3
|
GPSR4_SD3_DAT2
|
GPSR4_SD3_DAT1
|
GPSR4_SD3_DAT0
|
GPSR4_SD3_CMD
|
GPSR4_SD3_CLK
|
GPSR4_SD2_DS
|
GPSR4_SD2_DAT3
|
GPSR4_SD2_DAT2
|
GPSR4_SD2_DAT1
|
GPSR4_SD2_DAT0
|
GPSR4_SD2_CMD
|
GPSR4_SD2_CLK
);
pfc_reg_write
(
PFC_GPSR5
,
GPSR5_MSIOF0_SS2
|
GPSR5_MSIOF0_SS1
|
GPSR5_MSIOF0_SYNC
|
GPSR5_HRTS0
|
GPSR5_HCTS0
|
GPSR5_HTX0
|
GPSR5_HRX0
|
GPSR5_HSCK0
|
GPSR5_RX2_A
|
GPSR5_TX2_A
|
GPSR5_SCK2
|
GPSR5_RTS1_TANS
|
GPSR5_CTS1
|
GPSR5_TX1_A
|
GPSR5_RX1_A
|
GPSR5_RTS0_TANS
|
GPSR5_SCK0
);
pfc_reg_write
(
PFC_GPSR6
,
GPSR6_USB30_OVC
|
GPSR6_USB30_PWEN
|
GPSR6_USB1_OVC
|
GPSR6_USB1_PWEN
|
GPSR6_USB0_OVC
|
GPSR6_USB0_PWEN
|
GPSR6_AUDIO_CLKB_B
|
GPSR6_AUDIO_CLKA_A
|
GPSR6_SSI_SDATA8
|
GPSR6_SSI_SDATA7
|
GPSR6_SSI_WS78
|
GPSR6_SSI_SCK78
|
GPSR6_SSI_WS6
|
GPSR6_SSI_SCK6
|
GPSR6_SSI_SDATA4
|
GPSR6_SSI_WS4
|
GPSR6_SSI_SCK4
|
GPSR6_SSI_SDATA1_A
|
GPSR6_SSI_SDATA0
|
GPSR6_SSI_WS0129
|
GPSR6_SSI_SCK0129
);
pfc_reg_write
(
PFC_GPSR7
,
GPSR7_HDMI1_CEC
|
GPSR7_HDMI0_CEC
|
GPSR7_AVS2
|
GPSR7_AVS1
);
/* initialize POC control register */
pfc_reg_write
(
PFC_POCCTRL0
,
POC_SD3_DS_33V
|
POC_SD3_DAT7_33V
|
POC_SD3_DAT6_33V
|
POC_SD3_DAT5_33V
|
POC_SD3_DAT4_33V
|
POC_SD3_DAT3_33V
|
POC_SD3_DAT2_33V
|
POC_SD3_DAT1_33V
|
POC_SD3_DAT0_33V
|
POC_SD3_CMD_33V
|
POC_SD3_CLK_33V
|
POC_SD0_DAT3_33V
|
POC_SD0_DAT2_33V
|
POC_SD0_DAT1_33V
|
POC_SD0_DAT0_33V
|
POC_SD0_CMD_33V
|
POC_SD0_CLK_33V
);
/* initialize DRV control register */
reg
=
mmio_read_32
(
PFC_DRVCTRL0
);
reg
=
((
reg
&
DRVCTRL0_MASK
)
|
DRVCTRL0_QSPI0_SPCLK
(
3
)
|
DRVCTRL0_QSPI0_MOSI_IO0
(
3
)
|
DRVCTRL0_QSPI0_MISO_IO1
(
3
)
|
DRVCTRL0_QSPI0_IO2
(
3
)
|
DRVCTRL0_QSPI0_IO3
(
3
)
|
DRVCTRL0_QSPI0_SSL
(
3
)
|
DRVCTRL0_QSPI1_SPCLK
(
3
)
|
DRVCTRL0_QSPI1_MOSI_IO0
(
3
));
pfc_reg_write
(
PFC_DRVCTRL0
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL1
);
reg
=
((
reg
&
DRVCTRL1_MASK
)
|
DRVCTRL1_QSPI1_MISO_IO1
(
3
)
|
DRVCTRL1_QSPI1_IO2
(
3
)
|
DRVCTRL1_QSPI1_IO3
(
3
)
|
DRVCTRL1_QSPI1_SS
(
3
)
|
DRVCTRL1_RPC_INT
(
3
)
|
DRVCTRL1_RPC_WP
(
3
)
|
DRVCTRL1_RPC_RESET
(
3
)
|
DRVCTRL1_AVB_RX_CTL
(
7
));
pfc_reg_write
(
PFC_DRVCTRL1
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL2
);
reg
=
((
reg
&
DRVCTRL2_MASK
)
|
DRVCTRL2_AVB_RXC
(
7
)
|
DRVCTRL2_AVB_RD0
(
7
)
|
DRVCTRL2_AVB_RD1
(
7
)
|
DRVCTRL2_AVB_RD2
(
7
)
|
DRVCTRL2_AVB_RD3
(
7
)
|
DRVCTRL2_AVB_TX_CTL
(
3
)
|
DRVCTRL2_AVB_TXC
(
3
)
|
DRVCTRL2_AVB_TD0
(
3
));
pfc_reg_write
(
PFC_DRVCTRL2
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL3
);
reg
=
((
reg
&
DRVCTRL3_MASK
)
|
DRVCTRL3_AVB_TD1
(
3
)
|
DRVCTRL3_AVB_TD2
(
3
)
|
DRVCTRL3_AVB_TD3
(
3
)
|
DRVCTRL3_AVB_TXCREFCLK
(
7
)
|
DRVCTRL3_AVB_MDIO
(
7
)
|
DRVCTRL3_AVB_MDC
(
7
)
|
DRVCTRL3_AVB_MAGIC
(
7
)
|
DRVCTRL3_AVB_PHY_INT
(
7
));
pfc_reg_write
(
PFC_DRVCTRL3
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL4
);
reg
=
((
reg
&
DRVCTRL4_MASK
)
|
DRVCTRL4_AVB_LINK
(
7
)
|
DRVCTRL4_AVB_AVTP_MATCH
(
7
)
|
DRVCTRL4_AVB_AVTP_CAPTURE
(
7
)
|
DRVCTRL4_IRQ0
(
7
)
|
DRVCTRL4_IRQ1
(
7
)
|
DRVCTRL4_IRQ2
(
7
)
|
DRVCTRL4_IRQ3
(
7
)
|
DRVCTRL4_IRQ4
(
7
));
pfc_reg_write
(
PFC_DRVCTRL4
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL5
);
reg
=
((
reg
&
DRVCTRL5_MASK
)
|
DRVCTRL5_IRQ5
(
7
)
|
DRVCTRL5_PWM0
(
7
)
|
DRVCTRL5_PWM1
(
7
)
|
DRVCTRL5_PWM2
(
7
)
|
DRVCTRL5_A0
(
3
)
|
DRVCTRL5_A1
(
3
)
|
DRVCTRL5_A2
(
3
)
|
DRVCTRL5_A3
(
3
));
pfc_reg_write
(
PFC_DRVCTRL5
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL6
);
reg
=
((
reg
&
DRVCTRL6_MASK
)
|
DRVCTRL6_A4
(
3
)
|
DRVCTRL6_A5
(
3
)
|
DRVCTRL6_A6
(
3
)
|
DRVCTRL6_A7
(
3
)
|
DRVCTRL6_A8
(
7
)
|
DRVCTRL6_A9
(
7
)
|
DRVCTRL6_A10
(
7
)
|
DRVCTRL6_A11
(
7
));
pfc_reg_write
(
PFC_DRVCTRL6
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL7
);
reg
=
((
reg
&
DRVCTRL7_MASK
)
|
DRVCTRL7_A12
(
3
)
|
DRVCTRL7_A13
(
3
)
|
DRVCTRL7_A14
(
3
)
|
DRVCTRL7_A15
(
3
)
|
DRVCTRL7_A16
(
3
)
|
DRVCTRL7_A17
(
3
)
|
DRVCTRL7_A18
(
3
)
|
DRVCTRL7_A19
(
3
));
pfc_reg_write
(
PFC_DRVCTRL7
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL8
);
reg
=
((
reg
&
DRVCTRL8_MASK
)
|
DRVCTRL8_CLKOUT
(
7
)
|
DRVCTRL8_CS0
(
7
)
|
DRVCTRL8_CS1_A2
(
7
)
|
DRVCTRL8_BS
(
7
)
|
DRVCTRL8_RD
(
7
)
|
DRVCTRL8_RD_W
(
7
)
|
DRVCTRL8_WE0
(
7
)
|
DRVCTRL8_WE1
(
7
));
pfc_reg_write
(
PFC_DRVCTRL8
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL9
);
reg
=
((
reg
&
DRVCTRL9_MASK
)
|
DRVCTRL9_EX_WAIT0
(
7
)
|
DRVCTRL9_PRESETOU
(
7
)
|
DRVCTRL9_D0
(
7
)
|
DRVCTRL9_D1
(
7
)
|
DRVCTRL9_D2
(
7
)
|
DRVCTRL9_D3
(
7
)
|
DRVCTRL9_D4
(
7
)
|
DRVCTRL9_D5
(
7
));
pfc_reg_write
(
PFC_DRVCTRL9
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL10
);
reg
=
((
reg
&
DRVCTRL10_MASK
)
|
DRVCTRL10_D6
(
7
)
|
DRVCTRL10_D7
(
7
)
|
DRVCTRL10_D8
(
3
)
|
DRVCTRL10_D9
(
3
)
|
DRVCTRL10_D10
(
3
)
|
DRVCTRL10_D11
(
3
)
|
DRVCTRL10_D12
(
3
)
|
DRVCTRL10_D13
(
3
));
pfc_reg_write
(
PFC_DRVCTRL10
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL11
);
reg
=
((
reg
&
DRVCTRL11_MASK
)
|
DRVCTRL11_D14
(
3
)
|
DRVCTRL11_D15
(
3
)
|
DRVCTRL11_AVS1
(
7
)
|
DRVCTRL11_AVS2
(
7
)
|
DRVCTRL11_HDMI0_CEC
(
7
)
|
DRVCTRL11_HDMI1_CEC
(
7
)
|
DRVCTRL11_DU_DOTCLKIN0
(
3
)
|
DRVCTRL11_DU_DOTCLKIN1
(
3
));
pfc_reg_write
(
PFC_DRVCTRL11
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL12
);
reg
=
((
reg
&
DRVCTRL12_MASK
)
|
DRVCTRL12_DU_DOTCLKIN2
(
3
)
|
DRVCTRL12_DU_DOTCLKIN3
(
3
)
|
DRVCTRL12_DU_FSCLKST
(
3
)
|
DRVCTRL12_DU_TMS
(
3
));
pfc_reg_write
(
PFC_DRVCTRL12
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL13
);
reg
=
((
reg
&
DRVCTRL13_MASK
)
|
DRVCTRL13_TDO
(
3
)
|
DRVCTRL13_ASEBRK
(
3
)
|
DRVCTRL13_SD0_CLK
(
2
)
|
DRVCTRL13_SD0_CMD
(
2
)
|
DRVCTRL13_SD0_DAT0
(
2
)
|
DRVCTRL13_SD0_DAT1
(
2
)
|
DRVCTRL13_SD0_DAT2
(
2
)
|
DRVCTRL13_SD0_DAT3
(
2
));
pfc_reg_write
(
PFC_DRVCTRL13
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL14
);
reg
=
((
reg
&
DRVCTRL14_MASK
)
|
DRVCTRL14_SD1_CLK
(
7
)
|
DRVCTRL14_SD1_CMD
(
7
)
|
DRVCTRL14_SD1_DAT0
(
5
)
|
DRVCTRL14_SD1_DAT1
(
5
)
|
DRVCTRL14_SD1_DAT2
(
5
)
|
DRVCTRL14_SD1_DAT3
(
5
)
|
DRVCTRL14_SD2_CLK
(
5
)
|
DRVCTRL14_SD2_CMD
(
5
));
pfc_reg_write
(
PFC_DRVCTRL14
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL15
);
reg
=
((
reg
&
DRVCTRL15_MASK
)
|
DRVCTRL15_SD2_DAT0
(
5
)
|
DRVCTRL15_SD2_DAT1
(
5
)
|
DRVCTRL15_SD2_DAT2
(
5
)
|
DRVCTRL15_SD2_DAT3
(
5
)
|
DRVCTRL15_SD2_DS
(
5
)
|
DRVCTRL15_SD3_CLK
(
2
)
|
DRVCTRL15_SD3_CMD
(
2
)
|
DRVCTRL15_SD3_DAT0
(
2
));
pfc_reg_write
(
PFC_DRVCTRL15
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL16
);
reg
=
((
reg
&
DRVCTRL16_MASK
)
|
DRVCTRL16_SD3_DAT1
(
2
)
|
DRVCTRL16_SD3_DAT2
(
2
)
|
DRVCTRL16_SD3_DAT3
(
2
)
|
DRVCTRL16_SD3_DAT4
(
7
)
|
DRVCTRL16_SD3_DAT5
(
7
)
|
DRVCTRL16_SD3_DAT6
(
7
)
|
DRVCTRL16_SD3_DAT7
(
7
)
|
DRVCTRL16_SD3_DS
(
7
));
pfc_reg_write
(
PFC_DRVCTRL16
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL17
);
reg
=
((
reg
&
DRVCTRL17_MASK
)
|
DRVCTRL17_SD0_CD
(
7
)
|
DRVCTRL17_SD0_WP
(
7
)
|
DRVCTRL17_SD1_CD
(
7
)
|
DRVCTRL17_SD1_WP
(
7
)
|
DRVCTRL17_SCK0
(
7
)
|
DRVCTRL17_RX0
(
7
)
|
DRVCTRL17_TX0
(
7
)
|
DRVCTRL17_CTS0
(
7
));
pfc_reg_write
(
PFC_DRVCTRL17
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL18
);
reg
=
((
reg
&
DRVCTRL18_MASK
)
|
DRVCTRL18_RTS0_TANS
(
7
)
|
DRVCTRL18_RX1
(
7
)
|
DRVCTRL18_TX1
(
7
)
|
DRVCTRL18_CTS1
(
7
)
|
DRVCTRL18_RTS1_TANS
(
7
)
|
DRVCTRL18_SCK2
(
7
)
|
DRVCTRL18_TX2
(
7
)
|
DRVCTRL18_RX2
(
7
));
pfc_reg_write
(
PFC_DRVCTRL18
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL19
);
reg
=
((
reg
&
DRVCTRL19_MASK
)
|
DRVCTRL19_HSCK0
(
7
)
|
DRVCTRL19_HRX0
(
7
)
|
DRVCTRL19_HTX0
(
7
)
|
DRVCTRL19_HCTS0
(
7
)
|
DRVCTRL19_HRTS0
(
7
)
|
DRVCTRL19_MSIOF0_SCK
(
7
)
|
DRVCTRL19_MSIOF0_SYNC
(
7
)
|
DRVCTRL19_MSIOF0_SS1
(
7
));
pfc_reg_write
(
PFC_DRVCTRL19
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL20
);
reg
=
((
reg
&
DRVCTRL20_MASK
)
|
DRVCTRL20_MSIOF0_TXD
(
7
)
|
DRVCTRL20_MSIOF0_SS2
(
7
)
|
DRVCTRL20_MSIOF0_RXD
(
7
)
|
DRVCTRL20_MLB_CLK
(
7
)
|
DRVCTRL20_MLB_SIG
(
7
)
|
DRVCTRL20_MLB_DAT
(
7
)
|
DRVCTRL20_MLB_REF
(
7
)
|
DRVCTRL20_SSI_SCK0129
(
7
));
pfc_reg_write
(
PFC_DRVCTRL20
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL21
);
reg
=
((
reg
&
DRVCTRL21_MASK
)
|
DRVCTRL21_SSI_WS0129
(
7
)
|
DRVCTRL21_SSI_SDATA0
(
7
)
|
DRVCTRL21_SSI_SDATA1
(
7
)
|
DRVCTRL21_SSI_SDATA2
(
7
)
|
DRVCTRL21_SSI_SCK34
(
7
)
|
DRVCTRL21_SSI_WS34
(
7
)
|
DRVCTRL21_SSI_SDATA3
(
7
)
|
DRVCTRL21_SSI_SCK4
(
7
));
pfc_reg_write
(
PFC_DRVCTRL21
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL22
);
reg
=
((
reg
&
DRVCTRL22_MASK
)
|
DRVCTRL22_SSI_WS4
(
7
)
|
DRVCTRL22_SSI_SDATA4
(
7
)
|
DRVCTRL22_SSI_SCK5
(
7
)
|
DRVCTRL22_SSI_WS5
(
7
)
|
DRVCTRL22_SSI_SDATA5
(
7
)
|
DRVCTRL22_SSI_SCK6
(
7
)
|
DRVCTRL22_SSI_WS6
(
7
)
|
DRVCTRL22_SSI_SDATA6
(
7
));
pfc_reg_write
(
PFC_DRVCTRL22
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL23
);
reg
=
((
reg
&
DRVCTRL23_MASK
)
|
DRVCTRL23_SSI_SCK78
(
7
)
|
DRVCTRL23_SSI_WS78
(
7
)
|
DRVCTRL23_SSI_SDATA7
(
7
)
|
DRVCTRL23_SSI_SDATA8
(
7
)
|
DRVCTRL23_SSI_SDATA9
(
7
)
|
DRVCTRL23_AUDIO_CLKA
(
7
)
|
DRVCTRL23_AUDIO_CLKB
(
7
)
|
DRVCTRL23_USB0_PWEN
(
7
));
pfc_reg_write
(
PFC_DRVCTRL23
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL24
);
reg
=
((
reg
&
DRVCTRL24_MASK
)
|
DRVCTRL24_USB0_OVC
(
7
)
|
DRVCTRL24_USB1_PWEN
(
7
)
|
DRVCTRL24_USB1_OVC
(
7
)
|
DRVCTRL24_USB30_PWEN
(
7
)
|
DRVCTRL24_USB30_OVC
(
7
)
|
DRVCTRL24_USB31_PWEN
(
7
)
|
DRVCTRL24_USB31_OVC
(
7
));
pfc_reg_write
(
PFC_DRVCTRL24
,
reg
);
/* initialize LSI pin pull-up/down control */
pfc_reg_write
(
PFC_PUD0
,
0x00005FBFU
);
pfc_reg_write
(
PFC_PUD1
,
0x00300FFEU
);
pfc_reg_write
(
PFC_PUD2
,
0x330001E6U
);
pfc_reg_write
(
PFC_PUD3
,
0x000002E0U
);
pfc_reg_write
(
PFC_PUD4
,
0xFFFFFF00U
);
pfc_reg_write
(
PFC_PUD5
,
0x7F5FFF87U
);
pfc_reg_write
(
PFC_PUD6
,
0x00000055U
);
/* initialize LSI pin pull-enable register */
pfc_reg_write
(
PFC_PUEN0
,
0x00000FFFU
);
pfc_reg_write
(
PFC_PUEN1
,
0x00100234U
);
pfc_reg_write
(
PFC_PUEN2
,
0x000004C4U
);
pfc_reg_write
(
PFC_PUEN3
,
0x00000200U
);
pfc_reg_write
(
PFC_PUEN4
,
0x3E000000U
);
pfc_reg_write
(
PFC_PUEN5
,
0x1F000805U
);
pfc_reg_write
(
PFC_PUEN6
,
0x00000006U
);
/* initialize positive/negative logic select */
mmio_write_32
(
GPIO_POSNEG0
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG1
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG2
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG3
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG4
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG5
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG6
,
0x00000000U
);
/* initialize general IO/interrupt switching */
mmio_write_32
(
GPIO_IOINTSEL0
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL1
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL2
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL3
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL4
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL5
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL6
,
0x00000000U
);
/* initialize general output register */
mmio_write_32
(
GPIO_OUTDT1
,
0x00000000U
);
mmio_write_32
(
GPIO_OUTDT2
,
0x00000400U
);
mmio_write_32
(
GPIO_OUTDT3
,
0x0000C000U
);
mmio_write_32
(
GPIO_OUTDT5
,
0x00000006U
);
mmio_write_32
(
GPIO_OUTDT6
,
0x00003880U
);
/* initialize general input/output switching */
mmio_write_32
(
GPIO_INOUTSEL0
,
0x00000000U
);
mmio_write_32
(
GPIO_INOUTSEL1
,
0x01000A00U
);
mmio_write_32
(
GPIO_INOUTSEL2
,
0x00000400U
);
mmio_write_32
(
GPIO_INOUTSEL3
,
0x0000C000U
);
mmio_write_32
(
GPIO_INOUTSEL4
,
0x00000000U
);
mmio_write_32
(
GPIO_INOUTSEL5
,
0x0000020EU
);
mmio_write_32
(
GPIO_INOUTSEL6
,
0x00013880U
);
}
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PFC_INIT_H3_V1_H__
#define PFC_INIT_H3_V1_H__
void
pfc_init_h3_v1
(
void
);
#endif
/* PFC_INIT_H3_V1_H__ */
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
/* for uint32_t */
#include <mmio.h>
#include "pfc_init_h3_v2.h"
#include "rcar_def.h"
/* GPIO base address */
#define GPIO_BASE (0xE6050000U)
/* GPIO registers */
#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U)
#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U)
#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U)
#define GPIO_INDT0 (GPIO_BASE + 0x000CU)
#define GPIO_INTDT0 (GPIO_BASE + 0x0010U)
#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U)
#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U)
#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU)
#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U)
#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U)
#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U)
#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U)
#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU)
#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U)
#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U)
#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U)
#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU)
#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U)
#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U)
#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
#define GPIO_INTDT1 (GPIO_BASE + 0x1010U)
#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U)
#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U)
#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU)
#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U)
#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U)
#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U)
#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U)
#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU)
#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U)
#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U)
#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U)
#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU)
#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U)
#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U)
#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U)
#define GPIO_INDT2 (GPIO_BASE + 0x200CU)
#define GPIO_INTDT2 (GPIO_BASE + 0x2010U)
#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U)
#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U)
#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU)
#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U)
#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U)
#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U)
#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U)
#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU)
#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U)
#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U)
#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U)
#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU)
#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U)
#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U)
#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
#define GPIO_INTDT3 (GPIO_BASE + 0x3010U)
#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U)
#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U)
#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU)
#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U)
#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U)
#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U)
#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U)
#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU)
#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U)
#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U)
#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U)
#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU)
#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U)
#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U)
#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U)
#define GPIO_INDT4 (GPIO_BASE + 0x400CU)
#define GPIO_INTDT4 (GPIO_BASE + 0x4010U)
#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U)
#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U)
#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU)
#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U)
#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U)
#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U)
#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U)
#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU)
#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U)
#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U)
#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U)
#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU)
#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U)
#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U)
#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U)
#define GPIO_INDT5 (GPIO_BASE + 0x500CU)
#define GPIO_INTDT5 (GPIO_BASE + 0x5010U)
#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U)
#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U)
#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU)
#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U)
#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U)
#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U)
#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U)
#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU)
#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U)
#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U)
#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U)
#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU)
#define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U)
#define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U)
#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
#define GPIO_INTDT6 (GPIO_BASE + 0x5410U)
#define GPIO_INTCLR6 (GPIO_BASE + 0x5414U)
#define GPIO_INTMSK6 (GPIO_BASE + 0x5418U)
#define GPIO_MSKCLR6 (GPIO_BASE + 0x541CU)
#define GPIO_POSNEG6 (GPIO_BASE + 0x5420U)
#define GPIO_EDGLEVEL6 (GPIO_BASE + 0x5424U)
#define GPIO_FILONOFF6 (GPIO_BASE + 0x5428U)
#define GPIO_INTMSKS6 (GPIO_BASE + 0x5438U)
#define GPIO_MSKCLRS6 (GPIO_BASE + 0x543CU)
#define GPIO_OUTDTSEL6 (GPIO_BASE + 0x5440U)
#define GPIO_OUTDTH6 (GPIO_BASE + 0x5444U)
#define GPIO_OUTDTL6 (GPIO_BASE + 0x5448U)
#define GPIO_BOTHEDGE6 (GPIO_BASE + 0x544CU)
#define GPIO_IOINTSEL7 (GPIO_BASE + 0x5800U)
#define GPIO_INOUTSEL7 (GPIO_BASE + 0x5804U)
#define GPIO_OUTDT7 (GPIO_BASE + 0x5808U)
#define GPIO_INDT7 (GPIO_BASE + 0x580CU)
#define GPIO_INTDT7 (GPIO_BASE + 0x5810U)
#define GPIO_INTCLR7 (GPIO_BASE + 0x5814U)
#define GPIO_INTMSK7 (GPIO_BASE + 0x5818U)
#define GPIO_MSKCLR7 (GPIO_BASE + 0x581CU)
#define GPIO_POSNEG7 (GPIO_BASE + 0x5820U)
#define GPIO_EDGLEVEL7 (GPIO_BASE + 0x5824U)
#define GPIO_FILONOFF7 (GPIO_BASE + 0x5828U)
#define GPIO_INTMSKS7 (GPIO_BASE + 0x5838U)
#define GPIO_MSKCLRS7 (GPIO_BASE + 0x583CU)
#define GPIO_OUTDTSEL7 (GPIO_BASE + 0x5840U)
#define GPIO_OUTDTH7 (GPIO_BASE + 0x5844U)
#define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U)
#define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU)
/* Pin functon base address */
#define PFC_BASE (0xE6060000U)
/* Pin functon registers */
#define PFC_PMMR (PFC_BASE + 0x0000U)
#define PFC_GPSR0 (PFC_BASE + 0x0100U)
#define PFC_GPSR1 (PFC_BASE + 0x0104U)
#define PFC_GPSR2 (PFC_BASE + 0x0108U)
#define PFC_GPSR3 (PFC_BASE + 0x010CU)
#define PFC_GPSR4 (PFC_BASE + 0x0110U)
#define PFC_GPSR5 (PFC_BASE + 0x0114U)
#define PFC_GPSR6 (PFC_BASE + 0x0118U)
#define PFC_GPSR7 (PFC_BASE + 0x011CU)
#define PFC_IPSR0 (PFC_BASE + 0x0200U)
#define PFC_IPSR1 (PFC_BASE + 0x0204U)
#define PFC_IPSR2 (PFC_BASE + 0x0208U)
#define PFC_IPSR3 (PFC_BASE + 0x020CU)
#define PFC_IPSR4 (PFC_BASE + 0x0210U)
#define PFC_IPSR5 (PFC_BASE + 0x0214U)
#define PFC_IPSR6 (PFC_BASE + 0x0218U)
#define PFC_IPSR7 (PFC_BASE + 0x021CU)
#define PFC_IPSR8 (PFC_BASE + 0x0220U)
#define PFC_IPSR9 (PFC_BASE + 0x0224U)
#define PFC_IPSR10 (PFC_BASE + 0x0228U)
#define PFC_IPSR11 (PFC_BASE + 0x022CU)
#define PFC_IPSR12 (PFC_BASE + 0x0230U)
#define PFC_IPSR13 (PFC_BASE + 0x0234U)
#define PFC_IPSR14 (PFC_BASE + 0x0238U)
#define PFC_IPSR15 (PFC_BASE + 0x023CU)
#define PFC_IPSR16 (PFC_BASE + 0x0240U)
#define PFC_IPSR17 (PFC_BASE + 0x0244U)
#define PFC_IPSR18 (PFC_BASE + 0x0248U)
#define PFC_DRVCTRL0 (PFC_BASE + 0x0300U)
#define PFC_DRVCTRL1 (PFC_BASE + 0x0304U)
#define PFC_DRVCTRL2 (PFC_BASE + 0x0308U)
#define PFC_DRVCTRL3 (PFC_BASE + 0x030CU)
#define PFC_DRVCTRL4 (PFC_BASE + 0x0310U)
#define PFC_DRVCTRL5 (PFC_BASE + 0x0314U)
#define PFC_DRVCTRL6 (PFC_BASE + 0x0318U)
#define PFC_DRVCTRL7 (PFC_BASE + 0x031CU)
#define PFC_DRVCTRL8 (PFC_BASE + 0x0320U)
#define PFC_DRVCTRL9 (PFC_BASE + 0x0324U)
#define PFC_DRVCTRL10 (PFC_BASE + 0x0328U)
#define PFC_DRVCTRL11 (PFC_BASE + 0x032CU)
#define PFC_DRVCTRL12 (PFC_BASE + 0x0330U)
#define PFC_DRVCTRL13 (PFC_BASE + 0x0334U)
#define PFC_DRVCTRL14 (PFC_BASE + 0x0338U)
#define PFC_DRVCTRL15 (PFC_BASE + 0x033CU)
#define PFC_DRVCTRL16 (PFC_BASE + 0x0340U)
#define PFC_DRVCTRL17 (PFC_BASE + 0x0344U)
#define PFC_DRVCTRL18 (PFC_BASE + 0x0348U)
#define PFC_DRVCTRL19 (PFC_BASE + 0x034CU)
#define PFC_DRVCTRL20 (PFC_BASE + 0x0350U)
#define PFC_DRVCTRL21 (PFC_BASE + 0x0354U)
#define PFC_DRVCTRL22 (PFC_BASE + 0x0358U)
#define PFC_DRVCTRL23 (PFC_BASE + 0x035CU)
#define PFC_DRVCTRL24 (PFC_BASE + 0x0360U)
#define PFC_POCCTRL0 (PFC_BASE + 0x0380U)
#define PFC_TDSELCTRL0 (PFC_BASE + 0x03C0U)
#define PFC_IOCTRL (PFC_BASE + 0x03E0U)
#define PFC_TSREG (PFC_BASE + 0x03E4U)
#define PFC_PUEN0 (PFC_BASE + 0x0400U)
#define PFC_PUEN1 (PFC_BASE + 0x0404U)
#define PFC_PUEN2 (PFC_BASE + 0x0408U)
#define PFC_PUEN3 (PFC_BASE + 0x040CU)
#define PFC_PUEN4 (PFC_BASE + 0x0410U)
#define PFC_PUEN5 (PFC_BASE + 0x0414U)
#define PFC_PUEN6 (PFC_BASE + 0x0418U)
#define PFC_PUD0 (PFC_BASE + 0x0440U)
#define PFC_PUD1 (PFC_BASE + 0x0444U)
#define PFC_PUD2 (PFC_BASE + 0x0448U)
#define PFC_PUD3 (PFC_BASE + 0x044CU)
#define PFC_PUD4 (PFC_BASE + 0x0450U)
#define PFC_PUD5 (PFC_BASE + 0x0454U)
#define PFC_PUD6 (PFC_BASE + 0x0458U)
#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U)
#define PFC_MOD_SEL1 (PFC_BASE + 0x0504U)
#define PFC_MOD_SEL2 (PFC_BASE + 0x0508U)
#define GPSR0_D15 ((uint32_t)1U << 15U)
#define GPSR0_D14 ((uint32_t)1U << 14U)
#define GPSR0_D13 ((uint32_t)1U << 13U)
#define GPSR0_D12 ((uint32_t)1U << 12U)
#define GPSR0_D11 ((uint32_t)1U << 11U)
#define GPSR0_D10 ((uint32_t)1U << 10U)
#define GPSR0_D9 ((uint32_t)1U << 9U)
#define GPSR0_D8 ((uint32_t)1U << 8U)
#define GPSR0_D7 ((uint32_t)1U << 7U)
#define GPSR0_D6 ((uint32_t)1U << 6U)
#define GPSR0_D5 ((uint32_t)1U << 5U)
#define GPSR0_D4 ((uint32_t)1U << 4U)
#define GPSR0_D3 ((uint32_t)1U << 3U)
#define GPSR0_D2 ((uint32_t)1U << 2U)
#define GPSR0_D1 ((uint32_t)1U << 1U)
#define GPSR0_D0 ((uint32_t)1U << 0U)
#define GPSR1_CLKOUT ((uint32_t)1U << 28U)
#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U)
#define GPSR1_WE1 ((uint32_t)1U << 26U)
#define GPSR1_WE0 ((uint32_t)1U << 25U)
#define GPSR1_RD_WR ((uint32_t)1U << 24U)
#define GPSR1_RD ((uint32_t)1U << 23U)
#define GPSR1_BS ((uint32_t)1U << 22U)
#define GPSR1_CS1_A26 ((uint32_t)1U << 21U)
#define GPSR1_CS0 ((uint32_t)1U << 20U)
#define GPSR1_A19 ((uint32_t)1U << 19U)
#define GPSR1_A18 ((uint32_t)1U << 18U)
#define GPSR1_A17 ((uint32_t)1U << 17U)
#define GPSR1_A16 ((uint32_t)1U << 16U)
#define GPSR1_A15 ((uint32_t)1U << 15U)
#define GPSR1_A14 ((uint32_t)1U << 14U)
#define GPSR1_A13 ((uint32_t)1U << 13U)
#define GPSR1_A12 ((uint32_t)1U << 12U)
#define GPSR1_A11 ((uint32_t)1U << 11U)
#define GPSR1_A10 ((uint32_t)1U << 10U)
#define GPSR1_A9 ((uint32_t)1U << 9U)
#define GPSR1_A8 ((uint32_t)1U << 8U)
#define GPSR1_A7 ((uint32_t)1U << 7U)
#define GPSR1_A6 ((uint32_t)1U << 6U)
#define GPSR1_A5 ((uint32_t)1U << 5U)
#define GPSR1_A4 ((uint32_t)1U << 4U)
#define GPSR1_A3 ((uint32_t)1U << 3U)
#define GPSR1_A2 ((uint32_t)1U << 2U)
#define GPSR1_A1 ((uint32_t)1U << 1U)
#define GPSR1_A0 ((uint32_t)1U << 0U)
#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U)
#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U)
#define GPSR2_AVB_LINK ((uint32_t)1U << 12U)
#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U)
#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U)
#define GPSR2_AVB_MDC ((uint32_t)1U << 9U)
#define GPSR2_PWM2_A ((uint32_t)1U << 8U)
#define GPSR2_PWM1_A ((uint32_t)1U << 7U)
#define GPSR2_PWM0 ((uint32_t)1U << 6U)
#define GPSR2_IRQ5 ((uint32_t)1U << 5U)
#define GPSR2_IRQ4 ((uint32_t)1U << 4U)
#define GPSR2_IRQ3 ((uint32_t)1U << 3U)
#define GPSR2_IRQ2 ((uint32_t)1U << 2U)
#define GPSR2_IRQ1 ((uint32_t)1U << 1U)
#define GPSR2_IRQ0 ((uint32_t)1U << 0U)
#define GPSR3_SD1_WP ((uint32_t)1U << 15U)
#define GPSR3_SD1_CD ((uint32_t)1U << 14U)
#define GPSR3_SD0_WP ((uint32_t)1U << 13U)
#define GPSR3_SD0_CD ((uint32_t)1U << 12U)
#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U)
#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U)
#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U)
#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U)
#define GPSR3_SD1_CMD ((uint32_t)1U << 7U)
#define GPSR3_SD1_CLK ((uint32_t)1U << 6U)
#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U)
#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U)
#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U)
#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U)
#define GPSR3_SD0_CMD ((uint32_t)1U << 1U)
#define GPSR3_SD0_CLK ((uint32_t)1U << 0U)
#define GPSR4_SD3_DS ((uint32_t)1U << 17U)
#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U)
#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U)
#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U)
#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U)
#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U)
#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U)
#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U)
#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U)
#define GPSR4_SD3_CMD ((uint32_t)1U << 8U)
#define GPSR4_SD3_CLK ((uint32_t)1U << 7U)
#define GPSR4_SD2_DS ((uint32_t)1U << 6U)
#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U)
#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U)
#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U)
#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U)
#define GPSR4_SD2_CMD ((uint32_t)1U << 1U)
#define GPSR4_SD2_CLK ((uint32_t)1U << 0U)
#define GPSR5_MLB_DAT ((uint32_t)1U << 25U)
#define GPSR5_MLB_SIG ((uint32_t)1U << 24U)
#define GPSR5_MLB_CLK ((uint32_t)1U << 23U)
#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U)
#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U)
#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U)
#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U)
#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U)
#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U)
#define GPSR5_HRTS0 ((uint32_t)1U << 16U)
#define GPSR5_HCTS0 ((uint32_t)1U << 15U)
#define GPSR5_HTX0 ((uint32_t)1U << 14U)
#define GPSR5_HRX0 ((uint32_t)1U << 13U)
#define GPSR5_HSCK0 ((uint32_t)1U << 12U)
#define GPSR5_RX2_A ((uint32_t)1U << 11U)
#define GPSR5_TX2_A ((uint32_t)1U << 10U)
#define GPSR5_SCK2 ((uint32_t)1U << 9U)
#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U)
#define GPSR5_CTS1 ((uint32_t)1U << 7U)
#define GPSR5_TX1_A ((uint32_t)1U << 6U)
#define GPSR5_RX1_A ((uint32_t)1U << 5U)
#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U)
#define GPSR5_CTS0 ((uint32_t)1U << 3U)
#define GPSR5_TX0 ((uint32_t)1U << 2U)
#define GPSR5_RX0 ((uint32_t)1U << 1U)
#define GPSR5_SCK0 ((uint32_t)1U << 0U)
#define GPSR6_USB31_OVC ((uint32_t)1U << 31U)
#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U)
#define GPSR6_USB30_OVC ((uint32_t)1U << 29U)
#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U)
#define GPSR6_USB1_OVC ((uint32_t)1U << 27U)
#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U)
#define GPSR6_USB0_OVC ((uint32_t)1U << 25U)
#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U)
#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U)
#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U)
#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U)
#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U)
#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U)
#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U)
#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U)
#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U)
#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U)
#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U)
#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U)
#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U)
#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U)
#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U)
#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U)
#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U)
#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U)
#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U)
#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U)
#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U)
#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U)
#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U)
#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U)
#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U)
#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U)
#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U)
#define GPSR7_AVS2 ((uint32_t)1U << 1U)
#define GPSR7_AVS1 ((uint32_t)1U << 0U)
#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
#define POC_SD3_DS_33V ((uint32_t)1U << 29U)
#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U)
#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U)
#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U)
#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U)
#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U)
#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U)
#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U)
#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U)
#define POC_SD3_CMD_33V ((uint32_t)1U << 20U)
#define POC_SD3_CLK_33V ((uint32_t)1U << 19U)
#define POC_SD2_DS_33V ((uint32_t)1U << 18U)
#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U)
#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U)
#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U)
#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U)
#define POC_SD2_CMD_33V ((uint32_t)1U << 13U)
#define POC_SD2_CLK_33V ((uint32_t)1U << 12U)
#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U)
#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U)
#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U)
#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U)
#define POC_SD1_CMD_33V ((uint32_t)1U << 7U)
#define POC_SD1_CLK_33V ((uint32_t)1U << 6U)
#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U)
#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U)
#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U)
#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U)
#define POC_SD0_CMD_33V ((uint32_t)1U << 1U)
#define POC_SD0_CLK_33V ((uint32_t)1U << 0U)
#define DRVCTRL0_MASK (0xCCCCCCCCU)
#define DRVCTRL1_MASK (0xCCCCCCC8U)
#define DRVCTRL2_MASK (0x88888888U)
#define DRVCTRL3_MASK (0x88888888U)
#define DRVCTRL4_MASK (0x88888888U)
#define DRVCTRL5_MASK (0x88888888U)
#define DRVCTRL6_MASK (0x88888888U)
#define DRVCTRL7_MASK (0x88888888U)
#define DRVCTRL8_MASK (0x88888888U)
#define DRVCTRL9_MASK (0x88888888U)
#define DRVCTRL10_MASK (0x88888888U)
#define DRVCTRL11_MASK (0x888888CCU)
#define DRVCTRL12_MASK (0xCCCFFFCFU)
#define DRVCTRL13_MASK (0xCC888888U)
#define DRVCTRL14_MASK (0x88888888U)
#define DRVCTRL15_MASK (0x88888888U)
#define DRVCTRL16_MASK (0x88888888U)
#define DRVCTRL17_MASK (0x88888888U)
#define DRVCTRL18_MASK (0x88888888U)
#define DRVCTRL19_MASK (0x88888888U)
#define DRVCTRL20_MASK (0x88888888U)
#define DRVCTRL21_MASK (0x88888888U)
#define DRVCTRL22_MASK (0x88888888U)
#define DRVCTRL23_MASK (0x88888888U)
#define DRVCTRL24_MASK (0x8888888FU)
#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
/* SCIF3 Registers for Dummy write */
#define SCIF3_BASE (0xE6C50000U)
#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U)
#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU)
#define SCFCR_DATA (0x0000U)
/* Realtime module stop control */
#define CPG_BASE (0xE6150000U)
#define CPG_MSTPSR0 (CPG_BASE + 0x0030U)
#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U)
#define RMSTPCR0_RTDMAC (0x00200000U)
static
void
pfc_reg_write
(
uint32_t
addr
,
uint32_t
data
);
static
void
pfc_reg_write
(
uint32_t
addr
,
uint32_t
data
)
{
mmio_write_32
(
PFC_PMMR
,
~
data
);
mmio_write_32
((
uintptr_t
)
addr
,
data
);
}
void
pfc_init_h3_v2
(
void
)
{
uint32_t
reg
;
/* initialize module select */
pfc_reg_write
(
PFC_MOD_SEL0
,
MOD_SEL0_MSIOF3_A
|
MOD_SEL0_MSIOF2_A
|
MOD_SEL0_MSIOF1_A
|
MOD_SEL0_LBSC_A
|
MOD_SEL0_IEBUS_A
|
MOD_SEL0_I2C2_A
|
MOD_SEL0_I2C1_A
|
MOD_SEL0_HSCIF4_A
|
MOD_SEL0_HSCIF3_A
|
MOD_SEL0_HSCIF1_A
|
MOD_SEL0_FSO_A
|
MOD_SEL0_HSCIF2_A
|
MOD_SEL0_ETHERAVB_A
|
MOD_SEL0_DRIF3_A
|
MOD_SEL0_DRIF2_A
|
MOD_SEL0_DRIF1_A
|
MOD_SEL0_DRIF0_A
|
MOD_SEL0_CANFD0_A
|
MOD_SEL0_ADG_A_A
);
pfc_reg_write
(
PFC_MOD_SEL1
,
MOD_SEL1_TSIF1_A
|
MOD_SEL1_TSIF0_A
|
MOD_SEL1_TIMER_TMU_A
|
MOD_SEL1_SSP1_1_A
|
MOD_SEL1_SSP1_0_A
|
MOD_SEL1_SSI_A
|
MOD_SEL1_SPEED_PULSE_IF_A
|
MOD_SEL1_SIMCARD_A
|
MOD_SEL1_SDHI2_A
|
MOD_SEL1_SCIF4_A
|
MOD_SEL1_SCIF3_A
|
MOD_SEL1_SCIF2_A
|
MOD_SEL1_SCIF1_A
|
MOD_SEL1_SCIF_A
|
MOD_SEL1_REMOCON_A
|
MOD_SEL1_RCAN0_A
|
MOD_SEL1_PWM6_A
|
MOD_SEL1_PWM5_A
|
MOD_SEL1_PWM4_A
|
MOD_SEL1_PWM3_A
|
MOD_SEL1_PWM2_A
|
MOD_SEL1_PWM1_A
);
pfc_reg_write
(
PFC_MOD_SEL2
,
MOD_SEL2_I2C_5_A
|
MOD_SEL2_I2C_3_A
|
MOD_SEL2_I2C_0_A
|
MOD_SEL2_FM_A
|
MOD_SEL2_SCIF5_A
|
MOD_SEL2_I2C6_A
|
MOD_SEL2_NDF_A
|
MOD_SEL2_SSI2_A
|
MOD_SEL2_SSI9_A
|
MOD_SEL2_TIMER_TMU2_A
|
MOD_SEL2_ADG_B_A
|
MOD_SEL2_ADG_C_A
|
MOD_SEL2_VIN4_A
);
/* initialize peripheral function select */
pfc_reg_write
(
PFC_IPSR0
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR1
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
3
)
|
IPSR_8_FUNC
(
3
)
|
IPSR_4_FUNC
(
3
)
|
IPSR_0_FUNC
(
3
));
pfc_reg_write
(
PFC_IPSR2
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR3
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR4
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR5
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR6
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR7
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR8
,
IPSR_28_FUNC
(
1
)
|
IPSR_24_FUNC
(
1
)
|
IPSR_20_FUNC
(
1
)
|
IPSR_16_FUNC
(
1
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR9
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR10
,
IPSR_28_FUNC
(
1
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR11
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
4
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
1
));
pfc_reg_write
(
PFC_IPSR12
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
4
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR13
,
IPSR_28_FUNC
(
8
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
3
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR14
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
3
)
|
IPSR_0_FUNC
(
8
));
pfc_reg_write
(
PFC_IPSR15
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR16
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR17
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
1
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR18
,
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
/* initialize GPIO/perihperal function select */
pfc_reg_write
(
PFC_GPSR0
,
GPSR0_D15
|
GPSR0_D14
|
GPSR0_D13
|
GPSR0_D12
|
GPSR0_D11
|
GPSR0_D10
|
GPSR0_D9
|
GPSR0_D8
);
pfc_reg_write
(
PFC_GPSR1
,
GPSR1_CLKOUT
|
GPSR1_EX_WAIT0_A
|
GPSR1_A19
|
GPSR1_A18
|
GPSR1_A17
|
GPSR1_A16
|
GPSR1_A15
|
GPSR1_A14
|
GPSR1_A13
|
GPSR1_A12
|
GPSR1_A7
|
GPSR1_A6
|
GPSR1_A5
|
GPSR1_A4
|
GPSR1_A3
|
GPSR1_A2
|
GPSR1_A1
|
GPSR1_A0
);
pfc_reg_write
(
PFC_GPSR2
,
GPSR2_AVB_AVTP_CAPTURE_A
|
GPSR2_AVB_AVTP_MATCH_A
|
GPSR2_AVB_LINK
|
GPSR2_AVB_PHY_INT
|
GPSR2_AVB_MDC
|
GPSR2_PWM2_A
|
GPSR2_PWM1_A
|
GPSR2_IRQ5
|
GPSR2_IRQ4
|
GPSR2_IRQ3
|
GPSR2_IRQ2
|
GPSR2_IRQ1
|
GPSR2_IRQ0
);
pfc_reg_write
(
PFC_GPSR3
,
GPSR3_SD0_WP
|
GPSR3_SD0_CD
|
GPSR3_SD1_DAT3
|
GPSR3_SD1_DAT2
|
GPSR3_SD1_DAT1
|
GPSR3_SD1_DAT0
|
GPSR3_SD0_DAT3
|
GPSR3_SD0_DAT2
|
GPSR3_SD0_DAT1
|
GPSR3_SD0_DAT0
|
GPSR3_SD0_CMD
|
GPSR3_SD0_CLK
);
pfc_reg_write
(
PFC_GPSR4
,
GPSR4_SD3_DAT7
|
GPSR4_SD3_DAT6
|
GPSR4_SD3_DAT3
|
GPSR4_SD3_DAT2
|
GPSR4_SD3_DAT1
|
GPSR4_SD3_DAT0
|
GPSR4_SD3_CMD
|
GPSR4_SD3_CLK
|
GPSR4_SD2_DS
|
GPSR4_SD2_DAT3
|
GPSR4_SD2_DAT2
|
GPSR4_SD2_DAT1
|
GPSR4_SD2_DAT0
|
GPSR4_SD2_CMD
|
GPSR4_SD2_CLK
);
pfc_reg_write
(
PFC_GPSR5
,
GPSR5_MSIOF0_SS2
|
GPSR5_MSIOF0_SS1
|
GPSR5_MSIOF0_SYNC
|
GPSR5_HRTS0
|
GPSR5_HCTS0
|
GPSR5_HTX0
|
GPSR5_HRX0
|
GPSR5_HSCK0
|
GPSR5_RX2_A
|
GPSR5_TX2_A
|
GPSR5_SCK2
|
GPSR5_RTS1_TANS
|
GPSR5_CTS1
|
GPSR5_TX1_A
|
GPSR5_RX1_A
|
GPSR5_RTS0_TANS
|
GPSR5_SCK0
);
pfc_reg_write
(
PFC_GPSR6
,
GPSR6_USB30_OVC
|
GPSR6_USB30_PWEN
|
GPSR6_USB1_OVC
|
GPSR6_USB1_PWEN
|
GPSR6_USB0_OVC
|
GPSR6_USB0_PWEN
|
GPSR6_AUDIO_CLKB_B
|
GPSR6_AUDIO_CLKA_A
|
GPSR6_SSI_SDATA8
|
GPSR6_SSI_SDATA7
|
GPSR6_SSI_WS78
|
GPSR6_SSI_SCK78
|
GPSR6_SSI_WS6
|
GPSR6_SSI_SCK6
|
GPSR6_SSI_SDATA4
|
GPSR6_SSI_WS4
|
GPSR6_SSI_SCK4
|
GPSR6_SSI_SDATA1_A
|
GPSR6_SSI_SDATA0
|
GPSR6_SSI_WS0129
|
GPSR6_SSI_SCK0129
);
pfc_reg_write
(
PFC_GPSR7
,
GPSR7_HDMI1_CEC
|
GPSR7_HDMI0_CEC
|
GPSR7_AVS2
|
GPSR7_AVS1
);
/* initialize POC control register */
pfc_reg_write
(
PFC_POCCTRL0
,
POC_SD3_DS_33V
|
POC_SD3_DAT7_33V
|
POC_SD3_DAT6_33V
|
POC_SD3_DAT5_33V
|
POC_SD3_DAT4_33V
|
POC_SD3_DAT3_33V
|
POC_SD3_DAT2_33V
|
POC_SD3_DAT1_33V
|
POC_SD3_DAT0_33V
|
POC_SD3_CMD_33V
|
POC_SD3_CLK_33V
|
POC_SD0_DAT3_33V
|
POC_SD0_DAT2_33V
|
POC_SD0_DAT1_33V
|
POC_SD0_DAT0_33V
|
POC_SD0_CMD_33V
|
POC_SD0_CLK_33V
);
/* initialize DRV control register */
reg
=
mmio_read_32
(
PFC_DRVCTRL0
);
reg
=
((
reg
&
DRVCTRL0_MASK
)
|
DRVCTRL0_QSPI0_SPCLK
(
3
)
|
DRVCTRL0_QSPI0_MOSI_IO0
(
3
)
|
DRVCTRL0_QSPI0_MISO_IO1
(
3
)
|
DRVCTRL0_QSPI0_IO2
(
3
)
|
DRVCTRL0_QSPI0_IO3
(
3
)
|
DRVCTRL0_QSPI0_SSL
(
3
)
|
DRVCTRL0_QSPI1_SPCLK
(
3
)
|
DRVCTRL0_QSPI1_MOSI_IO0
(
3
));
pfc_reg_write
(
PFC_DRVCTRL0
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL1
);
reg
=
((
reg
&
DRVCTRL1_MASK
)
|
DRVCTRL1_QSPI1_MISO_IO1
(
3
)
|
DRVCTRL1_QSPI1_IO2
(
3
)
|
DRVCTRL1_QSPI1_IO3
(
3
)
|
DRVCTRL1_QSPI1_SS
(
3
)
|
DRVCTRL1_RPC_INT
(
3
)
|
DRVCTRL1_RPC_WP
(
3
)
|
DRVCTRL1_RPC_RESET
(
3
)
|
DRVCTRL1_AVB_RX_CTL
(
7
));
pfc_reg_write
(
PFC_DRVCTRL1
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL2
);
reg
=
((
reg
&
DRVCTRL2_MASK
)
|
DRVCTRL2_AVB_RXC
(
7
)
|
DRVCTRL2_AVB_RD0
(
7
)
|
DRVCTRL2_AVB_RD1
(
7
)
|
DRVCTRL2_AVB_RD2
(
7
)
|
DRVCTRL2_AVB_RD3
(
7
)
|
DRVCTRL2_AVB_TX_CTL
(
3
)
|
DRVCTRL2_AVB_TXC
(
3
)
|
DRVCTRL2_AVB_TD0
(
3
));
pfc_reg_write
(
PFC_DRVCTRL2
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL3
);
reg
=
((
reg
&
DRVCTRL3_MASK
)
|
DRVCTRL3_AVB_TD1
(
3
)
|
DRVCTRL3_AVB_TD2
(
3
)
|
DRVCTRL3_AVB_TD3
(
3
)
|
DRVCTRL3_AVB_TXCREFCLK
(
7
)
|
DRVCTRL3_AVB_MDIO
(
7
)
|
DRVCTRL3_AVB_MDC
(
7
)
|
DRVCTRL3_AVB_MAGIC
(
7
)
|
DRVCTRL3_AVB_PHY_INT
(
7
));
pfc_reg_write
(
PFC_DRVCTRL3
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL4
);
reg
=
((
reg
&
DRVCTRL4_MASK
)
|
DRVCTRL4_AVB_LINK
(
7
)
|
DRVCTRL4_AVB_AVTP_MATCH
(
7
)
|
DRVCTRL4_AVB_AVTP_CAPTURE
(
7
)
|
DRVCTRL4_IRQ0
(
7
)
|
DRVCTRL4_IRQ1
(
7
)
|
DRVCTRL4_IRQ2
(
7
)
|
DRVCTRL4_IRQ3
(
7
)
|
DRVCTRL4_IRQ4
(
7
));
pfc_reg_write
(
PFC_DRVCTRL4
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL5
);
reg
=
((
reg
&
DRVCTRL5_MASK
)
|
DRVCTRL5_IRQ5
(
7
)
|
DRVCTRL5_PWM0
(
7
)
|
DRVCTRL5_PWM1
(
7
)
|
DRVCTRL5_PWM2
(
7
)
|
DRVCTRL5_A0
(
3
)
|
DRVCTRL5_A1
(
3
)
|
DRVCTRL5_A2
(
3
)
|
DRVCTRL5_A3
(
3
));
pfc_reg_write
(
PFC_DRVCTRL5
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL6
);
reg
=
((
reg
&
DRVCTRL6_MASK
)
|
DRVCTRL6_A4
(
3
)
|
DRVCTRL6_A5
(
3
)
|
DRVCTRL6_A6
(
3
)
|
DRVCTRL6_A7
(
3
)
|
DRVCTRL6_A8
(
7
)
|
DRVCTRL6_A9
(
7
)
|
DRVCTRL6_A10
(
7
)
|
DRVCTRL6_A11
(
7
));
pfc_reg_write
(
PFC_DRVCTRL6
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL7
);
reg
=
((
reg
&
DRVCTRL7_MASK
)
|
DRVCTRL7_A12
(
3
)
|
DRVCTRL7_A13
(
3
)
|
DRVCTRL7_A14
(
3
)
|
DRVCTRL7_A15
(
3
)
|
DRVCTRL7_A16
(
3
)
|
DRVCTRL7_A17
(
3
)
|
DRVCTRL7_A18
(
3
)
|
DRVCTRL7_A19
(
3
));
pfc_reg_write
(
PFC_DRVCTRL7
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL8
);
reg
=
((
reg
&
DRVCTRL8_MASK
)
|
DRVCTRL8_CLKOUT
(
7
)
|
DRVCTRL8_CS0
(
7
)
|
DRVCTRL8_CS1_A2
(
7
)
|
DRVCTRL8_BS
(
7
)
|
DRVCTRL8_RD
(
7
)
|
DRVCTRL8_RD_W
(
7
)
|
DRVCTRL8_WE0
(
7
)
|
DRVCTRL8_WE1
(
7
));
pfc_reg_write
(
PFC_DRVCTRL8
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL9
);
reg
=
((
reg
&
DRVCTRL9_MASK
)
|
DRVCTRL9_EX_WAIT0
(
7
)
|
DRVCTRL9_PRESETOU
(
7
)
|
DRVCTRL9_D0
(
7
)
|
DRVCTRL9_D1
(
7
)
|
DRVCTRL9_D2
(
7
)
|
DRVCTRL9_D3
(
7
)
|
DRVCTRL9_D4
(
7
)
|
DRVCTRL9_D5
(
7
));
pfc_reg_write
(
PFC_DRVCTRL9
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL10
);
reg
=
((
reg
&
DRVCTRL10_MASK
)
|
DRVCTRL10_D6
(
7
)
|
DRVCTRL10_D7
(
7
)
|
DRVCTRL10_D8
(
3
)
|
DRVCTRL10_D9
(
3
)
|
DRVCTRL10_D10
(
3
)
|
DRVCTRL10_D11
(
3
)
|
DRVCTRL10_D12
(
3
)
|
DRVCTRL10_D13
(
3
));
pfc_reg_write
(
PFC_DRVCTRL10
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL11
);
reg
=
((
reg
&
DRVCTRL11_MASK
)
|
DRVCTRL11_D14
(
3
)
|
DRVCTRL11_D15
(
3
)
|
DRVCTRL11_AVS1
(
7
)
|
DRVCTRL11_AVS2
(
7
)
|
DRVCTRL11_HDMI0_CEC
(
7
)
|
DRVCTRL11_HDMI1_CEC
(
7
)
|
DRVCTRL11_DU_DOTCLKIN0
(
3
)
|
DRVCTRL11_DU_DOTCLKIN1
(
3
));
pfc_reg_write
(
PFC_DRVCTRL11
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL12
);
reg
=
((
reg
&
DRVCTRL12_MASK
)
|
DRVCTRL12_DU_DOTCLKIN2
(
3
)
|
DRVCTRL12_DU_DOTCLKIN3
(
3
)
|
DRVCTRL12_DU_FSCLKST
(
3
)
|
DRVCTRL12_DU_TMS
(
3
));
pfc_reg_write
(
PFC_DRVCTRL12
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL13
);
reg
=
((
reg
&
DRVCTRL13_MASK
)
|
DRVCTRL13_TDO
(
3
)
|
DRVCTRL13_ASEBRK
(
3
)
|
DRVCTRL13_SD0_CLK
(
7
)
|
DRVCTRL13_SD0_CMD
(
7
)
|
DRVCTRL13_SD0_DAT0
(
7
)
|
DRVCTRL13_SD0_DAT1
(
7
)
|
DRVCTRL13_SD0_DAT2
(
7
)
|
DRVCTRL13_SD0_DAT3
(
7
));
pfc_reg_write
(
PFC_DRVCTRL13
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL14
);
reg
=
((
reg
&
DRVCTRL14_MASK
)
|
DRVCTRL14_SD1_CLK
(
7
)
|
DRVCTRL14_SD1_CMD
(
7
)
|
DRVCTRL14_SD1_DAT0
(
5
)
|
DRVCTRL14_SD1_DAT1
(
5
)
|
DRVCTRL14_SD1_DAT2
(
5
)
|
DRVCTRL14_SD1_DAT3
(
5
)
|
DRVCTRL14_SD2_CLK
(
5
)
|
DRVCTRL14_SD2_CMD
(
5
));
pfc_reg_write
(
PFC_DRVCTRL14
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL15
);
reg
=
((
reg
&
DRVCTRL15_MASK
)
|
DRVCTRL15_SD2_DAT0
(
5
)
|
DRVCTRL15_SD2_DAT1
(
5
)
|
DRVCTRL15_SD2_DAT2
(
5
)
|
DRVCTRL15_SD2_DAT3
(
5
)
|
DRVCTRL15_SD2_DS
(
5
)
|
DRVCTRL15_SD3_CLK
(
7
)
|
DRVCTRL15_SD3_CMD
(
7
)
|
DRVCTRL15_SD3_DAT0
(
7
));
pfc_reg_write
(
PFC_DRVCTRL15
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL16
);
reg
=
((
reg
&
DRVCTRL16_MASK
)
|
DRVCTRL16_SD3_DAT1
(
7
)
|
DRVCTRL16_SD3_DAT2
(
7
)
|
DRVCTRL16_SD3_DAT3
(
7
)
|
DRVCTRL16_SD3_DAT4
(
7
)
|
DRVCTRL16_SD3_DAT5
(
7
)
|
DRVCTRL16_SD3_DAT6
(
7
)
|
DRVCTRL16_SD3_DAT7
(
7
)
|
DRVCTRL16_SD3_DS
(
7
));
pfc_reg_write
(
PFC_DRVCTRL16
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL17
);
reg
=
((
reg
&
DRVCTRL17_MASK
)
|
DRVCTRL17_SD0_CD
(
7
)
|
DRVCTRL17_SD0_WP
(
7
)
|
DRVCTRL17_SD1_CD
(
7
)
|
DRVCTRL17_SD1_WP
(
7
)
|
DRVCTRL17_SCK0
(
7
)
|
DRVCTRL17_RX0
(
7
)
|
DRVCTRL17_TX0
(
7
)
|
DRVCTRL17_CTS0
(
7
));
pfc_reg_write
(
PFC_DRVCTRL17
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL18
);
reg
=
((
reg
&
DRVCTRL18_MASK
)
|
DRVCTRL18_RTS0_TANS
(
7
)
|
DRVCTRL18_RX1
(
7
)
|
DRVCTRL18_TX1
(
7
)
|
DRVCTRL18_CTS1
(
7
)
|
DRVCTRL18_RTS1_TANS
(
7
)
|
DRVCTRL18_SCK2
(
7
)
|
DRVCTRL18_TX2
(
7
)
|
DRVCTRL18_RX2
(
7
));
pfc_reg_write
(
PFC_DRVCTRL18
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL19
);
reg
=
((
reg
&
DRVCTRL19_MASK
)
|
DRVCTRL19_HSCK0
(
7
)
|
DRVCTRL19_HRX0
(
7
)
|
DRVCTRL19_HTX0
(
7
)
|
DRVCTRL19_HCTS0
(
7
)
|
DRVCTRL19_HRTS0
(
7
)
|
DRVCTRL19_MSIOF0_SCK
(
7
)
|
DRVCTRL19_MSIOF0_SYNC
(
7
)
|
DRVCTRL19_MSIOF0_SS1
(
7
));
pfc_reg_write
(
PFC_DRVCTRL19
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL20
);
reg
=
((
reg
&
DRVCTRL20_MASK
)
|
DRVCTRL20_MSIOF0_TXD
(
7
)
|
DRVCTRL20_MSIOF0_SS2
(
7
)
|
DRVCTRL20_MSIOF0_RXD
(
7
)
|
DRVCTRL20_MLB_CLK
(
7
)
|
DRVCTRL20_MLB_SIG
(
7
)
|
DRVCTRL20_MLB_DAT
(
7
)
|
DRVCTRL20_MLB_REF
(
7
)
|
DRVCTRL20_SSI_SCK0129
(
7
));
pfc_reg_write
(
PFC_DRVCTRL20
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL21
);
reg
=
((
reg
&
DRVCTRL21_MASK
)
|
DRVCTRL21_SSI_WS0129
(
7
)
|
DRVCTRL21_SSI_SDATA0
(
7
)
|
DRVCTRL21_SSI_SDATA1
(
7
)
|
DRVCTRL21_SSI_SDATA2
(
7
)
|
DRVCTRL21_SSI_SCK34
(
7
)
|
DRVCTRL21_SSI_WS34
(
7
)
|
DRVCTRL21_SSI_SDATA3
(
7
)
|
DRVCTRL21_SSI_SCK4
(
7
));
pfc_reg_write
(
PFC_DRVCTRL21
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL22
);
reg
=
((
reg
&
DRVCTRL22_MASK
)
|
DRVCTRL22_SSI_WS4
(
7
)
|
DRVCTRL22_SSI_SDATA4
(
7
)
|
DRVCTRL22_SSI_SCK5
(
7
)
|
DRVCTRL22_SSI_WS5
(
7
)
|
DRVCTRL22_SSI_SDATA5
(
7
)
|
DRVCTRL22_SSI_SCK6
(
7
)
|
DRVCTRL22_SSI_WS6
(
7
)
|
DRVCTRL22_SSI_SDATA6
(
7
));
pfc_reg_write
(
PFC_DRVCTRL22
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL23
);
reg
=
((
reg
&
DRVCTRL23_MASK
)
|
DRVCTRL23_SSI_SCK78
(
7
)
|
DRVCTRL23_SSI_WS78
(
7
)
|
DRVCTRL23_SSI_SDATA7
(
7
)
|
DRVCTRL23_SSI_SDATA8
(
7
)
|
DRVCTRL23_SSI_SDATA9
(
7
)
|
DRVCTRL23_AUDIO_CLKA
(
7
)
|
DRVCTRL23_AUDIO_CLKB
(
7
)
|
DRVCTRL23_USB0_PWEN
(
7
));
pfc_reg_write
(
PFC_DRVCTRL23
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL24
);
reg
=
((
reg
&
DRVCTRL24_MASK
)
|
DRVCTRL24_USB0_OVC
(
7
)
|
DRVCTRL24_USB1_PWEN
(
7
)
|
DRVCTRL24_USB1_OVC
(
7
)
|
DRVCTRL24_USB30_PWEN
(
7
)
|
DRVCTRL24_USB30_OVC
(
7
)
|
DRVCTRL24_USB31_PWEN
(
7
)
|
DRVCTRL24_USB31_OVC
(
7
));
pfc_reg_write
(
PFC_DRVCTRL24
,
reg
);
/* initialize LSI pin pull-up/down control */
pfc_reg_write
(
PFC_PUD0
,
0x00005FBFU
);
pfc_reg_write
(
PFC_PUD1
,
0x00300FFEU
);
pfc_reg_write
(
PFC_PUD2
,
0x330001E6U
);
pfc_reg_write
(
PFC_PUD3
,
0x000002E0U
);
pfc_reg_write
(
PFC_PUD4
,
0xFFFFFF00U
);
pfc_reg_write
(
PFC_PUD5
,
0x7F5FFF87U
);
pfc_reg_write
(
PFC_PUD6
,
0x00000055U
);
/* initialize LSI pin pull-enable register */
pfc_reg_write
(
PFC_PUEN0
,
0x00000FFFU
);
pfc_reg_write
(
PFC_PUEN1
,
0x00100234U
);
pfc_reg_write
(
PFC_PUEN2
,
0x000004C4U
);
pfc_reg_write
(
PFC_PUEN3
,
0x00000200U
);
pfc_reg_write
(
PFC_PUEN4
,
0x3E000000U
);
pfc_reg_write
(
PFC_PUEN5
,
0x1F000805U
);
pfc_reg_write
(
PFC_PUEN6
,
0x00000006U
);
/* initialize positive/negative logic select */
mmio_write_32
(
GPIO_POSNEG0
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG1
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG2
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG3
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG4
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG5
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG6
,
0x00000000U
);
/* initialize general IO/interrupt switching */
mmio_write_32
(
GPIO_IOINTSEL0
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL1
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL2
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL3
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL4
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL5
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL6
,
0x00000000U
);
/* initialize general output register */
mmio_write_32
(
GPIO_OUTDT1
,
0x00000000U
);
mmio_write_32
(
GPIO_OUTDT2
,
0x00000400U
);
mmio_write_32
(
GPIO_OUTDT3
,
0x0000C000U
);
mmio_write_32
(
GPIO_OUTDT5
,
0x00000006U
);
mmio_write_32
(
GPIO_OUTDT6
,
0x00003880U
);
/* initialize general input/output switching */
mmio_write_32
(
GPIO_INOUTSEL0
,
0x00000000U
);
mmio_write_32
(
GPIO_INOUTSEL1
,
0x01000A00U
);
mmio_write_32
(
GPIO_INOUTSEL2
,
0x00000400U
);
mmio_write_32
(
GPIO_INOUTSEL3
,
0x0000C000U
);
mmio_write_32
(
GPIO_INOUTSEL4
,
0x00000000U
);
mmio_write_32
(
GPIO_INOUTSEL5
,
0x0000020EU
);
mmio_write_32
(
GPIO_INOUTSEL6
,
0x00013880U
);
}
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PFC_INIT_H3_V2_H__
#define PFC_INIT_H3_V2_H__
void
pfc_init_h3_v2
(
void
);
#endif
/* PFC_INIT_H3_V2_H__ */
drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
/* for uint32_t */
#include <mmio.h>
#include "pfc_init_m3.h"
#include "rcar_def.h"
#include "rcar_private.h"
/* GPIO base address */
#define GPIO_BASE (0xE6050000U)
/* GPIO registers */
#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U)
#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U)
#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U)
#define GPIO_INDT0 (GPIO_BASE + 0x000CU)
#define GPIO_INTDT0 (GPIO_BASE + 0x0010U)
#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U)
#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U)
#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU)
#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U)
#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U)
#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U)
#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U)
#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU)
#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U)
#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U)
#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U)
#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU)
#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U)
#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U)
#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
#define GPIO_INTDT1 (GPIO_BASE + 0x1010U)
#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U)
#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U)
#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU)
#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U)
#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U)
#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U)
#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U)
#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU)
#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U)
#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U)
#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U)
#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU)
#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U)
#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U)
#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U)
#define GPIO_INDT2 (GPIO_BASE + 0x200CU)
#define GPIO_INTDT2 (GPIO_BASE + 0x2010U)
#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U)
#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U)
#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU)
#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U)
#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U)
#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U)
#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U)
#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU)
#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U)
#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U)
#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U)
#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU)
#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U)
#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U)
#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
#define GPIO_INTDT3 (GPIO_BASE + 0x3010U)
#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U)
#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U)
#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU)
#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U)
#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U)
#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U)
#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U)
#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU)
#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U)
#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U)
#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U)
#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU)
#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U)
#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U)
#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U)
#define GPIO_INDT4 (GPIO_BASE + 0x400CU)
#define GPIO_INTDT4 (GPIO_BASE + 0x4010U)
#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U)
#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U)
#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU)
#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U)
#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U)
#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U)
#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U)
#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU)
#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U)
#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U)
#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U)
#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU)
#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U)
#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U)
#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U)
#define GPIO_INDT5 (GPIO_BASE + 0x500CU)
#define GPIO_INTDT5 (GPIO_BASE + 0x5010U)
#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U)
#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U)
#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU)
#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U)
#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U)
#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U)
#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U)
#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU)
#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U)
#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U)
#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U)
#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU)
#define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U)
#define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U)
#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
#define GPIO_INTDT6 (GPIO_BASE + 0x5410U)
#define GPIO_INTCLR6 (GPIO_BASE + 0x5414U)
#define GPIO_INTMSK6 (GPIO_BASE + 0x5418U)
#define GPIO_MSKCLR6 (GPIO_BASE + 0x541CU)
#define GPIO_POSNEG6 (GPIO_BASE + 0x5420U)
#define GPIO_EDGLEVEL6 (GPIO_BASE + 0x5424U)
#define GPIO_FILONOFF6 (GPIO_BASE + 0x5428U)
#define GPIO_INTMSKS6 (GPIO_BASE + 0x5438U)
#define GPIO_MSKCLRS6 (GPIO_BASE + 0x543CU)
#define GPIO_OUTDTSEL6 (GPIO_BASE + 0x5440U)
#define GPIO_OUTDTH6 (GPIO_BASE + 0x5444U)
#define GPIO_OUTDTL6 (GPIO_BASE + 0x5448U)
#define GPIO_BOTHEDGE6 (GPIO_BASE + 0x544CU)
#define GPIO_IOINTSEL7 (GPIO_BASE + 0x5800U)
#define GPIO_INOUTSEL7 (GPIO_BASE + 0x5804U)
#define GPIO_OUTDT7 (GPIO_BASE + 0x5808U)
#define GPIO_INDT7 (GPIO_BASE + 0x580CU)
#define GPIO_INTDT7 (GPIO_BASE + 0x5810U)
#define GPIO_INTCLR7 (GPIO_BASE + 0x5814U)
#define GPIO_INTMSK7 (GPIO_BASE + 0x5818U)
#define GPIO_MSKCLR7 (GPIO_BASE + 0x581CU)
#define GPIO_POSNEG7 (GPIO_BASE + 0x5820U)
#define GPIO_EDGLEVEL7 (GPIO_BASE + 0x5824U)
#define GPIO_FILONOFF7 (GPIO_BASE + 0x5828U)
#define GPIO_INTMSKS7 (GPIO_BASE + 0x5838U)
#define GPIO_MSKCLRS7 (GPIO_BASE + 0x583CU)
#define GPIO_OUTDTSEL7 (GPIO_BASE + 0x5840U)
#define GPIO_OUTDTH7 (GPIO_BASE + 0x5844U)
#define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U)
#define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU)
/* Pin functon base address */
#define PFC_BASE (0xE6060000U)
/* Pin functon registers */
#define PFC_PMMR (PFC_BASE + 0x0000U)
#define PFC_GPSR0 (PFC_BASE + 0x0100U)
#define PFC_GPSR1 (PFC_BASE + 0x0104U)
#define PFC_GPSR2 (PFC_BASE + 0x0108U)
#define PFC_GPSR3 (PFC_BASE + 0x010CU)
#define PFC_GPSR4 (PFC_BASE + 0x0110U)
#define PFC_GPSR5 (PFC_BASE + 0x0114U)
#define PFC_GPSR6 (PFC_BASE + 0x0118U)
#define PFC_GPSR7 (PFC_BASE + 0x011CU)
#define PFC_IPSR0 (PFC_BASE + 0x0200U)
#define PFC_IPSR1 (PFC_BASE + 0x0204U)
#define PFC_IPSR2 (PFC_BASE + 0x0208U)
#define PFC_IPSR3 (PFC_BASE + 0x020CU)
#define PFC_IPSR4 (PFC_BASE + 0x0210U)
#define PFC_IPSR5 (PFC_BASE + 0x0214U)
#define PFC_IPSR6 (PFC_BASE + 0x0218U)
#define PFC_IPSR7 (PFC_BASE + 0x021CU)
#define PFC_IPSR8 (PFC_BASE + 0x0220U)
#define PFC_IPSR9 (PFC_BASE + 0x0224U)
#define PFC_IPSR10 (PFC_BASE + 0x0228U)
#define PFC_IPSR11 (PFC_BASE + 0x022CU)
#define PFC_IPSR12 (PFC_BASE + 0x0230U)
#define PFC_IPSR13 (PFC_BASE + 0x0234U)
#define PFC_IPSR14 (PFC_BASE + 0x0238U)
#define PFC_IPSR15 (PFC_BASE + 0x023CU)
#define PFC_IPSR16 (PFC_BASE + 0x0240U)
#define PFC_IPSR17 (PFC_BASE + 0x0244U)
#define PFC_IPSR18 (PFC_BASE + 0x0248U)
#define PFC_DRVCTRL0 (PFC_BASE + 0x0300U)
#define PFC_DRVCTRL1 (PFC_BASE + 0x0304U)
#define PFC_DRVCTRL2 (PFC_BASE + 0x0308U)
#define PFC_DRVCTRL3 (PFC_BASE + 0x030CU)
#define PFC_DRVCTRL4 (PFC_BASE + 0x0310U)
#define PFC_DRVCTRL5 (PFC_BASE + 0x0314U)
#define PFC_DRVCTRL6 (PFC_BASE + 0x0318U)
#define PFC_DRVCTRL7 (PFC_BASE + 0x031CU)
#define PFC_DRVCTRL8 (PFC_BASE + 0x0320U)
#define PFC_DRVCTRL9 (PFC_BASE + 0x0324U)
#define PFC_DRVCTRL10 (PFC_BASE + 0x0328U)
#define PFC_DRVCTRL11 (PFC_BASE + 0x032CU)
#define PFC_DRVCTRL12 (PFC_BASE + 0x0330U)
#define PFC_DRVCTRL13 (PFC_BASE + 0x0334U)
#define PFC_DRVCTRL14 (PFC_BASE + 0x0338U)
#define PFC_DRVCTRL15 (PFC_BASE + 0x033CU)
#define PFC_DRVCTRL16 (PFC_BASE + 0x0340U)
#define PFC_DRVCTRL17 (PFC_BASE + 0x0344U)
#define PFC_DRVCTRL18 (PFC_BASE + 0x0348U)
#define PFC_DRVCTRL19 (PFC_BASE + 0x034CU)
#define PFC_DRVCTRL20 (PFC_BASE + 0x0350U)
#define PFC_DRVCTRL21 (PFC_BASE + 0x0354U)
#define PFC_DRVCTRL22 (PFC_BASE + 0x0358U)
#define PFC_DRVCTRL23 (PFC_BASE + 0x035CU)
#define PFC_DRVCTRL24 (PFC_BASE + 0x0360U)
#define PFC_POCCTRL0 (PFC_BASE + 0x0380U)
#define PFC_TDSELCTRL0 (PFC_BASE + 0x03C0U)
#define PFC_IOCTRL (PFC_BASE + 0x03E0U)
#define PFC_TSREG (PFC_BASE + 0x03E4U)
#define PFC_PUEN0 (PFC_BASE + 0x0400U)
#define PFC_PUEN1 (PFC_BASE + 0x0404U)
#define PFC_PUEN2 (PFC_BASE + 0x0408U)
#define PFC_PUEN3 (PFC_BASE + 0x040CU)
#define PFC_PUEN4 (PFC_BASE + 0x0410U)
#define PFC_PUEN5 (PFC_BASE + 0x0414U)
#define PFC_PUEN6 (PFC_BASE + 0x0418U)
#define PFC_PUD0 (PFC_BASE + 0x0440U)
#define PFC_PUD1 (PFC_BASE + 0x0444U)
#define PFC_PUD2 (PFC_BASE + 0x0448U)
#define PFC_PUD3 (PFC_BASE + 0x044CU)
#define PFC_PUD4 (PFC_BASE + 0x0450U)
#define PFC_PUD5 (PFC_BASE + 0x0454U)
#define PFC_PUD6 (PFC_BASE + 0x0458U)
#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U)
#define PFC_MOD_SEL1 (PFC_BASE + 0x0504U)
#define PFC_MOD_SEL2 (PFC_BASE + 0x0508U)
#define GPSR0_D15 ((uint32_t)1U << 15U)
#define GPSR0_D14 ((uint32_t)1U << 14U)
#define GPSR0_D13 ((uint32_t)1U << 13U)
#define GPSR0_D12 ((uint32_t)1U << 12U)
#define GPSR0_D11 ((uint32_t)1U << 11U)
#define GPSR0_D10 ((uint32_t)1U << 10U)
#define GPSR0_D9 ((uint32_t)1U << 9U)
#define GPSR0_D8 ((uint32_t)1U << 8U)
#define GPSR0_D7 ((uint32_t)1U << 7U)
#define GPSR0_D6 ((uint32_t)1U << 6U)
#define GPSR0_D5 ((uint32_t)1U << 5U)
#define GPSR0_D4 ((uint32_t)1U << 4U)
#define GPSR0_D3 ((uint32_t)1U << 3U)
#define GPSR0_D2 ((uint32_t)1U << 2U)
#define GPSR0_D1 ((uint32_t)1U << 1U)
#define GPSR0_D0 ((uint32_t)1U << 0U)
#define GPSR1_CLKOUT ((uint32_t)1U << 28U)
#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U)
#define GPSR1_WE1 ((uint32_t)1U << 26U)
#define GPSR1_WE0 ((uint32_t)1U << 25U)
#define GPSR1_RD_WR ((uint32_t)1U << 24U)
#define GPSR1_RD ((uint32_t)1U << 23U)
#define GPSR1_BS ((uint32_t)1U << 22U)
#define GPSR1_CS1_A26 ((uint32_t)1U << 21U)
#define GPSR1_CS0 ((uint32_t)1U << 20U)
#define GPSR1_A19 ((uint32_t)1U << 19U)
#define GPSR1_A18 ((uint32_t)1U << 18U)
#define GPSR1_A17 ((uint32_t)1U << 17U)
#define GPSR1_A16 ((uint32_t)1U << 16U)
#define GPSR1_A15 ((uint32_t)1U << 15U)
#define GPSR1_A14 ((uint32_t)1U << 14U)
#define GPSR1_A13 ((uint32_t)1U << 13U)
#define GPSR1_A12 ((uint32_t)1U << 12U)
#define GPSR1_A11 ((uint32_t)1U << 11U)
#define GPSR1_A10 ((uint32_t)1U << 10U)
#define GPSR1_A9 ((uint32_t)1U << 9U)
#define GPSR1_A8 ((uint32_t)1U << 8U)
#define GPSR1_A7 ((uint32_t)1U << 7U)
#define GPSR1_A6 ((uint32_t)1U << 6U)
#define GPSR1_A5 ((uint32_t)1U << 5U)
#define GPSR1_A4 ((uint32_t)1U << 4U)
#define GPSR1_A3 ((uint32_t)1U << 3U)
#define GPSR1_A2 ((uint32_t)1U << 2U)
#define GPSR1_A1 ((uint32_t)1U << 1U)
#define GPSR1_A0 ((uint32_t)1U << 0U)
#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U)
#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U)
#define GPSR2_AVB_LINK ((uint32_t)1U << 12U)
#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U)
#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U)
#define GPSR2_AVB_MDC ((uint32_t)1U << 9U)
#define GPSR2_PWM2_A ((uint32_t)1U << 8U)
#define GPSR2_PWM1_A ((uint32_t)1U << 7U)
#define GPSR2_PWM0 ((uint32_t)1U << 6U)
#define GPSR2_IRQ5 ((uint32_t)1U << 5U)
#define GPSR2_IRQ4 ((uint32_t)1U << 4U)
#define GPSR2_IRQ3 ((uint32_t)1U << 3U)
#define GPSR2_IRQ2 ((uint32_t)1U << 2U)
#define GPSR2_IRQ1 ((uint32_t)1U << 1U)
#define GPSR2_IRQ0 ((uint32_t)1U << 0U)
#define GPSR3_SD1_WP ((uint32_t)1U << 15U)
#define GPSR3_SD1_CD ((uint32_t)1U << 14U)
#define GPSR3_SD0_WP ((uint32_t)1U << 13U)
#define GPSR3_SD0_CD ((uint32_t)1U << 12U)
#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U)
#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U)
#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U)
#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U)
#define GPSR3_SD1_CMD ((uint32_t)1U << 7U)
#define GPSR3_SD1_CLK ((uint32_t)1U << 6U)
#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U)
#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U)
#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U)
#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U)
#define GPSR3_SD0_CMD ((uint32_t)1U << 1U)
#define GPSR3_SD0_CLK ((uint32_t)1U << 0U)
#define GPSR4_SD3_DS ((uint32_t)1U << 17U)
#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U)
#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U)
#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U)
#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U)
#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U)
#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U)
#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U)
#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U)
#define GPSR4_SD3_CMD ((uint32_t)1U << 8U)
#define GPSR4_SD3_CLK ((uint32_t)1U << 7U)
#define GPSR4_SD2_DS ((uint32_t)1U << 6U)
#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U)
#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U)
#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U)
#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U)
#define GPSR4_SD2_CMD ((uint32_t)1U << 1U)
#define GPSR4_SD2_CLK ((uint32_t)1U << 0U)
#define GPSR5_MLB_DAT ((uint32_t)1U << 25U)
#define GPSR5_MLB_SIG ((uint32_t)1U << 24U)
#define GPSR5_MLB_CLK ((uint32_t)1U << 23U)
#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U)
#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U)
#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U)
#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U)
#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U)
#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U)
#define GPSR5_HRTS0 ((uint32_t)1U << 16U)
#define GPSR5_HCTS0 ((uint32_t)1U << 15U)
#define GPSR5_HTX0 ((uint32_t)1U << 14U)
#define GPSR5_HRX0 ((uint32_t)1U << 13U)
#define GPSR5_HSCK0 ((uint32_t)1U << 12U)
#define GPSR5_RX2_A ((uint32_t)1U << 11U)
#define GPSR5_TX2_A ((uint32_t)1U << 10U)
#define GPSR5_SCK2 ((uint32_t)1U << 9U)
#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U)
#define GPSR5_CTS1 ((uint32_t)1U << 7U)
#define GPSR5_TX1_A ((uint32_t)1U << 6U)
#define GPSR5_RX1_A ((uint32_t)1U << 5U)
#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U)
#define GPSR5_CTS0 ((uint32_t)1U << 3U)
#define GPSR5_TX0 ((uint32_t)1U << 2U)
#define GPSR5_RX0 ((uint32_t)1U << 1U)
#define GPSR5_SCK0 ((uint32_t)1U << 0U)
#define GPSR6_USB31_OVC ((uint32_t)1U << 31U)
#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U)
#define GPSR6_USB30_OVC ((uint32_t)1U << 29U)
#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U)
#define GPSR6_USB1_OVC ((uint32_t)1U << 27U)
#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U)
#define GPSR6_USB0_OVC ((uint32_t)1U << 25U)
#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U)
#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U)
#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U)
#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U)
#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U)
#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U)
#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U)
#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U)
#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U)
#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U)
#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U)
#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U)
#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U)
#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U)
#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U)
#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U)
#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U)
#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U)
#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U)
#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U)
#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U)
#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U)
#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U)
#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U)
#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U)
#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U)
#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U)
#define GPSR7_AVS2 ((uint32_t)1U << 1U)
#define GPSR7_AVS1 ((uint32_t)1U << 0U)
#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
#define POC_SD3_DS_33V ((uint32_t)1U << 29U)
#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U)
#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U)
#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U)
#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U)
#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U)
#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U)
#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U)
#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U)
#define POC_SD3_CMD_33V ((uint32_t)1U << 20U)
#define POC_SD3_CLK_33V ((uint32_t)1U << 19U)
#define POC_SD2_DS_33V ((uint32_t)1U << 18U)
#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U)
#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U)
#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U)
#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U)
#define POC_SD2_CMD_33V ((uint32_t)1U << 13U)
#define POC_SD2_CLK_33V ((uint32_t)1U << 12U)
#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U)
#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U)
#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U)
#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U)
#define POC_SD1_CMD_33V ((uint32_t)1U << 7U)
#define POC_SD1_CLK_33V ((uint32_t)1U << 6U)
#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U)
#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U)
#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U)
#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U)
#define POC_SD0_CMD_33V ((uint32_t)1U << 1U)
#define POC_SD0_CLK_33V ((uint32_t)1U << 0U)
#define DRVCTRL0_MASK (0xCCCCCCCCU)
#define DRVCTRL1_MASK (0xCCCCCCC8U)
#define DRVCTRL2_MASK (0x88888888U)
#define DRVCTRL3_MASK (0x88888888U)
#define DRVCTRL4_MASK (0x88888888U)
#define DRVCTRL5_MASK (0x88888888U)
#define DRVCTRL6_MASK (0x88888888U)
#define DRVCTRL7_MASK (0x88888888U)
#define DRVCTRL8_MASK (0x88888888U)
#define DRVCTRL9_MASK (0x88888888U)
#define DRVCTRL10_MASK (0x88888888U)
#define DRVCTRL11_MASK (0x888888CCU)
#define DRVCTRL12_MASK (0xCCCFFFCFU)
#define DRVCTRL13_MASK (0xCC888888U)
#define DRVCTRL14_MASK (0x88888888U)
#define DRVCTRL15_MASK (0x88888888U)
#define DRVCTRL16_MASK (0x88888888U)
#define DRVCTRL17_MASK (0x88888888U)
#define DRVCTRL18_MASK (0x88888888U)
#define DRVCTRL19_MASK (0x88888888U)
#define DRVCTRL20_MASK (0x88888888U)
#define DRVCTRL21_MASK (0x88888888U)
#define DRVCTRL22_MASK (0x88888888U)
#define DRVCTRL23_MASK (0x88888888U)
#define DRVCTRL24_MASK (0x8888888FU)
#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
/* SCIF3 Registers for Dummy write */
#define SCIF3_BASE (0xE6C50000U)
#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U)
#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU)
#define SCFCR_DATA (0x0000U)
/* Realtime module stop control */
#define CPG_BASE (0xE6150000U)
#define CPG_SCMSTPCR0 (CPG_BASE + 0x0B20U)
#define CPG_MSTPSR0 (CPG_BASE + 0x0030U)
#define SCMSTPCR0_RTDMAC (0x00200000U)
/* RT-DMAC Registers */
#define RTDMAC_CH (0U)
/* choose 0 to 15 */
#define RTDMAC_BASE (0xFFC10000U)
#define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U)
#define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U)
#define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x)))
#define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x)))
#define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x)))
#define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x)))
#define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x)))
#define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x)))
#define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U)
#define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U)
#define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U)
#define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U)
#define RDMOR_DME (0x0001U)
/* DMA Master Enable */
#define RDMCHCR_DPM_INFINITE (0x30000000U)
/* Infinite repeat mode */
#define RDMCHCR_RPT_TCR (0x02000000U)
/* enable to update TCR */
#define RDMCHCR_TS_2 (0x00000008U)
/* Word(2byte) units transfer */
#define RDMCHCR_RS_AUTO (0x00000400U)
/* Auto request */
#define RDMCHCR_DE (0x00000001U)
/* DMA Enable */
#define RDMCHCRB_DRST (0x00008000U)
/* Descriptor reset */
#define RDMCHCRB_SLM_256 (0x00000080U)
/* once in 256 clock cycle */
#define RDMDPBASE_SEL_EXT (0x00000001U)
/* External memory use */
static
void
StartRtDma0_Descriptor
(
void
);
static
void
pfc_reg_write
(
uint32_t
addr
,
uint32_t
data
);
static
void
StartRtDma0_Descriptor
(
void
)
{
uint32_t
reg
;
reg
=
mmio_read_32
(
RCAR_PRR
);
reg
&=
(
RCAR_PRODUCT_MASK
|
RCAR_CUT_MASK
);
if
(
reg
==
(
RCAR_PRODUCT_M3_CUT10
))
{
/* Enable clock supply to RTDMAC. */
mstpcr_write
(
CPG_SCMSTPCR0
,
CPG_MSTPSR0
,
SCMSTPCR0_RTDMAC
);
/* Initialize ch0, Reset Descriptor */
mmio_write_32
(
RTDMAC_RDMCHCLR
,
((
uint32_t
)
1U
<<
RTDMAC_CH
));
mmio_write_32
(
RTDMAC_RDMCHCRB
(
RTDMAC_CH
),
RDMCHCRB_DRST
);
/* Enable DMA */
mmio_write_16
(
RTDMAC_RDMOR
,
RDMOR_DME
);
/* Set first transfer */
mmio_write_32
(
RTDMAC_RDMSAR
(
RTDMAC_CH
),
RCAR_PRR
);
mmio_write_32
(
RTDMAC_RDMDAR
(
RTDMAC_CH
),
SCIF3_SCFDR
);
mmio_write_32
(
RTDMAC_RDMTCR
(
RTDMAC_CH
),
0x00000001U
);
/* Set descriptor */
mmio_write_32
(
RTDMAC_DESC_RDMSAR
,
0x00000000U
);
mmio_write_32
(
RTDMAC_DESC_RDMDAR
,
0x00000000U
);
mmio_write_32
(
RTDMAC_DESC_RDMTCR
,
0x00200000U
);
mmio_write_32
(
RTDMAC_RDMCHCRB
(
RTDMAC_CH
),
RDMCHCRB_SLM_256
);
mmio_write_32
(
RTDMAC_RDMDPBASE
(
RTDMAC_CH
),
RTDMAC_DESC_BASE
|
RDMDPBASE_SEL_EXT
);
/* Set transfer parameter, Start transfer */
mmio_write_32
(
RTDMAC_RDMCHCR
(
RTDMAC_CH
),
RDMCHCR_DPM_INFINITE
|
RDMCHCR_RPT_TCR
|
RDMCHCR_TS_2
|
RDMCHCR_RS_AUTO
|
RDMCHCR_DE
);
}
}
static
void
pfc_reg_write
(
uint32_t
addr
,
uint32_t
data
)
{
uint32_t
prr
;
prr
=
mmio_read_32
(
RCAR_PRR
);
prr
&=
(
RCAR_PRODUCT_MASK
|
RCAR_CUT_MASK
);
mmio_write_32
(
PFC_PMMR
,
~
data
);
if
(
prr
==
(
RCAR_PRODUCT_M3_CUT10
))
{
mmio_write_16
(
SCIF3_SCFCR
,
SCFCR_DATA
);
/* Dummy write */
}
mmio_write_32
((
uintptr_t
)
addr
,
data
);
if
(
prr
==
(
RCAR_PRODUCT_M3_CUT10
))
{
mmio_write_16
(
SCIF3_SCFCR
,
SCFCR_DATA
);
/* Dummy write */
}
}
void
pfc_init_m3
(
void
)
{
uint32_t
reg
;
/* Work around for PFC eratta */
StartRtDma0_Descriptor
();
/* initialize module select */
pfc_reg_write
(
PFC_MOD_SEL0
,
MOD_SEL0_MSIOF3_A
|
MOD_SEL0_MSIOF2_A
|
MOD_SEL0_MSIOF1_A
|
MOD_SEL0_LBSC_A
|
MOD_SEL0_IEBUS_A
|
MOD_SEL0_I2C2_A
|
MOD_SEL0_I2C1_A
|
MOD_SEL0_HSCIF4_A
|
MOD_SEL0_HSCIF3_A
|
MOD_SEL0_HSCIF1_A
|
MOD_SEL0_FSO_A
|
MOD_SEL0_HSCIF2_A
|
MOD_SEL0_ETHERAVB_A
|
MOD_SEL0_DRIF3_A
|
MOD_SEL0_DRIF2_A
|
MOD_SEL0_DRIF1_A
|
MOD_SEL0_DRIF0_A
|
MOD_SEL0_CANFD0_A
|
MOD_SEL0_ADG_A_A
);
pfc_reg_write
(
PFC_MOD_SEL1
,
MOD_SEL1_TSIF1_A
|
MOD_SEL1_TSIF0_A
|
MOD_SEL1_TIMER_TMU_A
|
MOD_SEL1_SSP1_1_A
|
MOD_SEL1_SSP1_0_A
|
MOD_SEL1_SSI_A
|
MOD_SEL1_SPEED_PULSE_IF_A
|
MOD_SEL1_SIMCARD_A
|
MOD_SEL1_SDHI2_A
|
MOD_SEL1_SCIF4_A
|
MOD_SEL1_SCIF3_A
|
MOD_SEL1_SCIF2_A
|
MOD_SEL1_SCIF1_A
|
MOD_SEL1_SCIF_A
|
MOD_SEL1_REMOCON_A
|
MOD_SEL1_RCAN0_A
|
MOD_SEL1_PWM6_A
|
MOD_SEL1_PWM5_A
|
MOD_SEL1_PWM4_A
|
MOD_SEL1_PWM3_A
|
MOD_SEL1_PWM2_A
|
MOD_SEL1_PWM1_A
);
pfc_reg_write
(
PFC_MOD_SEL2
,
MOD_SEL2_I2C_5_A
|
MOD_SEL2_I2C_3_A
|
MOD_SEL2_I2C_0_A
|
MOD_SEL2_FM_A
|
MOD_SEL2_SCIF5_A
|
MOD_SEL2_I2C6_A
|
MOD_SEL2_NDF_A
|
MOD_SEL2_SSI2_A
|
MOD_SEL2_SSI9_A
|
MOD_SEL2_TIMER_TMU2_A
|
MOD_SEL2_ADG_B_A
|
MOD_SEL2_ADG_C_A
|
MOD_SEL2_VIN4_A
);
/* initialize peripheral function select */
pfc_reg_write
(
PFC_IPSR0
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR1
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
3
)
|
IPSR_8_FUNC
(
3
)
|
IPSR_4_FUNC
(
3
)
|
IPSR_0_FUNC
(
3
));
pfc_reg_write
(
PFC_IPSR2
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR3
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR4
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR5
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR6
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR7
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR8
,
IPSR_28_FUNC
(
1
)
|
IPSR_24_FUNC
(
1
)
|
IPSR_20_FUNC
(
1
)
|
IPSR_16_FUNC
(
1
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR9
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR10
,
IPSR_28_FUNC
(
1
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR11
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
4
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
1
));
pfc_reg_write
(
PFC_IPSR12
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
4
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR13
,
IPSR_28_FUNC
(
8
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
3
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR14
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
3
)
|
IPSR_0_FUNC
(
8
));
pfc_reg_write
(
PFC_IPSR15
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR16
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR17
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
1
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR18
,
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
/* initialize GPIO/perihperal function select */
pfc_reg_write
(
PFC_GPSR0
,
GPSR0_D15
|
GPSR0_D14
|
GPSR0_D13
|
GPSR0_D12
|
GPSR0_D11
|
GPSR0_D10
|
GPSR0_D9
|
GPSR0_D8
);
pfc_reg_write
(
PFC_GPSR1
,
GPSR1_CLKOUT
|
GPSR1_EX_WAIT0_A
|
GPSR1_A19
|
GPSR1_A18
|
GPSR1_A17
|
GPSR1_A16
|
GPSR1_A15
|
GPSR1_A14
|
GPSR1_A13
|
GPSR1_A12
|
GPSR1_A7
|
GPSR1_A6
|
GPSR1_A5
|
GPSR1_A4
|
GPSR1_A3
|
GPSR1_A2
|
GPSR1_A1
|
GPSR1_A0
);
pfc_reg_write
(
PFC_GPSR2
,
GPSR2_AVB_AVTP_CAPTURE_A
|
GPSR2_AVB_AVTP_MATCH_A
|
GPSR2_AVB_LINK
|
GPSR2_AVB_PHY_INT
|
GPSR2_AVB_MDC
|
GPSR2_PWM2_A
|
GPSR2_PWM1_A
|
GPSR2_IRQ5
|
GPSR2_IRQ4
|
GPSR2_IRQ3
|
GPSR2_IRQ2
|
GPSR2_IRQ1
|
GPSR2_IRQ0
);
pfc_reg_write
(
PFC_GPSR3
,
GPSR3_SD0_WP
|
GPSR3_SD0_CD
|
GPSR3_SD1_DAT3
|
GPSR3_SD1_DAT2
|
GPSR3_SD1_DAT1
|
GPSR3_SD1_DAT0
|
GPSR3_SD0_DAT3
|
GPSR3_SD0_DAT2
|
GPSR3_SD0_DAT1
|
GPSR3_SD0_DAT0
|
GPSR3_SD0_CMD
|
GPSR3_SD0_CLK
);
pfc_reg_write
(
PFC_GPSR4
,
GPSR4_SD3_DAT7
|
GPSR4_SD3_DAT6
|
GPSR4_SD3_DAT3
|
GPSR4_SD3_DAT2
|
GPSR4_SD3_DAT1
|
GPSR4_SD3_DAT0
|
GPSR4_SD3_CMD
|
GPSR4_SD3_CLK
|
GPSR4_SD2_DS
|
GPSR4_SD2_DAT3
|
GPSR4_SD2_DAT2
|
GPSR4_SD2_DAT1
|
GPSR4_SD2_DAT0
|
GPSR4_SD2_CMD
|
GPSR4_SD2_CLK
);
pfc_reg_write
(
PFC_GPSR5
,
GPSR5_MSIOF0_SS2
|
GPSR5_MSIOF0_SS1
|
GPSR5_MSIOF0_SYNC
|
GPSR5_HRTS0
|
GPSR5_HCTS0
|
GPSR5_HTX0
|
GPSR5_HRX0
|
GPSR5_HSCK0
|
GPSR5_RX2_A
|
GPSR5_TX2_A
|
GPSR5_SCK2
|
GPSR5_RTS1_TANS
|
GPSR5_CTS1
|
GPSR5_TX1_A
|
GPSR5_RX1_A
|
GPSR5_RTS0_TANS
|
GPSR5_SCK0
);
pfc_reg_write
(
PFC_GPSR6
,
GPSR6_USB30_OVC
|
GPSR6_USB30_PWEN
|
GPSR6_USB1_OVC
|
GPSR6_USB1_PWEN
|
GPSR6_USB0_OVC
|
GPSR6_USB0_PWEN
|
GPSR6_AUDIO_CLKB_B
|
GPSR6_AUDIO_CLKA_A
|
GPSR6_SSI_SDATA8
|
GPSR6_SSI_SDATA7
|
GPSR6_SSI_WS78
|
GPSR6_SSI_SCK78
|
GPSR6_SSI_WS6
|
GPSR6_SSI_SCK6
|
GPSR6_SSI_SDATA4
|
GPSR6_SSI_WS4
|
GPSR6_SSI_SCK4
|
GPSR6_SSI_SDATA1_A
|
GPSR6_SSI_SDATA0
|
GPSR6_SSI_WS0129
|
GPSR6_SSI_SCK0129
);
pfc_reg_write
(
PFC_GPSR7
,
GPSR7_HDMI1_CEC
|
GPSR7_HDMI0_CEC
|
GPSR7_AVS2
|
GPSR7_AVS1
);
/* initialize POC control register */
pfc_reg_write
(
PFC_POCCTRL0
,
POC_SD3_DS_33V
|
POC_SD3_DAT7_33V
|
POC_SD3_DAT6_33V
|
POC_SD3_DAT5_33V
|
POC_SD3_DAT4_33V
|
POC_SD3_DAT3_33V
|
POC_SD3_DAT2_33V
|
POC_SD3_DAT1_33V
|
POC_SD3_DAT0_33V
|
POC_SD3_CMD_33V
|
POC_SD3_CLK_33V
|
POC_SD0_DAT3_33V
|
POC_SD0_DAT2_33V
|
POC_SD0_DAT1_33V
|
POC_SD0_DAT0_33V
|
POC_SD0_CMD_33V
|
POC_SD0_CLK_33V
);
/* initialize DRV control register */
reg
=
mmio_read_32
(
PFC_DRVCTRL0
);
reg
=
((
reg
&
DRVCTRL0_MASK
)
|
DRVCTRL0_QSPI0_SPCLK
(
3
)
|
DRVCTRL0_QSPI0_MOSI_IO0
(
3
)
|
DRVCTRL0_QSPI0_MISO_IO1
(
3
)
|
DRVCTRL0_QSPI0_IO2
(
3
)
|
DRVCTRL0_QSPI0_IO3
(
3
)
|
DRVCTRL0_QSPI0_SSL
(
3
)
|
DRVCTRL0_QSPI1_SPCLK
(
3
)
|
DRVCTRL0_QSPI1_MOSI_IO0
(
3
));
pfc_reg_write
(
PFC_DRVCTRL0
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL1
);
reg
=
((
reg
&
DRVCTRL1_MASK
)
|
DRVCTRL1_QSPI1_MISO_IO1
(
3
)
|
DRVCTRL1_QSPI1_IO2
(
3
)
|
DRVCTRL1_QSPI1_IO3
(
3
)
|
DRVCTRL1_QSPI1_SS
(
3
)
|
DRVCTRL1_RPC_INT
(
3
)
|
DRVCTRL1_RPC_WP
(
3
)
|
DRVCTRL1_RPC_RESET
(
3
)
|
DRVCTRL1_AVB_RX_CTL
(
7
));
pfc_reg_write
(
PFC_DRVCTRL1
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL2
);
reg
=
((
reg
&
DRVCTRL2_MASK
)
|
DRVCTRL2_AVB_RXC
(
7
)
|
DRVCTRL2_AVB_RD0
(
7
)
|
DRVCTRL2_AVB_RD1
(
7
)
|
DRVCTRL2_AVB_RD2
(
7
)
|
DRVCTRL2_AVB_RD3
(
7
)
|
DRVCTRL2_AVB_TX_CTL
(
3
)
|
DRVCTRL2_AVB_TXC
(
3
)
|
DRVCTRL2_AVB_TD0
(
3
));
pfc_reg_write
(
PFC_DRVCTRL2
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL3
);
reg
=
((
reg
&
DRVCTRL3_MASK
)
|
DRVCTRL3_AVB_TD1
(
3
)
|
DRVCTRL3_AVB_TD2
(
3
)
|
DRVCTRL3_AVB_TD3
(
3
)
|
DRVCTRL3_AVB_TXCREFCLK
(
7
)
|
DRVCTRL3_AVB_MDIO
(
7
)
|
DRVCTRL3_AVB_MDC
(
7
)
|
DRVCTRL3_AVB_MAGIC
(
7
)
|
DRVCTRL3_AVB_PHY_INT
(
7
));
pfc_reg_write
(
PFC_DRVCTRL3
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL4
);
reg
=
((
reg
&
DRVCTRL4_MASK
)
|
DRVCTRL4_AVB_LINK
(
7
)
|
DRVCTRL4_AVB_AVTP_MATCH
(
7
)
|
DRVCTRL4_AVB_AVTP_CAPTURE
(
7
)
|
DRVCTRL4_IRQ0
(
7
)
|
DRVCTRL4_IRQ1
(
7
)
|
DRVCTRL4_IRQ2
(
7
)
|
DRVCTRL4_IRQ3
(
7
)
|
DRVCTRL4_IRQ4
(
7
));
pfc_reg_write
(
PFC_DRVCTRL4
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL5
);
reg
=
((
reg
&
DRVCTRL5_MASK
)
|
DRVCTRL5_IRQ5
(
7
)
|
DRVCTRL5_PWM0
(
7
)
|
DRVCTRL5_PWM1
(
7
)
|
DRVCTRL5_PWM2
(
7
)
|
DRVCTRL5_A0
(
3
)
|
DRVCTRL5_A1
(
3
)
|
DRVCTRL5_A2
(
3
)
|
DRVCTRL5_A3
(
3
));
pfc_reg_write
(
PFC_DRVCTRL5
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL6
);
reg
=
((
reg
&
DRVCTRL6_MASK
)
|
DRVCTRL6_A4
(
3
)
|
DRVCTRL6_A5
(
3
)
|
DRVCTRL6_A6
(
3
)
|
DRVCTRL6_A7
(
3
)
|
DRVCTRL6_A8
(
7
)
|
DRVCTRL6_A9
(
7
)
|
DRVCTRL6_A10
(
7
)
|
DRVCTRL6_A11
(
7
));
pfc_reg_write
(
PFC_DRVCTRL6
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL7
);
reg
=
((
reg
&
DRVCTRL7_MASK
)
|
DRVCTRL7_A12
(
3
)
|
DRVCTRL7_A13
(
3
)
|
DRVCTRL7_A14
(
3
)
|
DRVCTRL7_A15
(
3
)
|
DRVCTRL7_A16
(
3
)
|
DRVCTRL7_A17
(
3
)
|
DRVCTRL7_A18
(
3
)
|
DRVCTRL7_A19
(
3
));
pfc_reg_write
(
PFC_DRVCTRL7
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL8
);
reg
=
((
reg
&
DRVCTRL8_MASK
)
|
DRVCTRL8_CLKOUT
(
7
)
|
DRVCTRL8_CS0
(
7
)
|
DRVCTRL8_CS1_A2
(
7
)
|
DRVCTRL8_BS
(
7
)
|
DRVCTRL8_RD
(
7
)
|
DRVCTRL8_RD_W
(
7
)
|
DRVCTRL8_WE0
(
7
)
|
DRVCTRL8_WE1
(
7
));
pfc_reg_write
(
PFC_DRVCTRL8
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL9
);
reg
=
((
reg
&
DRVCTRL9_MASK
)
|
DRVCTRL9_EX_WAIT0
(
7
)
|
DRVCTRL9_PRESETOU
(
7
)
|
DRVCTRL9_D0
(
7
)
|
DRVCTRL9_D1
(
7
)
|
DRVCTRL9_D2
(
7
)
|
DRVCTRL9_D3
(
7
)
|
DRVCTRL9_D4
(
7
)
|
DRVCTRL9_D5
(
7
));
pfc_reg_write
(
PFC_DRVCTRL9
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL10
);
reg
=
((
reg
&
DRVCTRL10_MASK
)
|
DRVCTRL10_D6
(
7
)
|
DRVCTRL10_D7
(
7
)
|
DRVCTRL10_D8
(
3
)
|
DRVCTRL10_D9
(
3
)
|
DRVCTRL10_D10
(
3
)
|
DRVCTRL10_D11
(
3
)
|
DRVCTRL10_D12
(
3
)
|
DRVCTRL10_D13
(
3
));
pfc_reg_write
(
PFC_DRVCTRL10
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL11
);
reg
=
((
reg
&
DRVCTRL11_MASK
)
|
DRVCTRL11_D14
(
3
)
|
DRVCTRL11_D15
(
3
)
|
DRVCTRL11_AVS1
(
7
)
|
DRVCTRL11_AVS2
(
7
)
|
DRVCTRL11_HDMI0_CEC
(
7
)
|
DRVCTRL11_HDMI1_CEC
(
7
)
|
DRVCTRL11_DU_DOTCLKIN0
(
3
)
|
DRVCTRL11_DU_DOTCLKIN1
(
3
));
pfc_reg_write
(
PFC_DRVCTRL11
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL12
);
reg
=
((
reg
&
DRVCTRL12_MASK
)
|
DRVCTRL12_DU_DOTCLKIN2
(
3
)
|
DRVCTRL12_DU_DOTCLKIN3
(
3
)
|
DRVCTRL12_DU_FSCLKST
(
3
)
|
DRVCTRL12_DU_TMS
(
3
));
pfc_reg_write
(
PFC_DRVCTRL12
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL13
);
reg
=
((
reg
&
DRVCTRL13_MASK
)
|
DRVCTRL13_TDO
(
3
)
|
DRVCTRL13_ASEBRK
(
3
)
|
DRVCTRL13_SD0_CLK
(
7
)
|
DRVCTRL13_SD0_CMD
(
7
)
|
DRVCTRL13_SD0_DAT0
(
7
)
|
DRVCTRL13_SD0_DAT1
(
7
)
|
DRVCTRL13_SD0_DAT2
(
7
)
|
DRVCTRL13_SD0_DAT3
(
7
));
pfc_reg_write
(
PFC_DRVCTRL13
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL14
);
reg
=
((
reg
&
DRVCTRL14_MASK
)
|
DRVCTRL14_SD1_CLK
(
7
)
|
DRVCTRL14_SD1_CMD
(
7
)
|
DRVCTRL14_SD1_DAT0
(
5
)
|
DRVCTRL14_SD1_DAT1
(
5
)
|
DRVCTRL14_SD1_DAT2
(
5
)
|
DRVCTRL14_SD1_DAT3
(
5
)
|
DRVCTRL14_SD2_CLK
(
5
)
|
DRVCTRL14_SD2_CMD
(
5
));
pfc_reg_write
(
PFC_DRVCTRL14
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL15
);
reg
=
((
reg
&
DRVCTRL15_MASK
)
|
DRVCTRL15_SD2_DAT0
(
5
)
|
DRVCTRL15_SD2_DAT1
(
5
)
|
DRVCTRL15_SD2_DAT2
(
5
)
|
DRVCTRL15_SD2_DAT3
(
5
)
|
DRVCTRL15_SD2_DS
(
5
)
|
DRVCTRL15_SD3_CLK
(
7
)
|
DRVCTRL15_SD3_CMD
(
7
)
|
DRVCTRL15_SD3_DAT0
(
7
));
pfc_reg_write
(
PFC_DRVCTRL15
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL16
);
reg
=
((
reg
&
DRVCTRL16_MASK
)
|
DRVCTRL16_SD3_DAT1
(
7
)
|
DRVCTRL16_SD3_DAT2
(
7
)
|
DRVCTRL16_SD3_DAT3
(
7
)
|
DRVCTRL16_SD3_DAT4
(
7
)
|
DRVCTRL16_SD3_DAT5
(
7
)
|
DRVCTRL16_SD3_DAT6
(
7
)
|
DRVCTRL16_SD3_DAT7
(
7
)
|
DRVCTRL16_SD3_DS
(
7
));
pfc_reg_write
(
PFC_DRVCTRL16
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL17
);
reg
=
((
reg
&
DRVCTRL17_MASK
)
|
DRVCTRL17_SD0_CD
(
7
)
|
DRVCTRL17_SD0_WP
(
7
)
|
DRVCTRL17_SD1_CD
(
7
)
|
DRVCTRL17_SD1_WP
(
7
)
|
DRVCTRL17_SCK0
(
7
)
|
DRVCTRL17_RX0
(
7
)
|
DRVCTRL17_TX0
(
7
)
|
DRVCTRL17_CTS0
(
7
));
pfc_reg_write
(
PFC_DRVCTRL17
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL18
);
reg
=
((
reg
&
DRVCTRL18_MASK
)
|
DRVCTRL18_RTS0_TANS
(
7
)
|
DRVCTRL18_RX1
(
7
)
|
DRVCTRL18_TX1
(
7
)
|
DRVCTRL18_CTS1
(
7
)
|
DRVCTRL18_RTS1_TANS
(
7
)
|
DRVCTRL18_SCK2
(
7
)
|
DRVCTRL18_TX2
(
7
)
|
DRVCTRL18_RX2
(
7
));
pfc_reg_write
(
PFC_DRVCTRL18
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL19
);
reg
=
((
reg
&
DRVCTRL19_MASK
)
|
DRVCTRL19_HSCK0
(
7
)
|
DRVCTRL19_HRX0
(
7
)
|
DRVCTRL19_HTX0
(
7
)
|
DRVCTRL19_HCTS0
(
7
)
|
DRVCTRL19_HRTS0
(
7
)
|
DRVCTRL19_MSIOF0_SCK
(
7
)
|
DRVCTRL19_MSIOF0_SYNC
(
7
)
|
DRVCTRL19_MSIOF0_SS1
(
7
));
pfc_reg_write
(
PFC_DRVCTRL19
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL20
);
reg
=
((
reg
&
DRVCTRL20_MASK
)
|
DRVCTRL20_MSIOF0_TXD
(
7
)
|
DRVCTRL20_MSIOF0_SS2
(
7
)
|
DRVCTRL20_MSIOF0_RXD
(
7
)
|
DRVCTRL20_MLB_CLK
(
7
)
|
DRVCTRL20_MLB_SIG
(
7
)
|
DRVCTRL20_MLB_DAT
(
7
)
|
DRVCTRL20_MLB_REF
(
7
)
|
DRVCTRL20_SSI_SCK0129
(
7
));
pfc_reg_write
(
PFC_DRVCTRL20
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL21
);
reg
=
((
reg
&
DRVCTRL21_MASK
)
|
DRVCTRL21_SSI_WS0129
(
7
)
|
DRVCTRL21_SSI_SDATA0
(
7
)
|
DRVCTRL21_SSI_SDATA1
(
7
)
|
DRVCTRL21_SSI_SDATA2
(
7
)
|
DRVCTRL21_SSI_SCK34
(
7
)
|
DRVCTRL21_SSI_WS34
(
7
)
|
DRVCTRL21_SSI_SDATA3
(
7
)
|
DRVCTRL21_SSI_SCK4
(
7
));
pfc_reg_write
(
PFC_DRVCTRL21
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL22
);
reg
=
((
reg
&
DRVCTRL22_MASK
)
|
DRVCTRL22_SSI_WS4
(
7
)
|
DRVCTRL22_SSI_SDATA4
(
7
)
|
DRVCTRL22_SSI_SCK5
(
7
)
|
DRVCTRL22_SSI_WS5
(
7
)
|
DRVCTRL22_SSI_SDATA5
(
7
)
|
DRVCTRL22_SSI_SCK6
(
7
)
|
DRVCTRL22_SSI_WS6
(
7
)
|
DRVCTRL22_SSI_SDATA6
(
7
));
pfc_reg_write
(
PFC_DRVCTRL22
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL23
);
reg
=
((
reg
&
DRVCTRL23_MASK
)
|
DRVCTRL23_SSI_SCK78
(
7
)
|
DRVCTRL23_SSI_WS78
(
7
)
|
DRVCTRL23_SSI_SDATA7
(
7
)
|
DRVCTRL23_SSI_SDATA8
(
7
)
|
DRVCTRL23_SSI_SDATA9
(
7
)
|
DRVCTRL23_AUDIO_CLKA
(
7
)
|
DRVCTRL23_AUDIO_CLKB
(
7
)
|
DRVCTRL23_USB0_PWEN
(
7
));
pfc_reg_write
(
PFC_DRVCTRL23
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL24
);
reg
=
((
reg
&
DRVCTRL24_MASK
)
|
DRVCTRL24_USB0_OVC
(
7
)
|
DRVCTRL24_USB1_PWEN
(
7
)
|
DRVCTRL24_USB1_OVC
(
7
)
|
DRVCTRL24_USB30_PWEN
(
7
)
|
DRVCTRL24_USB30_OVC
(
7
)
|
DRVCTRL24_USB31_PWEN
(
7
)
|
DRVCTRL24_USB31_OVC
(
7
));
pfc_reg_write
(
PFC_DRVCTRL24
,
reg
);
/* initialize LSI pin pull-up/down control */
pfc_reg_write
(
PFC_PUD0
,
0x00005FBFU
);
pfc_reg_write
(
PFC_PUD1
,
0x00300FFEU
);
pfc_reg_write
(
PFC_PUD2
,
0x330001E6U
);
pfc_reg_write
(
PFC_PUD3
,
0x000002E0U
);
pfc_reg_write
(
PFC_PUD4
,
0xFFFFFF00U
);
pfc_reg_write
(
PFC_PUD5
,
0x7F5FFF87U
);
pfc_reg_write
(
PFC_PUD6
,
0x00000055U
);
/* initialize LSI pin pull-enable register */
pfc_reg_write
(
PFC_PUEN0
,
0x00000FFFU
);
pfc_reg_write
(
PFC_PUEN1
,
0x00100234U
);
pfc_reg_write
(
PFC_PUEN2
,
0x000004C4U
);
pfc_reg_write
(
PFC_PUEN3
,
0x00000200U
);
pfc_reg_write
(
PFC_PUEN4
,
0x3E000000U
);
pfc_reg_write
(
PFC_PUEN5
,
0x1F000805U
);
pfc_reg_write
(
PFC_PUEN6
,
0x00000006U
);
/* initialize positive/negative logic select */
mmio_write_32
(
GPIO_POSNEG0
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG1
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG2
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG3
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG4
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG5
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG6
,
0x00000000U
);
/* initialize general IO/interrupt switching */
mmio_write_32
(
GPIO_IOINTSEL0
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL1
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL2
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL3
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL4
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL5
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL6
,
0x00000000U
);
/* initialize general output register */
mmio_write_32
(
GPIO_OUTDT1
,
0x00000000U
);
mmio_write_32
(
GPIO_OUTDT2
,
0x00000400U
);
mmio_write_32
(
GPIO_OUTDT3
,
0x0000C000U
);
mmio_write_32
(
GPIO_OUTDT5
,
0x00000006U
);
mmio_write_32
(
GPIO_OUTDT6
,
0x00003880U
);
/* initialize general input/output switching */
mmio_write_32
(
GPIO_INOUTSEL0
,
0x00000000U
);
mmio_write_32
(
GPIO_INOUTSEL1
,
0x01000A00U
);
mmio_write_32
(
GPIO_INOUTSEL2
,
0x00000400U
);
mmio_write_32
(
GPIO_INOUTSEL3
,
0x0000C000U
);
mmio_write_32
(
GPIO_INOUTSEL4
,
0x00000000U
);
mmio_write_32
(
GPIO_INOUTSEL5
,
0x0000020EU
);
mmio_write_32
(
GPIO_INOUTSEL6
,
0x00013880U
);
}
drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PFC_INIT_M3_H__
#define PFC_INIT_M3_H__
void
pfc_init_m3
(
void
);
#endif
/* PFC_INIT_M3_H__ */
drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
/* for uint32_t */
#include <mmio.h>
#include "pfc_init_m3n.h"
#include "rcar_def.h"
/* GPIO base address */
#define GPIO_BASE (0xE6050000U)
/* GPIO registers */
#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U)
#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U)
#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U)
#define GPIO_INDT0 (GPIO_BASE + 0x000CU)
#define GPIO_INTDT0 (GPIO_BASE + 0x0010U)
#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U)
#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U)
#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU)
#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U)
#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U)
#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U)
#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U)
#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU)
#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U)
#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U)
#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U)
#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU)
#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U)
#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U)
#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
#define GPIO_INTDT1 (GPIO_BASE + 0x1010U)
#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U)
#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U)
#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU)
#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U)
#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U)
#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U)
#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U)
#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU)
#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U)
#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U)
#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U)
#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU)
#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U)
#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U)
#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U)
#define GPIO_INDT2 (GPIO_BASE + 0x200CU)
#define GPIO_INTDT2 (GPIO_BASE + 0x2010U)
#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U)
#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U)
#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU)
#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U)
#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U)
#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U)
#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U)
#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU)
#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U)
#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U)
#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U)
#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU)
#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U)
#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U)
#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
#define GPIO_INTDT3 (GPIO_BASE + 0x3010U)
#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U)
#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U)
#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU)
#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U)
#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U)
#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U)
#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U)
#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU)
#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U)
#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U)
#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U)
#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU)
#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U)
#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U)
#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U)
#define GPIO_INDT4 (GPIO_BASE + 0x400CU)
#define GPIO_INTDT4 (GPIO_BASE + 0x4010U)
#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U)
#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U)
#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU)
#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U)
#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U)
#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U)
#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U)
#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU)
#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U)
#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U)
#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U)
#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU)
#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U)
#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U)
#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U)
#define GPIO_INDT5 (GPIO_BASE + 0x500CU)
#define GPIO_INTDT5 (GPIO_BASE + 0x5010U)
#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U)
#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U)
#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU)
#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U)
#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U)
#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U)
#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U)
#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU)
#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U)
#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U)
#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U)
#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU)
#define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U)
#define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U)
#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
#define GPIO_INTDT6 (GPIO_BASE + 0x5410U)
#define GPIO_INTCLR6 (GPIO_BASE + 0x5414U)
#define GPIO_INTMSK6 (GPIO_BASE + 0x5418U)
#define GPIO_MSKCLR6 (GPIO_BASE + 0x541CU)
#define GPIO_POSNEG6 (GPIO_BASE + 0x5420U)
#define GPIO_EDGLEVEL6 (GPIO_BASE + 0x5424U)
#define GPIO_FILONOFF6 (GPIO_BASE + 0x5428U)
#define GPIO_INTMSKS6 (GPIO_BASE + 0x5438U)
#define GPIO_MSKCLRS6 (GPIO_BASE + 0x543CU)
#define GPIO_OUTDTSEL6 (GPIO_BASE + 0x5440U)
#define GPIO_OUTDTH6 (GPIO_BASE + 0x5444U)
#define GPIO_OUTDTL6 (GPIO_BASE + 0x5448U)
#define GPIO_BOTHEDGE6 (GPIO_BASE + 0x544CU)
#define GPIO_IOINTSEL7 (GPIO_BASE + 0x5800U)
#define GPIO_INOUTSEL7 (GPIO_BASE + 0x5804U)
#define GPIO_OUTDT7 (GPIO_BASE + 0x5808U)
#define GPIO_INDT7 (GPIO_BASE + 0x580CU)
#define GPIO_INTDT7 (GPIO_BASE + 0x5810U)
#define GPIO_INTCLR7 (GPIO_BASE + 0x5814U)
#define GPIO_INTMSK7 (GPIO_BASE + 0x5818U)
#define GPIO_MSKCLR7 (GPIO_BASE + 0x581CU)
#define GPIO_POSNEG7 (GPIO_BASE + 0x5820U)
#define GPIO_EDGLEVEL7 (GPIO_BASE + 0x5824U)
#define GPIO_FILONOFF7 (GPIO_BASE + 0x5828U)
#define GPIO_INTMSKS7 (GPIO_BASE + 0x5838U)
#define GPIO_MSKCLRS7 (GPIO_BASE + 0x583CU)
#define GPIO_OUTDTSEL7 (GPIO_BASE + 0x5840U)
#define GPIO_OUTDTH7 (GPIO_BASE + 0x5844U)
#define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U)
#define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU)
/* Pin functon base address */
#define PFC_BASE (0xE6060000U)
/* Pin functon registers */
#define PFC_PMMR (PFC_BASE + 0x0000U)
#define PFC_GPSR0 (PFC_BASE + 0x0100U)
#define PFC_GPSR1 (PFC_BASE + 0x0104U)
#define PFC_GPSR2 (PFC_BASE + 0x0108U)
#define PFC_GPSR3 (PFC_BASE + 0x010CU)
#define PFC_GPSR4 (PFC_BASE + 0x0110U)
#define PFC_GPSR5 (PFC_BASE + 0x0114U)
#define PFC_GPSR6 (PFC_BASE + 0x0118U)
#define PFC_GPSR7 (PFC_BASE + 0x011CU)
#define PFC_IPSR0 (PFC_BASE + 0x0200U)
#define PFC_IPSR1 (PFC_BASE + 0x0204U)
#define PFC_IPSR2 (PFC_BASE + 0x0208U)
#define PFC_IPSR3 (PFC_BASE + 0x020CU)
#define PFC_IPSR4 (PFC_BASE + 0x0210U)
#define PFC_IPSR5 (PFC_BASE + 0x0214U)
#define PFC_IPSR6 (PFC_BASE + 0x0218U)
#define PFC_IPSR7 (PFC_BASE + 0x021CU)
#define PFC_IPSR8 (PFC_BASE + 0x0220U)
#define PFC_IPSR9 (PFC_BASE + 0x0224U)
#define PFC_IPSR10 (PFC_BASE + 0x0228U)
#define PFC_IPSR11 (PFC_BASE + 0x022CU)
#define PFC_IPSR12 (PFC_BASE + 0x0230U)
#define PFC_IPSR13 (PFC_BASE + 0x0234U)
#define PFC_IPSR14 (PFC_BASE + 0x0238U)
#define PFC_IPSR15 (PFC_BASE + 0x023CU)
#define PFC_IPSR16 (PFC_BASE + 0x0240U)
#define PFC_IPSR17 (PFC_BASE + 0x0244U)
#define PFC_IPSR18 (PFC_BASE + 0x0248U)
#define PFC_DRVCTRL0 (PFC_BASE + 0x0300U)
#define PFC_DRVCTRL1 (PFC_BASE + 0x0304U)
#define PFC_DRVCTRL2 (PFC_BASE + 0x0308U)
#define PFC_DRVCTRL3 (PFC_BASE + 0x030CU)
#define PFC_DRVCTRL4 (PFC_BASE + 0x0310U)
#define PFC_DRVCTRL5 (PFC_BASE + 0x0314U)
#define PFC_DRVCTRL6 (PFC_BASE + 0x0318U)
#define PFC_DRVCTRL7 (PFC_BASE + 0x031CU)
#define PFC_DRVCTRL8 (PFC_BASE + 0x0320U)
#define PFC_DRVCTRL9 (PFC_BASE + 0x0324U)
#define PFC_DRVCTRL10 (PFC_BASE + 0x0328U)
#define PFC_DRVCTRL11 (PFC_BASE + 0x032CU)
#define PFC_DRVCTRL12 (PFC_BASE + 0x0330U)
#define PFC_DRVCTRL13 (PFC_BASE + 0x0334U)
#define PFC_DRVCTRL14 (PFC_BASE + 0x0338U)
#define PFC_DRVCTRL15 (PFC_BASE + 0x033CU)
#define PFC_DRVCTRL16 (PFC_BASE + 0x0340U)
#define PFC_DRVCTRL17 (PFC_BASE + 0x0344U)
#define PFC_DRVCTRL18 (PFC_BASE + 0x0348U)
#define PFC_DRVCTRL19 (PFC_BASE + 0x034CU)
#define PFC_DRVCTRL20 (PFC_BASE + 0x0350U)
#define PFC_DRVCTRL21 (PFC_BASE + 0x0354U)
#define PFC_DRVCTRL22 (PFC_BASE + 0x0358U)
#define PFC_DRVCTRL23 (PFC_BASE + 0x035CU)
#define PFC_DRVCTRL24 (PFC_BASE + 0x0360U)
#define PFC_POCCTRL0 (PFC_BASE + 0x0380U)
#define PFC_TDSELCTRL0 (PFC_BASE + 0x03C0U)
#define PFC_IOCTRL (PFC_BASE + 0x03E0U)
#define PFC_TSREG (PFC_BASE + 0x03E4U)
#define PFC_PUEN0 (PFC_BASE + 0x0400U)
#define PFC_PUEN1 (PFC_BASE + 0x0404U)
#define PFC_PUEN2 (PFC_BASE + 0x0408U)
#define PFC_PUEN3 (PFC_BASE + 0x040CU)
#define PFC_PUEN4 (PFC_BASE + 0x0410U)
#define PFC_PUEN5 (PFC_BASE + 0x0414U)
#define PFC_PUEN6 (PFC_BASE + 0x0418U)
#define PFC_PUD0 (PFC_BASE + 0x0440U)
#define PFC_PUD1 (PFC_BASE + 0x0444U)
#define PFC_PUD2 (PFC_BASE + 0x0448U)
#define PFC_PUD3 (PFC_BASE + 0x044CU)
#define PFC_PUD4 (PFC_BASE + 0x0450U)
#define PFC_PUD5 (PFC_BASE + 0x0454U)
#define PFC_PUD6 (PFC_BASE + 0x0458U)
#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U)
#define PFC_MOD_SEL1 (PFC_BASE + 0x0504U)
#define PFC_MOD_SEL2 (PFC_BASE + 0x0508U)
#define GPSR0_D15 ((uint32_t)1U << 15U)
#define GPSR0_D14 ((uint32_t)1U << 14U)
#define GPSR0_D13 ((uint32_t)1U << 13U)
#define GPSR0_D12 ((uint32_t)1U << 12U)
#define GPSR0_D11 ((uint32_t)1U << 11U)
#define GPSR0_D10 ((uint32_t)1U << 10U)
#define GPSR0_D9 ((uint32_t)1U << 9U)
#define GPSR0_D8 ((uint32_t)1U << 8U)
#define GPSR0_D7 ((uint32_t)1U << 7U)
#define GPSR0_D6 ((uint32_t)1U << 6U)
#define GPSR0_D5 ((uint32_t)1U << 5U)
#define GPSR0_D4 ((uint32_t)1U << 4U)
#define GPSR0_D3 ((uint32_t)1U << 3U)
#define GPSR0_D2 ((uint32_t)1U << 2U)
#define GPSR0_D1 ((uint32_t)1U << 1U)
#define GPSR0_D0 ((uint32_t)1U << 0U)
#define GPSR1_CLKOUT ((uint32_t)1U << 28U)
#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U)
#define GPSR1_WE1 ((uint32_t)1U << 26U)
#define GPSR1_WE0 ((uint32_t)1U << 25U)
#define GPSR1_RD_WR ((uint32_t)1U << 24U)
#define GPSR1_RD ((uint32_t)1U << 23U)
#define GPSR1_BS ((uint32_t)1U << 22U)
#define GPSR1_CS1_A26 ((uint32_t)1U << 21U)
#define GPSR1_CS0 ((uint32_t)1U << 20U)
#define GPSR1_A19 ((uint32_t)1U << 19U)
#define GPSR1_A18 ((uint32_t)1U << 18U)
#define GPSR1_A17 ((uint32_t)1U << 17U)
#define GPSR1_A16 ((uint32_t)1U << 16U)
#define GPSR1_A15 ((uint32_t)1U << 15U)
#define GPSR1_A14 ((uint32_t)1U << 14U)
#define GPSR1_A13 ((uint32_t)1U << 13U)
#define GPSR1_A12 ((uint32_t)1U << 12U)
#define GPSR1_A11 ((uint32_t)1U << 11U)
#define GPSR1_A10 ((uint32_t)1U << 10U)
#define GPSR1_A9 ((uint32_t)1U << 9U)
#define GPSR1_A8 ((uint32_t)1U << 8U)
#define GPSR1_A7 ((uint32_t)1U << 7U)
#define GPSR1_A6 ((uint32_t)1U << 6U)
#define GPSR1_A5 ((uint32_t)1U << 5U)
#define GPSR1_A4 ((uint32_t)1U << 4U)
#define GPSR1_A3 ((uint32_t)1U << 3U)
#define GPSR1_A2 ((uint32_t)1U << 2U)
#define GPSR1_A1 ((uint32_t)1U << 1U)
#define GPSR1_A0 ((uint32_t)1U << 0U)
#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U)
#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U)
#define GPSR2_AVB_LINK ((uint32_t)1U << 12U)
#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U)
#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U)
#define GPSR2_AVB_MDC ((uint32_t)1U << 9U)
#define GPSR2_PWM2_A ((uint32_t)1U << 8U)
#define GPSR2_PWM1_A ((uint32_t)1U << 7U)
#define GPSR2_PWM0 ((uint32_t)1U << 6U)
#define GPSR2_IRQ5 ((uint32_t)1U << 5U)
#define GPSR2_IRQ4 ((uint32_t)1U << 4U)
#define GPSR2_IRQ3 ((uint32_t)1U << 3U)
#define GPSR2_IRQ2 ((uint32_t)1U << 2U)
#define GPSR2_IRQ1 ((uint32_t)1U << 1U)
#define GPSR2_IRQ0 ((uint32_t)1U << 0U)
#define GPSR3_SD1_WP ((uint32_t)1U << 15U)
#define GPSR3_SD1_CD ((uint32_t)1U << 14U)
#define GPSR3_SD0_WP ((uint32_t)1U << 13U)
#define GPSR3_SD0_CD ((uint32_t)1U << 12U)
#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U)
#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U)
#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U)
#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U)
#define GPSR3_SD1_CMD ((uint32_t)1U << 7U)
#define GPSR3_SD1_CLK ((uint32_t)1U << 6U)
#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U)
#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U)
#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U)
#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U)
#define GPSR3_SD0_CMD ((uint32_t)1U << 1U)
#define GPSR3_SD0_CLK ((uint32_t)1U << 0U)
#define GPSR4_SD3_DS ((uint32_t)1U << 17U)
#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U)
#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U)
#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U)
#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U)
#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U)
#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U)
#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U)
#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U)
#define GPSR4_SD3_CMD ((uint32_t)1U << 8U)
#define GPSR4_SD3_CLK ((uint32_t)1U << 7U)
#define GPSR4_SD2_DS ((uint32_t)1U << 6U)
#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U)
#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U)
#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U)
#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U)
#define GPSR4_SD2_CMD ((uint32_t)1U << 1U)
#define GPSR4_SD2_CLK ((uint32_t)1U << 0U)
#define GPSR5_MLB_DAT ((uint32_t)1U << 25U)
#define GPSR5_MLB_SIG ((uint32_t)1U << 24U)
#define GPSR5_MLB_CLK ((uint32_t)1U << 23U)
#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U)
#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U)
#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U)
#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U)
#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U)
#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U)
#define GPSR5_HRTS0 ((uint32_t)1U << 16U)
#define GPSR5_HCTS0 ((uint32_t)1U << 15U)
#define GPSR5_HTX0 ((uint32_t)1U << 14U)
#define GPSR5_HRX0 ((uint32_t)1U << 13U)
#define GPSR5_HSCK0 ((uint32_t)1U << 12U)
#define GPSR5_RX2_A ((uint32_t)1U << 11U)
#define GPSR5_TX2_A ((uint32_t)1U << 10U)
#define GPSR5_SCK2 ((uint32_t)1U << 9U)
#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U)
#define GPSR5_CTS1 ((uint32_t)1U << 7U)
#define GPSR5_TX1_A ((uint32_t)1U << 6U)
#define GPSR5_RX1_A ((uint32_t)1U << 5U)
#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U)
#define GPSR5_CTS0 ((uint32_t)1U << 3U)
#define GPSR5_TX0 ((uint32_t)1U << 2U)
#define GPSR5_RX0 ((uint32_t)1U << 1U)
#define GPSR5_SCK0 ((uint32_t)1U << 0U)
#define GPSR6_USB31_OVC ((uint32_t)1U << 31U)
#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U)
#define GPSR6_USB30_OVC ((uint32_t)1U << 29U)
#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U)
#define GPSR6_USB1_OVC ((uint32_t)1U << 27U)
#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U)
#define GPSR6_USB0_OVC ((uint32_t)1U << 25U)
#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U)
#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U)
#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U)
#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U)
#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U)
#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U)
#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U)
#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U)
#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U)
#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U)
#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U)
#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U)
#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U)
#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U)
#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U)
#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U)
#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U)
#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U)
#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U)
#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U)
#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U)
#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U)
#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U)
#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U)
#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U)
#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U)
#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U)
#define GPSR7_AVS2 ((uint32_t)1U << 1U)
#define GPSR7_AVS1 ((uint32_t)1U << 0U)
#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
#define POC_SD3_DS_33V ((uint32_t)1U << 29U)
#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U)
#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U)
#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U)
#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U)
#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U)
#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U)
#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U)
#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U)
#define POC_SD3_CMD_33V ((uint32_t)1U << 20U)
#define POC_SD3_CLK_33V ((uint32_t)1U << 19U)
#define POC_SD2_DS_33V ((uint32_t)1U << 18U)
#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U)
#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U)
#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U)
#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U)
#define POC_SD2_CMD_33V ((uint32_t)1U << 13U)
#define POC_SD2_CLK_33V ((uint32_t)1U << 12U)
#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U)
#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U)
#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U)
#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U)
#define POC_SD1_CMD_33V ((uint32_t)1U << 7U)
#define POC_SD1_CLK_33V ((uint32_t)1U << 6U)
#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U)
#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U)
#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U)
#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U)
#define POC_SD0_CMD_33V ((uint32_t)1U << 1U)
#define POC_SD0_CLK_33V ((uint32_t)1U << 0U)
#define DRVCTRL0_MASK (0xCCCCCCCCU)
#define DRVCTRL1_MASK (0xCCCCCCC8U)
#define DRVCTRL2_MASK (0x88888888U)
#define DRVCTRL3_MASK (0x88888888U)
#define DRVCTRL4_MASK (0x88888888U)
#define DRVCTRL5_MASK (0x88888888U)
#define DRVCTRL6_MASK (0x88888888U)
#define DRVCTRL7_MASK (0x88888888U)
#define DRVCTRL8_MASK (0x88888888U)
#define DRVCTRL9_MASK (0x88888888U)
#define DRVCTRL10_MASK (0x88888888U)
#define DRVCTRL11_MASK (0x888888CCU)
#define DRVCTRL12_MASK (0xCCCFFFCFU)
#define DRVCTRL13_MASK (0xCC888888U)
#define DRVCTRL14_MASK (0x88888888U)
#define DRVCTRL15_MASK (0x88888888U)
#define DRVCTRL16_MASK (0x88888888U)
#define DRVCTRL17_MASK (0x88888888U)
#define DRVCTRL18_MASK (0x88888888U)
#define DRVCTRL19_MASK (0x88888888U)
#define DRVCTRL20_MASK (0x88888888U)
#define DRVCTRL21_MASK (0x88888888U)
#define DRVCTRL22_MASK (0x88888888U)
#define DRVCTRL23_MASK (0x88888888U)
#define DRVCTRL24_MASK (0x8888888FU)
#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
static
void
pfc_reg_write
(
uint32_t
addr
,
uint32_t
data
);
static
void
pfc_reg_write
(
uint32_t
addr
,
uint32_t
data
)
{
mmio_write_32
(
PFC_PMMR
,
~
data
);
mmio_write_32
((
uintptr_t
)
addr
,
data
);
}
void
pfc_init_m3n
(
void
)
{
uint32_t
reg
;
/* initialize module select */
pfc_reg_write
(
PFC_MOD_SEL0
,
MOD_SEL0_MSIOF3_A
|
MOD_SEL0_MSIOF2_A
|
MOD_SEL0_MSIOF1_A
|
MOD_SEL0_LBSC_A
|
MOD_SEL0_IEBUS_A
|
MOD_SEL0_I2C2_A
|
MOD_SEL0_I2C1_A
|
MOD_SEL0_HSCIF4_A
|
MOD_SEL0_HSCIF3_A
|
MOD_SEL0_HSCIF1_A
|
MOD_SEL0_FSO_A
|
MOD_SEL0_HSCIF2_A
|
MOD_SEL0_ETHERAVB_A
|
MOD_SEL0_DRIF3_A
|
MOD_SEL0_DRIF2_A
|
MOD_SEL0_DRIF1_A
|
MOD_SEL0_DRIF0_A
|
MOD_SEL0_CANFD0_A
|
MOD_SEL0_ADG_A_A
);
pfc_reg_write
(
PFC_MOD_SEL1
,
MOD_SEL1_TSIF1_A
|
MOD_SEL1_TSIF0_A
|
MOD_SEL1_TIMER_TMU_A
|
MOD_SEL1_SSP1_1_A
|
MOD_SEL1_SSP1_0_A
|
MOD_SEL1_SSI_A
|
MOD_SEL1_SPEED_PULSE_IF_A
|
MOD_SEL1_SIMCARD_A
|
MOD_SEL1_SDHI2_A
|
MOD_SEL1_SCIF4_A
|
MOD_SEL1_SCIF3_A
|
MOD_SEL1_SCIF2_A
|
MOD_SEL1_SCIF1_A
|
MOD_SEL1_SCIF_A
|
MOD_SEL1_REMOCON_A
|
MOD_SEL1_RCAN0_A
|
MOD_SEL1_PWM6_A
|
MOD_SEL1_PWM5_A
|
MOD_SEL1_PWM4_A
|
MOD_SEL1_PWM3_A
|
MOD_SEL1_PWM2_A
|
MOD_SEL1_PWM1_A
);
pfc_reg_write
(
PFC_MOD_SEL2
,
MOD_SEL2_I2C_5_A
|
MOD_SEL2_I2C_3_A
|
MOD_SEL2_I2C_0_A
|
MOD_SEL2_FM_A
|
MOD_SEL2_SCIF5_A
|
MOD_SEL2_I2C6_A
|
MOD_SEL2_NDF_A
|
MOD_SEL2_SSI2_A
|
MOD_SEL2_SSI9_A
|
MOD_SEL2_TIMER_TMU2_A
|
MOD_SEL2_ADG_B_A
|
MOD_SEL2_ADG_C_A
|
MOD_SEL2_VIN4_A
);
/* initialize peripheral function select */
pfc_reg_write
(
PFC_IPSR0
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR1
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
3
)
|
IPSR_8_FUNC
(
3
)
|
IPSR_4_FUNC
(
3
)
|
IPSR_0_FUNC
(
3
));
pfc_reg_write
(
PFC_IPSR2
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR3
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR4
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR5
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR6
,
IPSR_28_FUNC
(
6
)
|
IPSR_24_FUNC
(
6
)
|
IPSR_20_FUNC
(
6
)
|
IPSR_16_FUNC
(
6
)
|
IPSR_12_FUNC
(
6
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR7
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
6
)
|
IPSR_4_FUNC
(
6
)
|
IPSR_0_FUNC
(
6
));
pfc_reg_write
(
PFC_IPSR8
,
IPSR_28_FUNC
(
1
)
|
IPSR_24_FUNC
(
1
)
|
IPSR_20_FUNC
(
1
)
|
IPSR_16_FUNC
(
1
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR9
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR10
,
IPSR_28_FUNC
(
1
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR11
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
4
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
1
));
pfc_reg_write
(
PFC_IPSR12
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
4
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR13
,
IPSR_28_FUNC
(
8
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
3
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR14
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
3
)
|
IPSR_0_FUNC
(
8
));
pfc_reg_write
(
PFC_IPSR15
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR16
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR17
,
IPSR_28_FUNC
(
0
)
|
IPSR_24_FUNC
(
0
)
|
IPSR_20_FUNC
(
0
)
|
IPSR_16_FUNC
(
0
)
|
IPSR_12_FUNC
(
0
)
|
IPSR_8_FUNC
(
0
)
|
IPSR_4_FUNC
(
1
)
|
IPSR_0_FUNC
(
0
));
pfc_reg_write
(
PFC_IPSR18
,
IPSR_4_FUNC
(
0
)
|
IPSR_0_FUNC
(
0
));
/* initialize GPIO/perihperal function select */
pfc_reg_write
(
PFC_GPSR0
,
GPSR0_D15
|
GPSR0_D14
|
GPSR0_D13
|
GPSR0_D12
|
GPSR0_D11
|
GPSR0_D10
|
GPSR0_D9
|
GPSR0_D8
);
pfc_reg_write
(
PFC_GPSR1
,
GPSR1_CLKOUT
|
GPSR1_EX_WAIT0_A
|
GPSR1_A19
|
GPSR1_A18
|
GPSR1_A17
|
GPSR1_A16
|
GPSR1_A15
|
GPSR1_A14
|
GPSR1_A13
|
GPSR1_A12
|
GPSR1_A7
|
GPSR1_A6
|
GPSR1_A5
|
GPSR1_A4
|
GPSR1_A3
|
GPSR1_A2
|
GPSR1_A1
|
GPSR1_A0
);
pfc_reg_write
(
PFC_GPSR2
,
GPSR2_AVB_AVTP_CAPTURE_A
|
GPSR2_AVB_AVTP_MATCH_A
|
GPSR2_AVB_LINK
|
GPSR2_AVB_PHY_INT
|
GPSR2_AVB_MDC
|
GPSR2_PWM2_A
|
GPSR2_PWM1_A
|
GPSR2_IRQ5
|
GPSR2_IRQ4
|
GPSR2_IRQ3
|
GPSR2_IRQ2
|
GPSR2_IRQ1
|
GPSR2_IRQ0
);
pfc_reg_write
(
PFC_GPSR3
,
GPSR3_SD0_WP
|
GPSR3_SD0_CD
|
GPSR3_SD1_DAT3
|
GPSR3_SD1_DAT2
|
GPSR3_SD1_DAT1
|
GPSR3_SD1_DAT0
|
GPSR3_SD0_DAT3
|
GPSR3_SD0_DAT2
|
GPSR3_SD0_DAT1
|
GPSR3_SD0_DAT0
|
GPSR3_SD0_CMD
|
GPSR3_SD0_CLK
);
pfc_reg_write
(
PFC_GPSR4
,
GPSR4_SD3_DAT7
|
GPSR4_SD3_DAT6
|
GPSR4_SD3_DAT3
|
GPSR4_SD3_DAT2
|
GPSR4_SD3_DAT1
|
GPSR4_SD3_DAT0
|
GPSR4_SD3_CMD
|
GPSR4_SD3_CLK
|
GPSR4_SD2_DS
|
GPSR4_SD2_DAT3
|
GPSR4_SD2_DAT2
|
GPSR4_SD2_DAT1
|
GPSR4_SD2_DAT0
|
GPSR4_SD2_CMD
|
GPSR4_SD2_CLK
);
pfc_reg_write
(
PFC_GPSR5
,
GPSR5_MSIOF0_SS2
|
GPSR5_MSIOF0_SS1
|
GPSR5_MSIOF0_SYNC
|
GPSR5_HRTS0
|
GPSR5_HCTS0
|
GPSR5_HTX0
|
GPSR5_HRX0
|
GPSR5_HSCK0
|
GPSR5_RX2_A
|
GPSR5_TX2_A
|
GPSR5_SCK2
|
GPSR5_RTS1_TANS
|
GPSR5_CTS1
|
GPSR5_TX1_A
|
GPSR5_RX1_A
|
GPSR5_RTS0_TANS
|
GPSR5_SCK0
);
pfc_reg_write
(
PFC_GPSR6
,
GPSR6_USB30_OVC
|
GPSR6_USB30_PWEN
|
GPSR6_USB1_OVC
|
GPSR6_USB1_PWEN
|
GPSR6_USB0_OVC
|
GPSR6_USB0_PWEN
|
GPSR6_AUDIO_CLKB_B
|
GPSR6_AUDIO_CLKA_A
|
GPSR6_SSI_SDATA8
|
GPSR6_SSI_SDATA7
|
GPSR6_SSI_WS78
|
GPSR6_SSI_SCK78
|
GPSR6_SSI_WS6
|
GPSR6_SSI_SCK6
|
GPSR6_SSI_SDATA4
|
GPSR6_SSI_WS4
|
GPSR6_SSI_SCK4
|
GPSR6_SSI_SDATA1_A
|
GPSR6_SSI_SDATA0
|
GPSR6_SSI_WS0129
|
GPSR6_SSI_SCK0129
);
pfc_reg_write
(
PFC_GPSR7
,
GPSR7_HDMI1_CEC
|
GPSR7_HDMI0_CEC
|
GPSR7_AVS2
|
GPSR7_AVS1
);
/* initialize POC control register */
pfc_reg_write
(
PFC_POCCTRL0
,
POC_SD3_DS_33V
|
POC_SD3_DAT7_33V
|
POC_SD3_DAT6_33V
|
POC_SD3_DAT5_33V
|
POC_SD3_DAT4_33V
|
POC_SD3_DAT3_33V
|
POC_SD3_DAT2_33V
|
POC_SD3_DAT1_33V
|
POC_SD3_DAT0_33V
|
POC_SD3_CMD_33V
|
POC_SD3_CLK_33V
|
POC_SD0_DAT3_33V
|
POC_SD0_DAT2_33V
|
POC_SD0_DAT1_33V
|
POC_SD0_DAT0_33V
|
POC_SD0_CMD_33V
|
POC_SD0_CLK_33V
);
/* initialize DRV control register */
reg
=
mmio_read_32
(
PFC_DRVCTRL0
);
reg
=
((
reg
&
DRVCTRL0_MASK
)
|
DRVCTRL0_QSPI0_SPCLK
(
3
)
|
DRVCTRL0_QSPI0_MOSI_IO0
(
3
)
|
DRVCTRL0_QSPI0_MISO_IO1
(
3
)
|
DRVCTRL0_QSPI0_IO2
(
3
)
|
DRVCTRL0_QSPI0_IO3
(
3
)
|
DRVCTRL0_QSPI0_SSL
(
3
)
|
DRVCTRL0_QSPI1_SPCLK
(
3
)
|
DRVCTRL0_QSPI1_MOSI_IO0
(
3
));
pfc_reg_write
(
PFC_DRVCTRL0
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL1
);
reg
=
((
reg
&
DRVCTRL1_MASK
)
|
DRVCTRL1_QSPI1_MISO_IO1
(
3
)
|
DRVCTRL1_QSPI1_IO2
(
3
)
|
DRVCTRL1_QSPI1_IO3
(
3
)
|
DRVCTRL1_QSPI1_SS
(
3
)
|
DRVCTRL1_RPC_INT
(
3
)
|
DRVCTRL1_RPC_WP
(
3
)
|
DRVCTRL1_RPC_RESET
(
3
)
|
DRVCTRL1_AVB_RX_CTL
(
7
));
pfc_reg_write
(
PFC_DRVCTRL1
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL2
);
reg
=
((
reg
&
DRVCTRL2_MASK
)
|
DRVCTRL2_AVB_RXC
(
7
)
|
DRVCTRL2_AVB_RD0
(
7
)
|
DRVCTRL2_AVB_RD1
(
7
)
|
DRVCTRL2_AVB_RD2
(
7
)
|
DRVCTRL2_AVB_RD3
(
7
)
|
DRVCTRL2_AVB_TX_CTL
(
3
)
|
DRVCTRL2_AVB_TXC
(
3
)
|
DRVCTRL2_AVB_TD0
(
3
));
pfc_reg_write
(
PFC_DRVCTRL2
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL3
);
reg
=
((
reg
&
DRVCTRL3_MASK
)
|
DRVCTRL3_AVB_TD1
(
3
)
|
DRVCTRL3_AVB_TD2
(
3
)
|
DRVCTRL3_AVB_TD3
(
3
)
|
DRVCTRL3_AVB_TXCREFCLK
(
7
)
|
DRVCTRL3_AVB_MDIO
(
7
)
|
DRVCTRL3_AVB_MDC
(
7
)
|
DRVCTRL3_AVB_MAGIC
(
7
)
|
DRVCTRL3_AVB_PHY_INT
(
7
));
pfc_reg_write
(
PFC_DRVCTRL3
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL4
);
reg
=
((
reg
&
DRVCTRL4_MASK
)
|
DRVCTRL4_AVB_LINK
(
7
)
|
DRVCTRL4_AVB_AVTP_MATCH
(
7
)
|
DRVCTRL4_AVB_AVTP_CAPTURE
(
7
)
|
DRVCTRL4_IRQ0
(
7
)
|
DRVCTRL4_IRQ1
(
7
)
|
DRVCTRL4_IRQ2
(
7
)
|
DRVCTRL4_IRQ3
(
7
)
|
DRVCTRL4_IRQ4
(
7
));
pfc_reg_write
(
PFC_DRVCTRL4
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL5
);
reg
=
((
reg
&
DRVCTRL5_MASK
)
|
DRVCTRL5_IRQ5
(
7
)
|
DRVCTRL5_PWM0
(
7
)
|
DRVCTRL5_PWM1
(
7
)
|
DRVCTRL5_PWM2
(
7
)
|
DRVCTRL5_A0
(
3
)
|
DRVCTRL5_A1
(
3
)
|
DRVCTRL5_A2
(
3
)
|
DRVCTRL5_A3
(
3
));
pfc_reg_write
(
PFC_DRVCTRL5
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL6
);
reg
=
((
reg
&
DRVCTRL6_MASK
)
|
DRVCTRL6_A4
(
3
)
|
DRVCTRL6_A5
(
3
)
|
DRVCTRL6_A6
(
3
)
|
DRVCTRL6_A7
(
3
)
|
DRVCTRL6_A8
(
7
)
|
DRVCTRL6_A9
(
7
)
|
DRVCTRL6_A10
(
7
)
|
DRVCTRL6_A11
(
7
));
pfc_reg_write
(
PFC_DRVCTRL6
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL7
);
reg
=
((
reg
&
DRVCTRL7_MASK
)
|
DRVCTRL7_A12
(
3
)
|
DRVCTRL7_A13
(
3
)
|
DRVCTRL7_A14
(
3
)
|
DRVCTRL7_A15
(
3
)
|
DRVCTRL7_A16
(
3
)
|
DRVCTRL7_A17
(
3
)
|
DRVCTRL7_A18
(
3
)
|
DRVCTRL7_A19
(
3
));
pfc_reg_write
(
PFC_DRVCTRL7
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL8
);
reg
=
((
reg
&
DRVCTRL8_MASK
)
|
DRVCTRL8_CLKOUT
(
7
)
|
DRVCTRL8_CS0
(
7
)
|
DRVCTRL8_CS1_A2
(
7
)
|
DRVCTRL8_BS
(
7
)
|
DRVCTRL8_RD
(
7
)
|
DRVCTRL8_RD_W
(
7
)
|
DRVCTRL8_WE0
(
7
)
|
DRVCTRL8_WE1
(
7
));
pfc_reg_write
(
PFC_DRVCTRL8
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL9
);
reg
=
((
reg
&
DRVCTRL9_MASK
)
|
DRVCTRL9_EX_WAIT0
(
7
)
|
DRVCTRL9_PRESETOU
(
7
)
|
DRVCTRL9_D0
(
7
)
|
DRVCTRL9_D1
(
7
)
|
DRVCTRL9_D2
(
7
)
|
DRVCTRL9_D3
(
7
)
|
DRVCTRL9_D4
(
7
)
|
DRVCTRL9_D5
(
7
));
pfc_reg_write
(
PFC_DRVCTRL9
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL10
);
reg
=
((
reg
&
DRVCTRL10_MASK
)
|
DRVCTRL10_D6
(
7
)
|
DRVCTRL10_D7
(
7
)
|
DRVCTRL10_D8
(
3
)
|
DRVCTRL10_D9
(
3
)
|
DRVCTRL10_D10
(
3
)
|
DRVCTRL10_D11
(
3
)
|
DRVCTRL10_D12
(
3
)
|
DRVCTRL10_D13
(
3
));
pfc_reg_write
(
PFC_DRVCTRL10
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL11
);
reg
=
((
reg
&
DRVCTRL11_MASK
)
|
DRVCTRL11_D14
(
3
)
|
DRVCTRL11_D15
(
3
)
|
DRVCTRL11_AVS1
(
7
)
|
DRVCTRL11_AVS2
(
7
)
|
DRVCTRL11_HDMI0_CEC
(
7
)
|
DRVCTRL11_HDMI1_CEC
(
7
)
|
DRVCTRL11_DU_DOTCLKIN0
(
3
)
|
DRVCTRL11_DU_DOTCLKIN1
(
3
));
pfc_reg_write
(
PFC_DRVCTRL11
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL12
);
reg
=
((
reg
&
DRVCTRL12_MASK
)
|
DRVCTRL12_DU_DOTCLKIN2
(
3
)
|
DRVCTRL12_DU_DOTCLKIN3
(
3
)
|
DRVCTRL12_DU_FSCLKST
(
3
)
|
DRVCTRL12_DU_TMS
(
3
));
pfc_reg_write
(
PFC_DRVCTRL12
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL13
);
reg
=
((
reg
&
DRVCTRL13_MASK
)
|
DRVCTRL13_TDO
(
3
)
|
DRVCTRL13_ASEBRK
(
3
)
|
DRVCTRL13_SD0_CLK
(
7
)
|
DRVCTRL13_SD0_CMD
(
7
)
|
DRVCTRL13_SD0_DAT0
(
7
)
|
DRVCTRL13_SD0_DAT1
(
7
)
|
DRVCTRL13_SD0_DAT2
(
7
)
|
DRVCTRL13_SD0_DAT3
(
7
));
pfc_reg_write
(
PFC_DRVCTRL13
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL14
);
reg
=
((
reg
&
DRVCTRL14_MASK
)
|
DRVCTRL14_SD1_CLK
(
7
)
|
DRVCTRL14_SD1_CMD
(
7
)
|
DRVCTRL14_SD1_DAT0
(
5
)
|
DRVCTRL14_SD1_DAT1
(
5
)
|
DRVCTRL14_SD1_DAT2
(
5
)
|
DRVCTRL14_SD1_DAT3
(
5
)
|
DRVCTRL14_SD2_CLK
(
5
)
|
DRVCTRL14_SD2_CMD
(
5
));
pfc_reg_write
(
PFC_DRVCTRL14
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL15
);
reg
=
((
reg
&
DRVCTRL15_MASK
)
|
DRVCTRL15_SD2_DAT0
(
5
)
|
DRVCTRL15_SD2_DAT1
(
5
)
|
DRVCTRL15_SD2_DAT2
(
5
)
|
DRVCTRL15_SD2_DAT3
(
5
)
|
DRVCTRL15_SD2_DS
(
5
)
|
DRVCTRL15_SD3_CLK
(
7
)
|
DRVCTRL15_SD3_CMD
(
7
)
|
DRVCTRL15_SD3_DAT0
(
7
));
pfc_reg_write
(
PFC_DRVCTRL15
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL16
);
reg
=
((
reg
&
DRVCTRL16_MASK
)
|
DRVCTRL16_SD3_DAT1
(
7
)
|
DRVCTRL16_SD3_DAT2
(
7
)
|
DRVCTRL16_SD3_DAT3
(
7
)
|
DRVCTRL16_SD3_DAT4
(
7
)
|
DRVCTRL16_SD3_DAT5
(
7
)
|
DRVCTRL16_SD3_DAT6
(
7
)
|
DRVCTRL16_SD3_DAT7
(
7
)
|
DRVCTRL16_SD3_DS
(
7
));
pfc_reg_write
(
PFC_DRVCTRL16
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL17
);
reg
=
((
reg
&
DRVCTRL17_MASK
)
|
DRVCTRL17_SD0_CD
(
7
)
|
DRVCTRL17_SD0_WP
(
7
)
|
DRVCTRL17_SD1_CD
(
7
)
|
DRVCTRL17_SD1_WP
(
7
)
|
DRVCTRL17_SCK0
(
7
)
|
DRVCTRL17_RX0
(
7
)
|
DRVCTRL17_TX0
(
7
)
|
DRVCTRL17_CTS0
(
7
));
pfc_reg_write
(
PFC_DRVCTRL17
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL18
);
reg
=
((
reg
&
DRVCTRL18_MASK
)
|
DRVCTRL18_RTS0_TANS
(
7
)
|
DRVCTRL18_RX1
(
7
)
|
DRVCTRL18_TX1
(
7
)
|
DRVCTRL18_CTS1
(
7
)
|
DRVCTRL18_RTS1_TANS
(
7
)
|
DRVCTRL18_SCK2
(
7
)
|
DRVCTRL18_TX2
(
7
)
|
DRVCTRL18_RX2
(
7
));
pfc_reg_write
(
PFC_DRVCTRL18
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL19
);
reg
=
((
reg
&
DRVCTRL19_MASK
)
|
DRVCTRL19_HSCK0
(
7
)
|
DRVCTRL19_HRX0
(
7
)
|
DRVCTRL19_HTX0
(
7
)
|
DRVCTRL19_HCTS0
(
7
)
|
DRVCTRL19_HRTS0
(
7
)
|
DRVCTRL19_MSIOF0_SCK
(
7
)
|
DRVCTRL19_MSIOF0_SYNC
(
7
)
|
DRVCTRL19_MSIOF0_SS1
(
7
));
pfc_reg_write
(
PFC_DRVCTRL19
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL20
);
reg
=
((
reg
&
DRVCTRL20_MASK
)
|
DRVCTRL20_MSIOF0_TXD
(
7
)
|
DRVCTRL20_MSIOF0_SS2
(
7
)
|
DRVCTRL20_MSIOF0_RXD
(
7
)
|
DRVCTRL20_MLB_CLK
(
7
)
|
DRVCTRL20_MLB_SIG
(
7
)
|
DRVCTRL20_MLB_DAT
(
7
)
|
DRVCTRL20_MLB_REF
(
7
)
|
DRVCTRL20_SSI_SCK0129
(
7
));
pfc_reg_write
(
PFC_DRVCTRL20
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL21
);
reg
=
((
reg
&
DRVCTRL21_MASK
)
|
DRVCTRL21_SSI_WS0129
(
7
)
|
DRVCTRL21_SSI_SDATA0
(
7
)
|
DRVCTRL21_SSI_SDATA1
(
7
)
|
DRVCTRL21_SSI_SDATA2
(
7
)
|
DRVCTRL21_SSI_SCK34
(
7
)
|
DRVCTRL21_SSI_WS34
(
7
)
|
DRVCTRL21_SSI_SDATA3
(
7
)
|
DRVCTRL21_SSI_SCK4
(
7
));
pfc_reg_write
(
PFC_DRVCTRL21
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL22
);
reg
=
((
reg
&
DRVCTRL22_MASK
)
|
DRVCTRL22_SSI_WS4
(
7
)
|
DRVCTRL22_SSI_SDATA4
(
7
)
|
DRVCTRL22_SSI_SCK5
(
7
)
|
DRVCTRL22_SSI_WS5
(
7
)
|
DRVCTRL22_SSI_SDATA5
(
7
)
|
DRVCTRL22_SSI_SCK6
(
7
)
|
DRVCTRL22_SSI_WS6
(
7
)
|
DRVCTRL22_SSI_SDATA6
(
7
));
pfc_reg_write
(
PFC_DRVCTRL22
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL23
);
reg
=
((
reg
&
DRVCTRL23_MASK
)
|
DRVCTRL23_SSI_SCK78
(
7
)
|
DRVCTRL23_SSI_WS78
(
7
)
|
DRVCTRL23_SSI_SDATA7
(
7
)
|
DRVCTRL23_SSI_SDATA8
(
7
)
|
DRVCTRL23_SSI_SDATA9
(
7
)
|
DRVCTRL23_AUDIO_CLKA
(
7
)
|
DRVCTRL23_AUDIO_CLKB
(
7
)
|
DRVCTRL23_USB0_PWEN
(
7
));
pfc_reg_write
(
PFC_DRVCTRL23
,
reg
);
reg
=
mmio_read_32
(
PFC_DRVCTRL24
);
reg
=
((
reg
&
DRVCTRL24_MASK
)
|
DRVCTRL24_USB0_OVC
(
7
)
|
DRVCTRL24_USB1_PWEN
(
7
)
|
DRVCTRL24_USB1_OVC
(
7
)
|
DRVCTRL24_USB30_PWEN
(
7
)
|
DRVCTRL24_USB30_OVC
(
7
)
|
DRVCTRL24_USB31_PWEN
(
7
)
|
DRVCTRL24_USB31_OVC
(
7
));
pfc_reg_write
(
PFC_DRVCTRL24
,
reg
);
/* initialize LSI pin pull-up/down control */
pfc_reg_write
(
PFC_PUD0
,
0x00005FBFU
);
pfc_reg_write
(
PFC_PUD1
,
0x00300FFEU
);
pfc_reg_write
(
PFC_PUD2
,
0x330001E6U
);
pfc_reg_write
(
PFC_PUD3
,
0x000002E0U
);
pfc_reg_write
(
PFC_PUD4
,
0xFFFFFF00U
);
pfc_reg_write
(
PFC_PUD5
,
0x7F5FFF87U
);
pfc_reg_write
(
PFC_PUD6
,
0x00000055U
);
/* initialize LSI pin pull-enable register */
pfc_reg_write
(
PFC_PUEN0
,
0x00000FFFU
);
pfc_reg_write
(
PFC_PUEN1
,
0x00100234U
);
pfc_reg_write
(
PFC_PUEN2
,
0x000004C4U
);
pfc_reg_write
(
PFC_PUEN3
,
0x00000200U
);
pfc_reg_write
(
PFC_PUEN4
,
0x3E000000U
);
pfc_reg_write
(
PFC_PUEN5
,
0x1F000805U
);
pfc_reg_write
(
PFC_PUEN6
,
0x00000006U
);
/* initialize positive/negative logic select */
mmio_write_32
(
GPIO_POSNEG0
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG1
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG2
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG3
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG4
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG5
,
0x00000000U
);
mmio_write_32
(
GPIO_POSNEG6
,
0x00000000U
);
/* initialize general IO/interrupt switching */
mmio_write_32
(
GPIO_IOINTSEL0
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL1
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL2
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL3
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL4
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL5
,
0x00000000U
);
mmio_write_32
(
GPIO_IOINTSEL6
,
0x00000000U
);
/* initialize general output register */
mmio_write_32
(
GPIO_OUTDT1
,
0x00000000U
);
mmio_write_32
(
GPIO_OUTDT2
,
0x00000400U
);
mmio_write_32
(
GPIO_OUTDT3
,
0x0000C000U
);
mmio_write_32
(
GPIO_OUTDT5
,
0x00000006U
);
mmio_write_32
(
GPIO_OUTDT6
,
0x00003880U
);
/* initialize general input/output switching */
mmio_write_32
(
GPIO_INOUTSEL0
,
0x00000000U
);
mmio_write_32
(
GPIO_INOUTSEL1
,
0x01000A00U
);
mmio_write_32
(
GPIO_INOUTSEL2
,
0x00000400U
);
mmio_write_32
(
GPIO_INOUTSEL3
,
0x0000C000U
);
mmio_write_32
(
GPIO_INOUTSEL4
,
0x00000000U
);
mmio_write_32
(
GPIO_INOUTSEL5
,
0x0000020EU
);
mmio_write_32
(
GPIO_INOUTSEL6
,
0x00013880U
);
}
drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PFC_INIT_M3N_H__
#define PFC_INIT_M3N_H__
void
pfc_init_m3n
(
void
);
#endif
/* PFC_INIT_M3N_H__ */
drivers/staging/renesas/rcar/pfc/pfc.mk
0 → 100644
View file @
a51443fa
#
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq
(${RCAR_LSI},${RCAR_AUTO})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
else
ifdef
RCAR_LSI_CUT_COMPAT
ifeq
(${RCAR_LSI},${RCAR_H3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
endif
ifeq
(${RCAR_LSI},${RCAR_H3N})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
endif
ifeq
(${RCAR_LSI},${RCAR_M3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
endif
ifeq
(${RCAR_LSI},${RCAR_M3N})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
endif
ifeq
(${RCAR_LSI},${RCAR_E3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
endif
else
ifeq
(${RCAR_LSI},${RCAR_H3})
ifeq
(${LSI_CUT},10)
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
else
ifeq
(${LSI_CUT},11)
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
else
# LSI_CUT 20 or later
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
endif
endif
ifeq
(${RCAR_LSI},${RCAR_H3N})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
endif
ifeq
(${RCAR_LSI},${RCAR_M3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
endif
ifeq
(${RCAR_LSI},${RCAR_M3N})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
endif
ifeq
(${RCAR_LSI},${RCAR_E3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
endif
endif
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/pfc_init.c
drivers/staging/renesas/rcar/pfc/pfc_init.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <debug.h>
#include <mmio.h>
#include "rcar_def.h"
#if RCAR_LSI == RCAR_AUTO
#include "H3/pfc_init_h3_v1.h"
#include "H3/pfc_init_h3_v2.h"
#include "M3/pfc_init_m3.h"
#include "M3N/pfc_init_m3n.h"
#endif
#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
/* H3 */
#include "H3/pfc_init_h3_v1.h"
#include "H3/pfc_init_h3_v2.h"
#endif
#if RCAR_LSI == RCAR_M3
/* M3 */
#include "M3/pfc_init_m3.h"
#endif
#if RCAR_LSI == RCAR_M3N
/* M3N */
#include "M3N/pfc_init_m3n.h"
#endif
#if RCAR_LSI == RCAR_E3
/* E3 */
#include "E3/pfc_init_e3.h"
#endif
/* Product Register */
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_H3 (0x00004F00U)
/* R-Car H3 */
#define PRR_PRODUCT_M3 (0x00005200U)
/* R-Car M3 */
#define PRR_PRODUCT_M3N (0x00005500U)
/* R-Car M3N */
#define PRR_PRODUCT_E3 (0x00005700U)
/* R-Car E3 */
#define PRR_PRODUCT_10 (0x00U)
#define PRR_PRODUCT_11 (0x01U)
#define PRR_PRODUCT_20 (0x10U)
#define PRR_PRODUCT_ERR(reg) do{\
ERROR("LSI Product ID(PRR=0x%x) PFC "\
"initialize not supported.\n",reg);\
panic();\
}while(0)
#define PRR_CUT_ERR(reg) do{\
ERROR("LSI Cut ID(PRR=0x%x) PFC "\
"initialize not supported.\n",reg);\
panic();\
}while(0)
void
rcar_pfc_init
(
void
)
{
uint32_t
reg
;
reg
=
mmio_read_32
(
RCAR_PRR
);
#if RCAR_LSI == RCAR_AUTO
switch
(
reg
&
RCAR_PRODUCT_MASK
)
{
case
RCAR_PRODUCT_H3
:
switch
(
reg
&
PRR_CUT_MASK
)
{
case
PRR_PRODUCT_10
:
/* H3 Ver.1.0 */
pfc_init_h3_v1
();
break
;
case
PRR_PRODUCT_11
:
/* H3 Ver.1.1 */
pfc_init_h3_v1
();
break
;
default:
/* H3 Ver.2.0 or later */
pfc_init_h3_v2
();
break
;
}
break
;
case
RCAR_PRODUCT_M3
:
pfc_init_m3
();
break
;
case
RCAR_PRODUCT_M3N
:
pfc_init_m3n
();
break
;
default:
PRR_PRODUCT_ERR
(
reg
);
break
;
}
#elif RCAR_LSI_CUT_COMPAT
switch
(
reg
&
PRR_PRODUCT_MASK
)
{
case
PRR_PRODUCT_H3
:
#if (RCAR_LSI != RCAR_H3) && (RCAR_LSI != RCAR_H3N)
PRR_PRODUCT_ERR
(
reg
);
#else
switch
(
reg
&
PRR_CUT_MASK
)
{
case
PRR_PRODUCT_10
:
/* H3 Ver.1.0 */
pfc_init_h3_v1
();
break
;
case
PRR_PRODUCT_11
:
/* H3 Ver.1.1 */
pfc_init_h3_v1
();
break
;
default:
/* H3 Ver.2.0 or later */
pfc_init_h3_v2
();
break
;
}
#endif
break
;
case
PRR_PRODUCT_M3
:
#if RCAR_LSI != RCAR_M3
PRR_PRODUCT_ERR
(
reg
);
#else
pfc_init_m3
();
#endif
break
;
case
PRR_PRODUCT_M3N
:
#if RCAR_LSI != RCAR_M3N
PRR_PRODUCT_ERR
(
reg
);
#else
pfc_init_m3n
();
#endif
break
;
case
PRR_PRODUCT_E3
:
#if RCAR_LSI != RCAR_E3
PRR_PRODUCT_ERR
(
reg
);
#else
pfc_init_e3
();
#endif
break
;
default:
PRR_PRODUCT_ERR
(
reg
);
break
;
}
#else
#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
/* H3 */
#if RCAR_LSI_CUT == RCAR_CUT_10
/* H3 Ver.1.0 */
if
((
PRR_PRODUCT_H3
|
PRR_PRODUCT_10
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
|
PRR_CUT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
pfc_init_h3_v1
();
#elif RCAR_LSI_CUT == RCAR_CUT_11
/* H3 Ver.1.1 */
if
((
PRR_PRODUCT_H3
|
PRR_PRODUCT_11
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
|
PRR_CUT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
pfc_init_h3_v1
();
#else
/* H3 Ver.2.0 or later */
if
(
PRR_PRODUCT_H3
!=
(
reg
&
PRR_PRODUCT_MASK
))
{
PRR_PRODUCT_ERR
(
reg
);
}
pfc_init_h3_v2
();
#endif
#elif RCAR_LSI == RCAR_M3
/* M3 */
if
((
PRR_PRODUCT_M3
)
!=
(
reg
&
PRR_PRODUCT_MASK
))
{
PRR_PRODUCT_ERR
(
reg
);
}
pfc_init_m3
();
#elif RCAR_LSI == RCAR_M3N
/* M3N */
if
((
PRR_PRODUCT_M3N
)
!=
(
reg
&
PRR_PRODUCT_MASK
))
{
PRR_PRODUCT_ERR
(
reg
);
}
pfc_init_m3n
();
#elif RCAR_LSI == RCAR_E3
/* E3 */
if
((
PRR_PRODUCT_E3
)
!=
(
reg
&
PRR_PRODUCT_MASK
))
{
PRR_PRODUCT_ERR
(
reg
);
}
pfc_init_e3
();
#else
#error "Don't have PFC initialize routine(unknown)."
#endif
#endif
}
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <debug.h>
#include "../qos_common.h"
#include "../qos_reg.h"
#include "qos_init_e3_v10.h"
#define RCAR_QOS_VERSION "rev.0.02"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
#define REF_ARS_ARBSTOPCYCLE_E3 (((SL_INIT_SSLOTCLK_E3) - 5U) << 16U)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
#if RCAR_REF_INT == RCAR_REF_DEFAULT
#include "qos_init_e3_v10_mstat390.h"
#else
#include "qos_init_e3_v10_mstat780.h"
#endif
#endif
static
void
dbsc_setting
(
void
)
{
/* Register write enable */
io_write_32
(
DBSC_DBSYSCNT0
,
0x00001234U
);
/* BUFCAM settings */
io_write_32
(
DBSC_DBCAM0CNF1
,
0x00043218
);
io_write_32
(
DBSC_DBCAM0CNF2
,
0x000000F4
);
io_write_32
(
DBSC_DBSCHCNT0
,
0x000F0037
);
io_write_32
(
DBSC_DBSCHSZ0
,
0x00000001
);
io_write_32
(
DBSC_DBSCHRW0
,
0x22421111
);
/* DDR3 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
/* QoS Settings */
io_write_32
(
DBSC_DBSCHQOS00
,
0x00000F00
);
io_write_32
(
DBSC_DBSCHQOS01
,
0x00000B00
);
io_write_32
(
DBSC_DBSCHQOS02
,
0x00000000
);
io_write_32
(
DBSC_DBSCHQOS03
,
0x00000000
);
io_write_32
(
DBSC_DBSCHQOS40
,
0x00000300
);
io_write_32
(
DBSC_DBSCHQOS41
,
0x000002F0
);
io_write_32
(
DBSC_DBSCHQOS42
,
0x00000200
);
io_write_32
(
DBSC_DBSCHQOS43
,
0x00000100
);
io_write_32
(
DBSC_DBSCHQOS90
,
0x00000100
);
io_write_32
(
DBSC_DBSCHQOS91
,
0x000000F0
);
io_write_32
(
DBSC_DBSCHQOS92
,
0x000000A0
);
io_write_32
(
DBSC_DBSCHQOS93
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS130
,
0x00000100
);
io_write_32
(
DBSC_DBSCHQOS131
,
0x000000F0
);
io_write_32
(
DBSC_DBSCHQOS132
,
0x000000A0
);
io_write_32
(
DBSC_DBSCHQOS133
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS140
,
0x000000C0
);
io_write_32
(
DBSC_DBSCHQOS141
,
0x000000B0
);
io_write_32
(
DBSC_DBSCHQOS142
,
0x00000080
);
io_write_32
(
DBSC_DBSCHQOS143
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS150
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS151
,
0x00000030
);
io_write_32
(
DBSC_DBSCHQOS152
,
0x00000020
);
io_write_32
(
DBSC_DBSCHQOS153
,
0x00000010
);
/* Register write protect */
io_write_32
(
DBSC_DBSYSCNT0
,
0x00000000U
);
}
void
qos_init_e3_v10
(
void
)
{
dbsc_setting
();
/* DRAM Split Address mapping */
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
#if RCAR_LSI == RCAR_E3
#error "Don't set DRAM Split 4ch(E3)"
#else
ERROR
(
"DRAM Split 4ch not supported.(E3)"
);
panic
();
#endif
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
#if RCAR_LSI == RCAR_E3
#error "Don't set DRAM Split 2ch(E3)"
#else
ERROR
(
"DRAM Split 2ch not supported.(E3)"
);
panic
();
#endif
#else
NOTICE
(
"BL2: DRAM Split is OFF
\n
"
);
#endif
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
NOTICE
(
"BL2: QoS is default setting(%s)
\n
"
,
RCAR_QOS_VERSION
);
#endif
#if RCAR_REF_INT == RCAR_REF_DEFAULT
NOTICE
(
"BL2: DRAM refresh interval 3.9 usec
\n
"
);
#else
NOTICE
(
"BL2: DRAM refresh interval 7.8 usec
\n
"
);
#endif
io_write_32
(
QOSCTRL_RAS
,
0x00000020U
);
io_write_64
(
QOSCTRL_DANN
,
0x0404020002020201UL
);
io_write_32
(
QOSCTRL_DANT
,
0x00100804U
);
io_write_32
(
QOSCTRL_FSS
,
0x0000000AU
);
io_write_32
(
QOSCTRL_INSFC
,
0x06330001U
);
io_write_32
(
QOSCTRL_EARLYR
,
0x00000000U
);
io_write_32
(
QOSCTRL_RACNT0
,
0x00010003U
);
io_write_32
(
QOSCTRL_SL_INIT
,
SL_INIT_REFFSSLOT
|
SL_INIT_SLOTSSLOT
|
SL_INIT_SSLOTCLK_E3
);
io_write_32
(
QOSCTRL_REF_ARS
,
REF_ARS_ARBSTOPCYCLE_E3
);
{
uint32_t
i
;
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_fix
);
i
++
)
{
io_write_64
(
QOSBW_FIX_QOS_BANK0
+
i
*
8
,
mstat_fix
[
i
]);
io_write_64
(
QOSBW_FIX_QOS_BANK1
+
i
*
8
,
mstat_fix
[
i
]);
}
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_be
);
i
++
)
{
io_write_64
(
QOSBW_BE_QOS_BANK0
+
i
*
8
,
mstat_be
[
i
]);
io_write_64
(
QOSBW_BE_QOS_BANK1
+
i
*
8
,
mstat_be
[
i
]);
}
}
/* 3DG bus Leaf setting */
io_write_32
(
GPU_ACT_GRD
,
0x00001234U
);
io_write_32
(
GPU_ACT0
,
0x00000000U
);
io_write_32
(
GPU_ACT1
,
0x00000000U
);
io_write_32
(
GPU_ACT2
,
0x00000000U
);
io_write_32
(
GPU_ACT3
,
0x00000000U
);
io_write_32
(
GPU_ACT_GRD
,
0x00000000U
);
/* RT bus Leaf setting */
io_write_32
(
RT_ACT0
,
0x00000000U
);
io_write_32
(
RT_ACT1
,
0x00000000U
);
/* CCI bus Leaf setting */
io_write_32
(
CPU_ACT0
,
0x00000003U
);
io_write_32
(
CPU_ACT1
,
0x00000003U
);
io_write_32
(
QOSCTRL_RAEN
,
0x00000001U
);
io_write_32
(
QOSCTRL_STATQC
,
0x00000001U
);
#else
NOTICE
(
"BL2: QoS is None
\n
"
);
io_write_32
(
QOSCTRL_RAEN
,
0x00000001U
);
#endif
}
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef QOS_INIT_H_E3_V10__
#define QOS_INIT_H_E3_V10__
void
qos_init_e3_v10
(
void
);
#endif
/* QOS_INIT_H_E3_V10__ */
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
static
uint64_t
mstat_fix
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x001008620000FFFFUL
,
/* 0x0038, */
0x001008620000FFFFUL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x001415260000FFFFUL
,
/* 0x0060, */
0x001415260000FFFFUL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x001414930000FFFFUL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x000C08380000FFFFUL
,
/* 0x00a8, */
0x000C04110000FFFFUL
,
/* 0x00b0, */
0x000C04110000FFFFUL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x000C08380000FFFFUL
,
/* 0x00c8, */
0x000C04110000FFFFUL
,
/* 0x00d0, */
0x000C04110000FFFFUL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x001018580000FFFFUL
,
/* 0x00f8, */
0x000C04400000FFFFUL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x001008580000FFFFUL
,
/* 0x0118, */
0x000C19660000FFFFUL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x001008530000FFFFUL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x00100C960000FFFFUL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x001008530000FFFFUL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0010042A0000FFFFUL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x00101D8D0000FFFFUL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x001008530000FFFFUL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x000C04010000FFFFUL
,
/* 0x01c8, */
0x000C04010000FFFFUL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x000C04020000FFFFUL
,
/* 0x01f0, */
0x000C04090000FFFFUL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x000C04090000FFFFUL
,
/* 0x0210, */
0x000C04090000FFFFUL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x000C0C2A0000FFFFUL
,
/* 0x0268, */
0x001410040000FFFFUL
,
/* 0x0270, */
0x001404020000FFFFUL
,
/* 0x0278, */
0x000C08110000FFFFUL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x001410040000FFFFUL
,
/* 0x0298, */
0x001404020000FFFFUL
,
/* 0x02a0, */
0x000C04090000FFFFUL
,
/* 0x02a8, */
0x000C04090000FFFFUL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x000C04020000FFFFUL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x000C04090000FFFFUL
,
/* 0x02d8, */
0x000C04090000FFFFUL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x000C04020000FFFFUL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x0000000000000000UL
,
/* 0x0360, */
0x0000000000000000UL
,
/* 0x0368, */
0x0000000000000000UL
,
/* 0x0370, */
0x000C04020000FFFFUL
,
/* 0x0378, */
0x000C04020000FFFFUL
,
/* 0x0380, */
0x000C04090000FFFFUL
,
/* 0x0388, */
0x000C04090000FFFFUL
,
/* 0x0390, */
0x0000000000000000UL
,
};
static
uint64_t
mstat_be
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0012001005F03401UL
,
/* 0x0030, */
0x0000000000000000UL
,
/* 0x0038, */
0x0000000000000000UL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x0000000000000000UL
,
/* 0x0060, */
0x0000000000000000UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0000000000000000UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x0021060005FFFC01UL
,
/* 0x01c8, */
0x0021060005FFFC01UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0021010005F79801UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0021010005F79801UL
,
/* 0x0218, */
0x0011010005F79801UL
,
/* 0x0220, */
0x0011010005F79801UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0011010005F79801UL
,
/* 0x0238, */
0x0011010005F79801UL
,
/* 0x0240, */
0x0012010005F79801UL
,
/* 0x0248, */
0x0011010005F79801UL
,
/* 0x0250, */
0x0012010005F79801UL
,
/* 0x0258, */
0x0011010005F79801UL
,
/* 0x0260, */
0x0000000000000000UL
,
/* 0x0268, */
0x0000000000000000UL
,
/* 0x0270, */
0x0000000000000000UL
,
/* 0x0278, */
0x0000000000000000UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x0000000000000000UL
,
/* 0x0298, */
0x0000000000000000UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0011060005FFFC01UL
,
/* 0x02f8, */
0x0011060005FFFC01UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0012001005F03401UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x0012060005FFFC01UL
,
/* 0x0360, */
0x0012060005FFFC01UL
,
/* 0x0368, */
0x0012001005F03401UL
,
/* 0x0370, */
0x0000000000000000UL
,
/* 0x0378, */
0x0000000000000000UL
,
/* 0x0380, */
0x0000000000000000UL
,
/* 0x0388, */
0x0000000000000000UL
,
/* 0x0390, */
0x0012001005F03401UL
,
};
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
static
uint64_t
mstat_fix
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x001010C40000FFFFUL
,
/* 0x0038, */
0x001010C40000FFFFUL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x00142A4B0000FFFFUL
,
/* 0x0060, */
0x00142A4B0000FFFFUL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x001429260000FFFFUL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x000C10700000FFFFUL
,
/* 0x00a8, */
0x000C08210000FFFFUL
,
/* 0x00b0, */
0x000C08210000FFFFUL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x000C10700000FFFFUL
,
/* 0x00c8, */
0x000C08210000FFFFUL
,
/* 0x00d0, */
0x000C08210000FFFFUL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x00102CAF0000FFFFUL
,
/* 0x00f8, */
0x000C087F0000FFFFUL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x00100CAF0000FFFFUL
,
/* 0x0118, */
0x000C32CC0000FFFFUL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x00100CA50000FFFFUL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0010152C0000FFFFUL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x00100CA50000FFFFUL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x001008530000FFFFUL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x001037190000FFFFUL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x00100CA50000FFFFUL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x000C04010000FFFFUL
,
/* 0x01c8, */
0x000C04010000FFFFUL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x000C04040000FFFFUL
,
/* 0x01f0, */
0x000C08110000FFFFUL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x000C04110000FFFFUL
,
/* 0x0210, */
0x000C08110000FFFFUL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x000C18530000FFFFUL
,
/* 0x0268, */
0x00141C070000FFFFUL
,
/* 0x0270, */
0x001404040000FFFFUL
,
/* 0x0278, */
0x000C0C210000FFFFUL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x00141C070000FFFFUL
,
/* 0x0298, */
0x001404040000FFFFUL
,
/* 0x02a0, */
0x000C04110000FFFFUL
,
/* 0x02a8, */
0x000C04110000FFFFUL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x000C04040000FFFFUL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x000C04110000FFFFUL
,
/* 0x02d8, */
0x000C04110000FFFFUL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x000C04040000FFFFUL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x0000000000000000UL
,
/* 0x0360, */
0x0000000000000000UL
,
/* 0x0368, */
0x0000000000000000UL
,
/* 0x0370, */
0x000C04040000FFFFUL
,
/* 0x0378, */
0x000C04040000FFFFUL
,
/* 0x0380, */
0x000C04110000FFFFUL
,
/* 0x0388, */
0x000C04110000FFFFUL
,
/* 0x0390, */
0x0000000000000000UL
,
};
static
uint64_t
mstat_be
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0012001002F03401UL
,
/* 0x0030, */
0x0000000000000000UL
,
/* 0x0038, */
0x0000000000000000UL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x0000000000000000UL
,
/* 0x0060, */
0x0000000000000000UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0000000000000000UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x0021060002FFFC01UL
,
/* 0x01c8, */
0x0021060002FFFC01UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0021010002F3CC01UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0021010002F3CC01UL
,
/* 0x0218, */
0x0011010002F3CC01UL
,
/* 0x0220, */
0x0011010002F3CC01UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0011010002F3CC01UL
,
/* 0x0238, */
0x0011010002F3CC01UL
,
/* 0x0240, */
0x0012010002F3CC01UL
,
/* 0x0248, */
0x0011010002F3CC01UL
,
/* 0x0250, */
0x0012010002F3CC01UL
,
/* 0x0258, */
0x0011010002F3CC01UL
,
/* 0x0260, */
0x0000000000000000UL
,
/* 0x0268, */
0x0000000000000000UL
,
/* 0x0270, */
0x0000000000000000UL
,
/* 0x0278, */
0x0000000000000000UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x0000000000000000UL
,
/* 0x0298, */
0x0000000000000000UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0011060002FFFC01UL
,
/* 0x02f8, */
0x0011060002FFFC01UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0012001002F03401UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x0012060002FFFC01UL
,
/* 0x0360, */
0x0012060002FFFC01UL
,
/* 0x0368, */
0x0012001002F03401UL
,
/* 0x0370, */
0x0000000000000000UL
,
/* 0x0378, */
0x0000000000000000UL
,
/* 0x0380, */
0x0000000000000000UL
,
/* 0x0388, */
0x0000000000000000UL
,
/* 0x0390, */
0x0012001002F03401UL
,
};
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <debug.h>
#include "../qos_common.h"
#include "qos_init_h3_v10.h"
#define RCAR_QOS_VERSION "rev.0.36"
#define RCAR_QOS_NONE (3U)
#define RCAR_QOS_TYPE_DEFAULT (0U)
#define RCAR_DRAM_SPLIT_LINEAR (0U)
#define RCAR_DRAM_SPLIT_4CH (1U)
#define RCAR_DRAM_SPLIT_2CH (2U)
#define RCAR_DRAM_SPLIT_AUTO (3U)
#define AXI_BASE (0xE6784000U)
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
#define ADSPLCR0_SWP (0x0CU)
#define MSTAT_BASE (0xE67E0000U)
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
#define RALLOC_BASE (0xE67F0000U)
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
static
const
mstat_slot_t
mstat_fix
[]
=
{
{
0x0000U
,
0x0000000000000000UL
},
{
0x0008U
,
0x0000000000000000UL
},
{
0x0010U
,
0x0000000000000000UL
},
{
0x0018U
,
0x0000000000000000UL
},
{
0x0020U
,
0x0000000000000000UL
},
{
0x0028U
,
0x0000000000000000UL
},
{
0x0030U
,
0x0000000000000000UL
},
{
0x0038U
,
0x0000000000000000UL
},
{
0x0040U
,
0x00140C050000FFFFUL
},
{
0x0048U
,
0x0000000000000000UL
},
{
0x0050U
,
0x0000000000000000UL
},
{
0x0058U
,
0x001404030000FFFFUL
},
{
0x0060U
,
0x001408060000FFFFUL
},
{
0x0068U
,
0x0000000000000000UL
},
{
0x0070U
,
0x0000000000000000UL
},
{
0x0078U
,
0x0000000000000000UL
},
{
0x0080U
,
0x0000000000000000UL
},
{
0x0088U
,
0x00140C050000FFFFUL
},
{
0x0090U
,
0x001408060000FFFFUL
},
{
0x0098U
,
0x001404020000FFFFUL
},
{
0x00A0U
,
0x0000000000000000UL
},
{
0x00A8U
,
0x0000000000000000UL
},
{
0x00B0U
,
0x0000000000000000UL
},
{
0x00B8U
,
0x0000000000000000UL
},
{
0x00C0U
,
0x0000000000000000UL
},
{
0x00C8U
,
0x0000000000000000UL
},
{
0x00D0U
,
0x0000000000000000UL
},
{
0x00D8U
,
0x0000000000000000UL
},
{
0x00E0U
,
0x0000000000000000UL
},
{
0x00E8U
,
0x0000000000000000UL
},
{
0x00F0U
,
0x0000000000000000UL
},
{
0x00F8U
,
0x0000000000000000UL
},
{
0x0100U
,
0x0000000000000000UL
},
{
0x0108U
,
0x0000000000000000UL
},
{
0x0110U
,
0x0000000000000000UL
},
{
0x0118U
,
0x0000000000000000UL
},
{
0x0120U
,
0x0000000000000000UL
},
{
0x0128U
,
0x0000000000000000UL
},
{
0x0130U
,
0x0000000000000000UL
},
{
0x0138U
,
0x001004020000FFFFUL
},
{
0x0140U
,
0x001004020000FFFFUL
},
{
0x0148U
,
0x001004020000FFFFUL
},
{
0x0150U
,
0x001008050000FFFFUL
},
{
0x0158U
,
0x001008050000FFFFUL
},
{
0x0160U
,
0x001008050000FFFFUL
},
{
0x0168U
,
0x001008050000FFFFUL
},
{
0x0170U
,
0x001008050000FFFFUL
},
{
0x0178U
,
0x001004030000FFFFUL
},
{
0x0180U
,
0x001004030000FFFFUL
},
{
0x0188U
,
0x001004030000FFFFUL
},
{
0x0190U
,
0x001014140000FFFFUL
},
{
0x0198U
,
0x001014140000FFFFUL
},
{
0x01A0U
,
0x001008060000FFFFUL
},
{
0x01A8U
,
0x001008060000FFFFUL
},
{
0x01B0U
,
0x001008060000FFFFUL
},
{
0x01B8U
,
0x0000000000000000UL
},
{
0x01C0U
,
0x0000000000000000UL
},
{
0x01C8U
,
0x0000000000000000UL
},
{
0x01D0U
,
0x0000000000000000UL
},
{
0x01D8U
,
0x0000000000000000UL
},
{
0x01E0U
,
0x0000000000000000UL
},
{
0x01E8U
,
0x0000000000000000UL
},
{
0x01F0U
,
0x0000000000000000UL
},
{
0x01F8U
,
0x0000000000000000UL
},
{
0x0200U
,
0x0000000000000000UL
},
{
0x0208U
,
0x0000000000000000UL
},
{
0x0210U
,
0x0000000000000000UL
},
{
0x0218U
,
0x0000000000000000UL
},
{
0x0220U
,
0x0000000000000000UL
},
{
0x0228U
,
0x0000000000000000UL
},
{
0x0230U
,
0x0000000000000000UL
},
{
0x0238U
,
0x0000000000000000UL
},
{
0x0240U
,
0x0000000000000000UL
},
{
0x0248U
,
0x0000000000000000UL
},
{
0x0250U
,
0x0000000000000000UL
},
{
0x0258U
,
0x0000000000000000UL
},
{
0x0260U
,
0x0000000000000000UL
},
{
0x0268U
,
0x0000000000000000UL
},
{
0x0270U
,
0x0000000000000000UL
},
{
0x0278U
,
0x0000000000000000UL
},
{
0x0280U
,
0x0000000000000000UL
},
{
0x0288U
,
0x0000000000000000UL
},
{
0x0290U
,
0x0000000000000000UL
},
{
0x0298U
,
0x0000000000000000UL
},
{
0x02A0U
,
0x0000000000000000UL
},
{
0x02A8U
,
0x0000000000000000UL
},
{
0x02B0U
,
0x0000000000000000UL
},
{
0x02B8U
,
0x0000000000000000UL
},
{
0x02C0U
,
0x0000000000000000UL
},
{
0x02C8U
,
0x0000000000000000UL
},
{
0x02D0U
,
0x0000000000000000UL
},
{
0x02D8U
,
0x0000000000000000UL
},
{
0x02E0U
,
0x0000000000000000UL
},
{
0x02E8U
,
0x0000000000000000UL
},
{
0x02F0U
,
0x0000000000000000UL
},
{
0x02F8U
,
0x0000000000000000UL
},
{
0x0300U
,
0x0000000000000000UL
},
{
0x0308U
,
0x0000000000000000UL
},
{
0x0310U
,
0x0000000000000000UL
},
{
0x0318U
,
0x0000000000000000UL
},
{
0x0320U
,
0x0000000000000000UL
},
{
0x0328U
,
0x0000000000000000UL
},
{
0x0330U
,
0x0000000000000000UL
},
{
0x0338U
,
0x0000000000000000UL
},
};
static
const
mstat_slot_t
mstat_be
[]
=
{
{
0x0000U
,
0x001000100C8FFC01UL
},
{
0x0008U
,
0x001000100C8FFC01UL
},
{
0x0010U
,
0x001000100C8FFC01UL
},
{
0x0018U
,
0x001000100C8FFC01UL
},
{
0x0020U
,
0x001000100C8FFC01UL
},
{
0x0028U
,
0x001000100C8FFC01UL
},
{
0x0030U
,
0x001000100C8FFC01UL
},
{
0x0038U
,
0x001000100C8FFC01UL
},
{
0x0040U
,
0x0000000000000000UL
},
{
0x0048U
,
0x0000000000000000UL
},
{
0x0050U
,
0x001000100C8FFC01UL
},
{
0x0058U
,
0x0000000000000000UL
},
{
0x0060U
,
0x0000000000000000UL
},
{
0x0068U
,
0x001000100C8FFC01UL
},
{
0x0070U
,
0x001000100C8FFC01UL
},
{
0x0078U
,
0x001000100C8FFC01UL
},
{
0x0080U
,
0x001000100C8FFC01UL
},
{
0x0088U
,
0x0000000000000000UL
},
{
0x0090U
,
0x0000000000000000UL
},
{
0x0098U
,
0x0000000000000000UL
},
{
0x00A0U
,
0x001000100C8FFC01UL
},
{
0x00A8U
,
0x001000100C8FFC01UL
},
{
0x00B0U
,
0x001000100C8FFC01UL
},
{
0x00B8U
,
0x001000100C8FFC01UL
},
{
0x00C0U
,
0x001000100C8FFC01UL
},
{
0x00C8U
,
0x001000100C8FFC01UL
},
{
0x00D0U
,
0x001000100C8FFC01UL
},
{
0x00D8U
,
0x002000200C8FFC01UL
},
{
0x00E0U
,
0x002000200C8FFC01UL
},
{
0x00E8U
,
0x001000100C8FFC01UL
},
{
0x00F0U
,
0x001000100C8FFC01UL
},
{
0x00F8U
,
0x001000100C8FFC01UL
},
{
0x0100U
,
0x0000000000000000UL
},
{
0x0108U
,
0x002000200C8FFC01UL
},
{
0x0110U
,
0x001000100C8FFC01UL
},
{
0x0118U
,
0x001000100C8FFC01UL
},
{
0x0120U
,
0x0000000000000000UL
},
{
0x0128U
,
0x002000200C8FFC01UL
},
{
0x0130U
,
0x001000100C8FFC01UL
},
{
0x0138U
,
0x0000000000000000UL
},
{
0x0140U
,
0x0000000000000000UL
},
{
0x0148U
,
0x0000000000000000UL
},
{
0x0150U
,
0x0000000000000000UL
},
{
0x0158U
,
0x0000000000000000UL
},
{
0x0160U
,
0x0000000000000000UL
},
{
0x0168U
,
0x0000000000000000UL
},
{
0x0170U
,
0x0000000000000000UL
},
{
0x0178U
,
0x0000000000000000UL
},
{
0x0180U
,
0x0000000000000000UL
},
{
0x0188U
,
0x0000000000000000UL
},
{
0x0190U
,
0x0000000000000000UL
},
{
0x0198U
,
0x0000000000000000UL
},
{
0x01A0U
,
0x0000000000000000UL
},
{
0x01A8U
,
0x0000000000000000UL
},
{
0x01B0U
,
0x0000000000000000UL
},
{
0x01B8U
,
0x001000100C8FFC01UL
},
{
0x01C0U
,
0x001000200C8FFC01UL
},
{
0x01C8U
,
0x001000200C8FFC01UL
},
{
0x01D0U
,
0x001000200C8FFC01UL
},
{
0x01D8U
,
0x001000200C8FFC01UL
},
{
0x01E0U
,
0x001000100C8FFC01UL
},
{
0x01E8U
,
0x001000100C8FFC01UL
},
{
0x01F0U
,
0x001000100C8FFC01UL
},
{
0x01F8U
,
0x001000100C8FFC01UL
},
{
0x0200U
,
0x001000100C8FFC01UL
},
{
0x0208U
,
0x001000100C8FFC01UL
},
{
0x0210U
,
0x001000100C8FFC01UL
},
{
0x0218U
,
0x001000100C8FFC01UL
},
{
0x0220U
,
0x001000100C8FFC01UL
},
{
0x0228U
,
0x001000100C8FFC01UL
},
{
0x0230U
,
0x001000100C8FFC01UL
},
{
0x0238U
,
0x001000100C8FFC01UL
},
{
0x0240U
,
0x001000100C8FFC01UL
},
{
0x0248U
,
0x001000100C8FFC01UL
},
{
0x0250U
,
0x001000100C8FFC01UL
},
{
0x0258U
,
0x001000100C8FFC01UL
},
{
0x0260U
,
0x001000100C8FFC01UL
},
{
0x0268U
,
0x001000100C8FFC01UL
},
{
0x0270U
,
0x001000100C8FFC01UL
},
{
0x0278U
,
0x001000100C8FFC01UL
},
{
0x0280U
,
0x001000100C8FFC01UL
},
{
0x0288U
,
0x001000100C8FFC01UL
},
{
0x0290U
,
0x001000100C8FFC01UL
},
{
0x0298U
,
0x001000100C8FFC01UL
},
{
0x02A0U
,
0x001000100C8FFC01UL
},
{
0x02A8U
,
0x001000100C8FFC01UL
},
{
0x02B0U
,
0x001000100C8FFC01UL
},
{
0x02B8U
,
0x001000100C8FFC01UL
},
{
0x02C0U
,
0x001000100C8FFC01UL
},
{
0x02C8U
,
0x001000100C8FFC01UL
},
{
0x02D0U
,
0x001000100C8FFC01UL
},
{
0x02D8U
,
0x001000100C8FFC01UL
},
{
0x02E0U
,
0x001000100C8FFC01UL
},
{
0x02E8U
,
0x001000100C8FFC01UL
},
{
0x02F0U
,
0x001000200C8FFC01UL
},
{
0x02F8U
,
0x001000300C8FFC01UL
},
{
0x0300U
,
0x0000000000000000UL
},
{
0x0308U
,
0x001000200C8FFC01UL
},
{
0x0310U
,
0x001000300C8FFC01UL
},
{
0x0318U
,
0x0000000000000000UL
},
{
0x0320U
,
0x001000200C8FFC01UL
},
{
0x0328U
,
0x001000300C8FFC01UL
},
{
0x0330U
,
0x001000200C8FFC01UL
},
{
0x0338U
,
0x001000300C8FFC01UL
},
};
#endif
void
qos_init_h3_v10
(
void
)
{
/* DRAM Split Address mapping */
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
NOTICE
(
"BL2: DRAM Split is 4ch
\n
"
);
io_write_32
(
AXI_ADSPLCR0
,
ADSPLCR0_ADRMODE_DEFAULT
|
ADSPLCR0_SPLITSEL
(
0xFFU
)
|
ADSPLCR0_AREA
(
0x1BU
)
|
ADSPLCR0_SWP
);
io_write_32
(
AXI_ADSPLCR1
,
0x00000000U
);
io_write_32
(
AXI_ADSPLCR2
,
0xA8A90000U
);
io_write_32
(
AXI_ADSPLCR3
,
0x00000000U
);
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
NOTICE
(
"BL2: DRAM Split is 2ch
\n
"
);
io_write_32
(
AXI_ADSPLCR0
,
0x00000000U
);
io_write_32
(
AXI_ADSPLCR1
,
ADSPLCR0_ADRMODE_DEFAULT
|
ADSPLCR0_SPLITSEL
(
0xFFU
)
|
ADSPLCR0_AREA
(
0x1BU
)
|
ADSPLCR0_SWP
);
io_write_32
(
AXI_ADSPLCR2
,
0x00000000U
);
io_write_32
(
AXI_ADSPLCR3
,
0x00000000U
);
#else
NOTICE
(
"BL2: DRAM Split is OFF
\n
"
);
#endif
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
NOTICE
(
"BL2: QoS is default setting(%s)
\n
"
,
RCAR_QOS_VERSION
);
#endif
/* AR Cache setting */
io_write_32
(
0xE67D1000U
,
0x00000100U
);
io_write_32
(
0xE67D1008U
,
0x00000100U
);
/* Resource Alloc setting */
io_write_32
(
RALLOC_RAS
,
0x00000040U
);
io_write_32
(
RALLOC_FIXTH
,
0x000F0005U
);
io_write_32
(
RALLOC_REGGD
,
0x00000004U
);
io_write_64
(
RALLOC_DANN
,
0x0202000004040404UL
);
io_write_32
(
RALLOC_DANT
,
0x003C1110U
);
io_write_32
(
RALLOC_EC
,
0x00080001U
);
/* need for H3 v1.* */
io_write_64
(
RALLOC_EMS
,
0x0000000000000000UL
);
io_write_32
(
RALLOC_INSFC
,
0xC7840001U
);
io_write_32
(
RALLOC_BERR
,
0x00000000U
);
/* MSTAT setting */
io_write_32
(
MSTAT_SL_INIT
,
SL_INIT_REFFSSLOT
|
SL_INIT_SLOTSSLOT
|
SL_INIT_SSLOTCLK
);
io_write_32
(
MSTAT_REF_ARS
,
0x00330000U
);
/* MSTAT SRAM setting */
for
(
uint32_t
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_fix
);
i
++
)
{
io_write_64
(
MSTAT_FIX_QOS_BANK0
+
mstat_fix
[
i
].
addr
,
mstat_fix
[
i
].
value
);
io_write_64
(
MSTAT_FIX_QOS_BANK1
+
mstat_fix
[
i
].
addr
,
mstat_fix
[
i
].
value
);
}
for
(
uint32_t
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_be
);
i
++
)
{
io_write_64
(
MSTAT_BE_QOS_BANK0
+
mstat_be
[
i
].
addr
,
mstat_be
[
i
].
value
);
io_write_64
(
MSTAT_BE_QOS_BANK1
+
mstat_be
[
i
].
addr
,
mstat_be
[
i
].
value
);
}
/* 3DG bus Leaf setting */
io_write_32
(
0xFD820808U
,
0x00001234U
);
io_write_32
(
0xFD820800U
,
0x0000003FU
);
io_write_32
(
0xFD821800U
,
0x0000003FU
);
io_write_32
(
0xFD822800U
,
0x0000003FU
);
io_write_32
(
0xFD823800U
,
0x0000003FU
);
io_write_32
(
0xFD824800U
,
0x0000003FU
);
io_write_32
(
0xFD825800U
,
0x0000003FU
);
io_write_32
(
0xFD826800U
,
0x0000003FU
);
io_write_32
(
0xFD827800U
,
0x0000003FU
);
/* Resource Alloc start */
io_write_32
(
RALLOC_RAEN
,
0x00000001U
);
/* MSTAT start */
io_write_32
(
MSTAT_STATQC
,
0x00000001U
);
#else
NOTICE
(
"BL2: QoS is None
\n
"
);
/* Resource Alloc setting */
io_write_32
(
RALLOC_EC
,
0x00080001U
);
/* need for H3 v1.* */
#endif
/* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
}
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef QOS_INIT_H_H3_V10__
#define QOS_INIT_H_H3_V10__
void
qos_init_h3_v10
(
void
);
#endif
/* QOS_INIT_H_H3_V10__ */
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