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adam.huang
Arm Trusted Firmware
Commits
a51443fa
Unverified
Commit
a51443fa
authored
Oct 18, 2018
by
Soby Mathew
Committed by
GitHub
Oct 18, 2018
Browse files
Merge pull request #1582 from ldts/rcar_gen3/upstream
rcar_gen3: initial support
parents
0059be2d
84433c50
Changes
147
Show whitespace changes
Inline
Side-by-side
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <debug.h>
#include "../qos_common.h"
#include "qos_init_m3_v10.h"
#define RCAR_QOS_VERSION "rev.0.19"
#define RCAR_QOS_NONE (3U)
#define RCAR_QOS_TYPE_DEFAULT (0U)
#define RCAR_DRAM_SPLIT_LINEAR (0U)
#define RCAR_DRAM_SPLIT_4CH (1U)
#define RCAR_DRAM_SPLIT_2CH (2U)
#define RCAR_DRAM_SPLIT_AUTO (3U)
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
#define DBSC_BASE (0xE6790000U)
#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
#define AXI_BASE (0xE6784000U)
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
#define ADSPLCR0_SWP (0x0CU)
#define MSTAT_BASE (0xE67E0000U)
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
#define RALLOC_BASE (0xE67F0000U)
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
#define RALLOC_FSS (RALLOC_BASE + 0x0048U)
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
static
const
mstat_slot_t
mstat_fix
[]
=
{
{
0x0000U
,
0x0000000000000000UL
},
{
0x0008U
,
0x0000000000000000UL
},
{
0x0010U
,
0x0000000000000000UL
},
{
0x0018U
,
0x0000000000000000UL
},
{
0x0020U
,
0x0000000000000000UL
},
{
0x0028U
,
0x0000000000000000UL
},
{
0x0030U
,
0x001004030000FFFFUL
},
{
0x0038U
,
0x001004030000FFFFUL
},
{
0x0040U
,
0x001414090000FFFFUL
},
{
0x0048U
,
0x0000000000000000UL
},
{
0x0050U
,
0x001410010000FFFFUL
},
{
0x0058U
,
0x00140C090000FFFFUL
},
{
0x0060U
,
0x00140C090000FFFFUL
},
{
0x0068U
,
0x0000000000000000UL
},
{
0x0070U
,
0x001410010000FFFFUL
},
{
0x0078U
,
0x001004020000FFFFUL
},
{
0x0080U
,
0x0000000000000000UL
},
{
0x0088U
,
0x001414090000FFFFUL
},
{
0x0090U
,
0x001408060000FFFFUL
},
{
0x0098U
,
0x0000000000000000UL
},
{
0x00A0U
,
0x000C08020000FFFFUL
},
{
0x00A8U
,
0x000C04010000FFFFUL
},
{
0x00B0U
,
0x000C04010000FFFFUL
},
{
0x00B8U
,
0x0000000000000000UL
},
{
0x00C0U
,
0x000C08020000FFFFUL
},
{
0x00C8U
,
0x000C04010000FFFFUL
},
{
0x00D0U
,
0x000C04010000FFFFUL
},
{
0x00D8U
,
0x000C04030000FFFFUL
},
{
0x00E0U
,
0x000C100F0000FFFFUL
},
{
0x00E8U
,
0x0000000000000000UL
},
{
0x00F0U
,
0x001010080000FFFFUL
},
{
0x00F8U
,
0x0000000000000000UL
},
{
0x0100U
,
0x0000000000000000UL
},
{
0x0108U
,
0x0000000000000000UL
},
{
0x0110U
,
0x001010080000FFFFUL
},
{
0x0118U
,
0x0000000000000000UL
},
{
0x0120U
,
0x0000000000000000UL
},
{
0x0128U
,
0x0000000000000000UL
},
{
0x0130U
,
0x0000000000000000UL
},
{
0x0138U
,
0x00100C0A0000FFFFUL
},
{
0x0140U
,
0x0000000000000000UL
},
{
0x0148U
,
0x0000000000000000UL
},
{
0x0150U
,
0x00100C0A0000FFFFUL
},
{
0x0158U
,
0x0000000000000000UL
},
{
0x0160U
,
0x00100C0A0000FFFFUL
},
{
0x0168U
,
0x0000000000000000UL
},
{
0x0170U
,
0x0000000000000000UL
},
{
0x0178U
,
0x001008050000FFFFUL
},
{
0x0180U
,
0x0000000000000000UL
},
{
0x0188U
,
0x0000000000000000UL
},
{
0x0190U
,
0x001028280000FFFFUL
},
{
0x0198U
,
0x0000000000000000UL
},
{
0x01A0U
,
0x00100C0A0000FFFFUL
},
{
0x01A8U
,
0x0000000000000000UL
},
{
0x01B0U
,
0x0000000000000000UL
},
{
0x01B8U
,
0x0000000000000000UL
},
{
0x01C0U
,
0x0000000000000000UL
},
{
0x01C8U
,
0x0000000000000000UL
},
{
0x01D0U
,
0x0000000000000000UL
},
{
0x01D8U
,
0x0000000000000000UL
},
{
0x01E0U
,
0x0000000000000000UL
},
{
0x01E8U
,
0x0000000000000000UL
},
{
0x01F0U
,
0x0000000000000000UL
},
{
0x01F8U
,
0x0000000000000000UL
},
{
0x0200U
,
0x0000000000000000UL
},
{
0x0208U
,
0x0000000000000000UL
},
{
0x0210U
,
0x0000000000000000UL
},
{
0x0218U
,
0x0000000000000000UL
},
{
0x0220U
,
0x0000000000000000UL
},
{
0x0228U
,
0x0000000000000000UL
},
{
0x0230U
,
0x0000000000000000UL
},
{
0x0238U
,
0x0000000000000000UL
},
{
0x0240U
,
0x0000000000000000UL
},
{
0x0248U
,
0x0000000000000000UL
},
{
0x0250U
,
0x0000000000000000UL
},
{
0x0258U
,
0x0000000000000000UL
},
{
0x0260U
,
0x0000000000000000UL
},
{
0x0268U
,
0x001408010000FFFFUL
},
{
0x0270U
,
0x001404010000FFFFUL
},
{
0x0278U
,
0x0000000000000000UL
},
{
0x0280U
,
0x0000000000000000UL
},
{
0x0288U
,
0x0000000000000000UL
},
{
0x0290U
,
0x001408010000FFFFUL
},
{
0x0298U
,
0x001404010000FFFFUL
},
{
0x02A0U
,
0x000C04010000FFFFUL
},
{
0x02A8U
,
0x000C04010000FFFFUL
},
{
0x02B0U
,
0x001404010000FFFFUL
},
{
0x02B8U
,
0x0000000000000000UL
},
{
0x02C0U
,
0x0000000000000000UL
},
{
0x02C8U
,
0x0000000000000000UL
},
{
0x02D0U
,
0x000C04010000FFFFUL
},
{
0x02D8U
,
0x000C04010000FFFFUL
},
{
0x02E0U
,
0x001404010000FFFFUL
},
{
0x02E8U
,
0x0000000000000000UL
},
{
0x02F0U
,
0x0000000000000000UL
},
{
0x02F8U
,
0x0000000000000000UL
},
{
0x0300U
,
0x0000000000000000UL
},
{
0x0308U
,
0x0000000000000000UL
},
{
0x0310U
,
0x0000000000000000UL
},
{
0x0318U
,
0x0000000000000000UL
},
{
0x0320U
,
0x0000000000000000UL
},
{
0x0328U
,
0x0000000000000000UL
},
{
0x0330U
,
0x0000000000000000UL
},
{
0x0338U
,
0x0000000000000000UL
},
{
0x0340U
,
0x0000000000000000UL
},
{
0x0348U
,
0x0000000000000000UL
},
{
0x0350U
,
0x0000000000000000UL
},
};
static
const
mstat_slot_t
mstat_be
[]
=
{
{
0x0000U
,
0x001200100C89C401UL
},
{
0x0008U
,
0x001200100C89C401UL
},
{
0x0010U
,
0x001200100C89C401UL
},
{
0x0018U
,
0x001200100C89C401UL
},
{
0x0020U
,
0x0000000000000000UL
},
{
0x0028U
,
0x001100100C803401UL
},
{
0x0030U
,
0x0000000000000000UL
},
{
0x0038U
,
0x0000000000000000UL
},
{
0x0040U
,
0x0000000000000000UL
},
{
0x0048U
,
0x0000000000000000UL
},
{
0x0050U
,
0x0000000000000000UL
},
{
0x0058U
,
0x0000000000000000UL
},
{
0x0060U
,
0x0000000000000000UL
},
{
0x0068U
,
0x0000000000000000UL
},
{
0x0070U
,
0x0000000000000000UL
},
{
0x0078U
,
0x0000000000000000UL
},
{
0x0080U
,
0x0000000000000000UL
},
{
0x0088U
,
0x0000000000000000UL
},
{
0x0090U
,
0x0000000000000000UL
},
{
0x0098U
,
0x0000000000000000UL
},
{
0x00A0U
,
0x0000000000000000UL
},
{
0x00A8U
,
0x0000000000000000UL
},
{
0x00B0U
,
0x0000000000000000UL
},
{
0x00B8U
,
0x0000000000000000UL
},
{
0x00C0U
,
0x0000000000000000UL
},
{
0x00C8U
,
0x0000000000000000UL
},
{
0x00D0U
,
0x0000000000000000UL
},
{
0x00D8U
,
0x0000000000000000UL
},
{
0x00E0U
,
0x0000000000000000UL
},
{
0x00E8U
,
0x0000000000000000UL
},
{
0x00F0U
,
0x0000000000000000UL
},
{
0x00F8U
,
0x0000000000000000UL
},
{
0x0100U
,
0x0000000000000000UL
},
{
0x0108U
,
0x0000000000000000UL
},
{
0x0110U
,
0x0000000000000000UL
},
{
0x0118U
,
0x0000000000000000UL
},
{
0x0120U
,
0x0000000000000000UL
},
{
0x0128U
,
0x0000000000000000UL
},
{
0x0130U
,
0x0000000000000000UL
},
{
0x0138U
,
0x0000000000000000UL
},
{
0x0140U
,
0x0000000000000000UL
},
{
0x0148U
,
0x0000000000000000UL
},
{
0x0150U
,
0x0000000000000000UL
},
{
0x0158U
,
0x0000000000000000UL
},
{
0x0160U
,
0x0000000000000000UL
},
{
0x0168U
,
0x0000000000000000UL
},
{
0x0170U
,
0x0000000000000000UL
},
{
0x0178U
,
0x0000000000000000UL
},
{
0x0180U
,
0x0000000000000000UL
},
{
0x0188U
,
0x0000000000000000UL
},
{
0x0190U
,
0x0000000000000000UL
},
{
0x0198U
,
0x0000000000000000UL
},
{
0x01A0U
,
0x0000000000000000UL
},
{
0x01A8U
,
0x0000000000000000UL
},
{
0x01B0U
,
0x0000000000000000UL
},
{
0x01B8U
,
0x0000000000000000UL
},
{
0x01C0U
,
0x001100500C8FFC01UL
},
{
0x01C8U
,
0x001100500C8FFC01UL
},
{
0x01D0U
,
0x001100500C8FFC01UL
},
{
0x01D8U
,
0x001100500C8FFC01UL
},
{
0x01E0U
,
0x0000000000000000UL
},
{
0x01E8U
,
0x001200100C803401UL
},
{
0x01F0U
,
0x001100100C80FC01UL
},
{
0x01F8U
,
0x0000000000000000UL
},
{
0x0200U
,
0x0000000000000000UL
},
{
0x0208U
,
0x001200100C80FC01UL
},
{
0x0210U
,
0x001100100C80FC01UL
},
{
0x0218U
,
0x001100100C825801UL
},
{
0x0220U
,
0x001100100C825801UL
},
{
0x0228U
,
0x0000000000000000UL
},
{
0x0230U
,
0x001100100C825801UL
},
{
0x0238U
,
0x001100100C825801UL
},
{
0x0240U
,
0x001200100C8BB801UL
},
{
0x0248U
,
0x001100100C8EA401UL
},
{
0x0250U
,
0x001200100C8BB801UL
},
{
0x0258U
,
0x001100100C8EA401UL
},
{
0x0260U
,
0x001100100C84E401UL
},
{
0x0268U
,
0x0000000000000000UL
},
{
0x0270U
,
0x0000000000000000UL
},
{
0x0278U
,
0x001100100C81F401UL
},
{
0x0280U
,
0x0000000000000000UL
},
{
0x0288U
,
0x0000000000000000UL
},
{
0x0290U
,
0x0000000000000000UL
},
{
0x0298U
,
0x0000000000000000UL
},
{
0x02A0U
,
0x0000000000000000UL
},
{
0x02A8U
,
0x0000000000000000UL
},
{
0x02B0U
,
0x0000000000000000UL
},
{
0x02B8U
,
0x001100100C803401UL
},
{
0x02C0U
,
0x0000000000000000UL
},
{
0x02C8U
,
0x0000000000000000UL
},
{
0x02D0U
,
0x0000000000000000UL
},
{
0x02D8U
,
0x0000000000000000UL
},
{
0x02E0U
,
0x0000000000000000UL
},
{
0x02E8U
,
0x001100100C803401UL
},
{
0x02F0U
,
0x001100300C8FFC01UL
},
{
0x02F8U
,
0x001100500C8FFC01UL
},
{
0x0300U
,
0x0000000000000000UL
},
{
0x0308U
,
0x001100300C8FFC01UL
},
{
0x0310U
,
0x001100500C8FFC01UL
},
{
0x0318U
,
0x001200100C803401UL
},
{
0x0320U
,
0x0000000000000000UL
},
{
0x0328U
,
0x0000000000000000UL
},
{
0x0330U
,
0x0000000000000000UL
},
{
0x0338U
,
0x0000000000000000UL
},
{
0x0340U
,
0x0000000000000000UL
},
{
0x0348U
,
0x0000000000000000UL
},
{
0x0350U
,
0x0000000000000000UL
},
};
#endif
static
void
dbsc_setting
(
void
)
{
uint32_t
md
=
0
;
/* BUFCAM settings */
/* DBSC_DBCAM0CNF0 not set */
io_write_32
(
DBSC_DBCAM0CNF1
,
0x00043218
);
/* dbcam0cnf1 */
io_write_32
(
DBSC_DBCAM0CNF2
,
0x000000F4
);
/* dbcam0cnf2 */
io_write_32
(
DBSC_DBCAM0CNF3
,
0x00000000
);
/* dbcam0cnf3 */
io_write_32
(
DBSC_DBSCHCNT0
,
0x080F0037
);
/* dbschcnt0 */
/* DBSC_DBSCHCNT1 not set */
io_write_32
(
DBSC_DBSCHSZ0
,
0x00000001
);
/* dbschsz0 */
io_write_32
(
DBSC_DBSCHRW0
,
0x22421111
);
/* dbschrw0 */
md
=
(
*
((
volatile
uint32_t
*
)
RST_MODEMR
)
&
0x000A0000
)
>>
17
;
switch
(
md
)
{
case
0x0
:
/* DDR3200 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
case
0x1
:
/* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
/* DDR2800 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
case
0x4
:
/* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
/* DDR2400 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
default:
/* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
/* DDR1600 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
}
/* QoS Settings */
io_write_32
(
DBSC_DBSCHQOS_0_0
,
0x00000F00
);
io_write_32
(
DBSC_DBSCHQOS_0_1
,
0x00000B00
);
io_write_32
(
DBSC_DBSCHQOS_0_2
,
0x00000000
);
io_write_32
(
DBSC_DBSCHQOS_0_3
,
0x00000000
);
/* DBSC_DBSCHQOS_1_0 not set */
/* DBSC_DBSCHQOS_1_1 not set */
/* DBSC_DBSCHQOS_1_2 not set */
/* DBSC_DBSCHQOS_1_3 not set */
/* DBSC_DBSCHQOS_2_0 not set */
/* DBSC_DBSCHQOS_2_1 not set */
/* DBSC_DBSCHQOS_2_2 not set */
/* DBSC_DBSCHQOS_2_3 not set */
/* DBSC_DBSCHQOS_3_0 not set */
/* DBSC_DBSCHQOS_3_1 not set */
/* DBSC_DBSCHQOS_3_2 not set */
/* DBSC_DBSCHQOS_3_3 not set */
io_write_32
(
DBSC_DBSCHQOS_4_0
,
0x00000300
);
io_write_32
(
DBSC_DBSCHQOS_4_1
,
0x000002F0
);
io_write_32
(
DBSC_DBSCHQOS_4_2
,
0x00000200
);
io_write_32
(
DBSC_DBSCHQOS_4_3
,
0x00000100
);
/* DBSC_DBSCHQOS_5_0 not set */
/* DBSC_DBSCHQOS_5_1 not set */
/* DBSC_DBSCHQOS_5_2 not set */
/* DBSC_DBSCHQOS_5_3 not set */
/* DBSC_DBSCHQOS_6_0 not set */
/* DBSC_DBSCHQOS_6_1 not set */
/* DBSC_DBSCHQOS_6_2 not set */
/* DBSC_DBSCHQOS_6_3 not set */
/* DBSC_DBSCHQOS_7_0 not set */
/* DBSC_DBSCHQOS_7_1 not set */
/* DBSC_DBSCHQOS_7_2 not set */
/* DBSC_DBSCHQOS_7_3 not set */
/* DBSC_DBSCHQOS_8_0 not set */
/* DBSC_DBSCHQOS_8_1 not set */
/* DBSC_DBSCHQOS_8_2 not set */
/* DBSC_DBSCHQOS_8_3 not set */
io_write_32
(
DBSC_DBSCHQOS_9_0
,
0x00000300
);
io_write_32
(
DBSC_DBSCHQOS_9_1
,
0x000002F0
);
io_write_32
(
DBSC_DBSCHQOS_9_2
,
0x00000200
);
io_write_32
(
DBSC_DBSCHQOS_9_3
,
0x00000100
);
/* DBSC_DBSCHQOS_10_0 not set */
/* DBSC_DBSCHQOS_10_1 not set */
/* DBSC_DBSCHQOS_10_2 not set */
/* DBSC_DBSCHQOS_10_3 not set */
/* DBSC_DBSCHQOS_11_0 not set */
/* DBSC_DBSCHQOS_11_1 not set */
/* DBSC_DBSCHQOS_11_2 not set */
/* DBSC_DBSCHQOS_11_3 not set */
/* DBSC_DBSCHQOS_12_0 not set */
/* DBSC_DBSCHQOS_12_1 not set */
/* DBSC_DBSCHQOS_12_2 not set */
/* DBSC_DBSCHQOS_12_3 not set */
io_write_32
(
DBSC_DBSCHQOS_13_0
,
0x00000100
);
io_write_32
(
DBSC_DBSCHQOS_13_1
,
0x000000F0
);
io_write_32
(
DBSC_DBSCHQOS_13_2
,
0x000000A0
);
io_write_32
(
DBSC_DBSCHQOS_13_3
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS_14_0
,
0x000000C0
);
io_write_32
(
DBSC_DBSCHQOS_14_1
,
0x000000B0
);
io_write_32
(
DBSC_DBSCHQOS_14_2
,
0x00000080
);
io_write_32
(
DBSC_DBSCHQOS_14_3
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS_15_0
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS_15_1
,
0x00000030
);
io_write_32
(
DBSC_DBSCHQOS_15_2
,
0x00000020
);
io_write_32
(
DBSC_DBSCHQOS_15_3
,
0x00000010
);
}
void
qos_init_m3_v10
(
void
)
{
dbsc_setting
();
/* DRAM Split Address mapping */
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
#if RCAR_LSI == RCAR_M3
#error "Don't set DRAM Split 4ch(M3)"
#else
ERROR
(
"DRAM Split 4ch not supported.(M3)"
);
panic
();
#endif
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
NOTICE
(
"BL2: DRAM Split is 2ch
\n
"
);
io_write_32
(
AXI_ADSPLCR0
,
0x00000000U
);
io_write_32
(
AXI_ADSPLCR1
,
ADSPLCR0_ADRMODE_DEFAULT
|
ADSPLCR0_SPLITSEL
(
0xFFU
)
|
ADSPLCR0_AREA
(
0x1CU
)
|
ADSPLCR0_SWP
);
io_write_32
(
AXI_ADSPLCR2
,
0x089A0000U
);
io_write_32
(
AXI_ADSPLCR3
,
0x00000000U
);
#else
NOTICE
(
"BL2: DRAM Split is OFF
\n
"
);
#endif
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
NOTICE
(
"BL2: QoS is default setting(%s)
\n
"
,
RCAR_QOS_VERSION
);
#endif
/* Resource Alloc setting */
io_write_32
(
RALLOC_RAS
,
0x00000028U
);
io_write_32
(
RALLOC_FIXTH
,
0x000F0005U
);
io_write_32
(
RALLOC_REGGD
,
0x00000000U
);
io_write_64
(
RALLOC_DANN
,
0x0101010102020201UL
);
io_write_32
(
RALLOC_DANT
,
0x00100804U
);
io_write_32
(
RALLOC_EC
,
0x00000000U
);
io_write_64
(
RALLOC_EMS
,
0x0000000000000000UL
);
io_write_32
(
RALLOC_FSS
,
0x000003e8U
);
io_write_32
(
RALLOC_INSFC
,
0xC7840001U
);
io_write_32
(
RALLOC_BERR
,
0x00000000U
);
io_write_32
(
RALLOC_RACNT0
,
0x00000000U
);
/* MSTAT setting */
io_write_32
(
MSTAT_SL_INIT
,
SL_INIT_REFFSSLOT
|
SL_INIT_SLOTSSLOT
|
SL_INIT_SSLOTCLK
);
io_write_32
(
MSTAT_REF_ARS
,
0x00330000U
);
/* MSTAT SRAM setting */
{
uint32_t
i
;
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_fix
);
i
++
)
{
io_write_64
(
MSTAT_FIX_QOS_BANK0
+
mstat_fix
[
i
].
addr
,
mstat_fix
[
i
].
value
);
io_write_64
(
MSTAT_FIX_QOS_BANK1
+
mstat_fix
[
i
].
addr
,
mstat_fix
[
i
].
value
);
}
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_be
);
i
++
)
{
io_write_64
(
MSTAT_BE_QOS_BANK0
+
mstat_be
[
i
].
addr
,
mstat_be
[
i
].
value
);
io_write_64
(
MSTAT_BE_QOS_BANK1
+
mstat_be
[
i
].
addr
,
mstat_be
[
i
].
value
);
}
}
/* 3DG bus Leaf setting */
io_write_32
(
0xFD820808U
,
0x00001234U
);
io_write_32
(
0xFD820800U
,
0x00000006U
);
io_write_32
(
0xFD821800U
,
0x00000006U
);
io_write_32
(
0xFD822800U
,
0x00000006U
);
io_write_32
(
0xFD823800U
,
0x00000006U
);
io_write_32
(
0xFD824800U
,
0x00000006U
);
io_write_32
(
0xFD825800U
,
0x00000006U
);
io_write_32
(
0xFD826800U
,
0x00000006U
);
io_write_32
(
0xFD827800U
,
0x00000006U
);
/* RT bus Leaf setting */
io_write_32
(
0xFFC50800U
,
0x00000000U
);
io_write_32
(
0xFFC51800U
,
0x00000000U
);
/* Resource Alloc start */
io_write_32
(
RALLOC_RAEN
,
0x00000001U
);
/* MSTAT start */
io_write_32
(
MSTAT_STATQC
,
0x00000001U
);
#else
NOTICE
(
"BL2: QoS is None
\n
"
);
/* Resource Alloc setting */
io_write_32
(
RALLOC_EC
,
0x00000000U
);
/* Resource Alloc start */
io_write_32
(
RALLOC_RAEN
,
0x00000001U
);
#endif
/* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
}
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef QOS_INIT_H_M3_V10__
#define QOS_INIT_H_M3_V10__
void
qos_init_m3_v10
(
void
);
#endif
/* QOS_INIT_H_M3_V10__ */
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <debug.h>
#include "../qos_common.h"
#include "../qos_reg.h"
#include "qos_init_m3_v11.h"
#define RCAR_QOS_VERSION "rev.0.17"
#define QOSWT_TIME_BANK0 (20000000U)
/* unit:ns */
#define QOSWT_WTEN_ENABLE (0x1U)
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 (SL_INIT_SSLOTCLK_M3_11 - 0x5U)
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
#define WT_BASE_SUB_SLOT_NUM0 (12U)
#define QOSWT_WTSET0_PERIOD0_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
#define QOSWT_WTSET1_PERIOD1_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
#if RCAR_REF_INT == RCAR_REF_DEFAULT
#include "qos_init_m3_v11_mstat195.h"
#else
#include "qos_init_m3_v11_mstat390.h"
#endif
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
#if RCAR_REF_INT == RCAR_REF_DEFAULT
#include "qos_init_m3_v11_qoswt195.h"
#else
#include "qos_init_m3_v11_qoswt390.h"
#endif
#endif
/* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
#endif
static
void
dbsc_setting
(
void
)
{
uint32_t
md
=
0
;
/* BUFCAM settings */
io_write_32
(
DBSC_DBCAM0CNF1
,
0x00043218
);
/* dbcam0cnf1 */
io_write_32
(
DBSC_DBCAM0CNF2
,
0x000000F4
);
/* dbcam0cnf2 */
io_write_32
(
DBSC_DBCAM0CNF3
,
0x00000000
);
/* dbcam0cnf3 */
io_write_32
(
DBSC_DBSCHCNT0
,
0x000F0037
);
/* dbschcnt0 */
io_write_32
(
DBSC_DBSCHSZ0
,
0x00000001
);
/* dbschsz0 */
io_write_32
(
DBSC_DBSCHRW0
,
0x22421111
);
/* dbschrw0 */
md
=
(
*
((
volatile
uint32_t
*
)
RST_MODEMR
)
&
0x000A0000
)
>>
17
;
switch
(
md
)
{
case
0x0
:
/* DDR3200 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
case
0x1
:
/* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
/* DDR2800 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
case
0x4
:
/* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
/* DDR2400 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
default:
/* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
/* DDR1600 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
}
/* QoS Settings */
io_write_32
(
DBSC_DBSCHQOS00
,
0x00000F00
);
io_write_32
(
DBSC_DBSCHQOS01
,
0x00000B00
);
io_write_32
(
DBSC_DBSCHQOS02
,
0x00000000
);
io_write_32
(
DBSC_DBSCHQOS03
,
0x00000000
);
io_write_32
(
DBSC_DBSCHQOS40
,
0x00000300
);
io_write_32
(
DBSC_DBSCHQOS41
,
0x000002F0
);
io_write_32
(
DBSC_DBSCHQOS42
,
0x00000200
);
io_write_32
(
DBSC_DBSCHQOS43
,
0x00000100
);
io_write_32
(
DBSC_DBSCHQOS90
,
0x00000100
);
io_write_32
(
DBSC_DBSCHQOS91
,
0x000000F0
);
io_write_32
(
DBSC_DBSCHQOS92
,
0x000000A0
);
io_write_32
(
DBSC_DBSCHQOS93
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS120
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS121
,
0x00000030
);
io_write_32
(
DBSC_DBSCHQOS122
,
0x00000020
);
io_write_32
(
DBSC_DBSCHQOS123
,
0x00000010
);
io_write_32
(
DBSC_DBSCHQOS130
,
0x00000100
);
io_write_32
(
DBSC_DBSCHQOS131
,
0x000000F0
);
io_write_32
(
DBSC_DBSCHQOS132
,
0x000000A0
);
io_write_32
(
DBSC_DBSCHQOS133
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS140
,
0x000000C0
);
io_write_32
(
DBSC_DBSCHQOS141
,
0x000000B0
);
io_write_32
(
DBSC_DBSCHQOS142
,
0x00000080
);
io_write_32
(
DBSC_DBSCHQOS143
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS150
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS151
,
0x00000030
);
io_write_32
(
DBSC_DBSCHQOS152
,
0x00000020
);
io_write_32
(
DBSC_DBSCHQOS153
,
0x00000010
);
}
void
qos_init_m3_v11
(
void
)
{
dbsc_setting
();
/* DRAM Split Address mapping */
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
#if RCAR_LSI == RCAR_M3
#error "Don't set DRAM Split 4ch(M3)"
#else
ERROR
(
"DRAM Split 4ch not supported.(M3)"
);
panic
();
#endif
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
NOTICE
(
"BL2: DRAM Split is 2ch
\n
"
);
io_write_32
(
AXI_ADSPLCR0
,
0x00000000U
);
io_write_32
(
AXI_ADSPLCR1
,
ADSPLCR0_ADRMODE_DEFAULT
|
ADSPLCR0_SPLITSEL
(
0xFFU
)
|
ADSPLCR0_AREA
(
0x1CU
)
|
ADSPLCR0_SWP
);
io_write_32
(
AXI_ADSPLCR2
,
0x00001004U
);
io_write_32
(
AXI_ADSPLCR3
,
0x00000000U
);
#else
NOTICE
(
"BL2: DRAM Split is OFF
\n
"
);
#endif
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
NOTICE
(
"BL2: QoS is default setting(%s)
\n
"
,
RCAR_QOS_VERSION
);
#endif
#if RCAR_REF_INT == RCAR_REF_DEFAULT
NOTICE
(
"BL2: DRAM refresh interval 1.95 usec
\n
"
);
#else
NOTICE
(
"BL2: DRAM refresh interval 3.9 usec
\n
"
);
#endif
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
NOTICE
(
"BL2: Periodic Write DQ Training
\n
"
);
#endif
/* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
io_write_32
(
QOSCTRL_RAS
,
0x00000044U
);
io_write_64
(
QOSCTRL_DANN
,
0x0404020002020201UL
);
io_write_32
(
QOSCTRL_DANT
,
0x0020100AU
);
io_write_32
(
QOSCTRL_INSFC
,
0x06330001U
);
io_write_32
(
QOSCTRL_RACNT0
,
0x02010003U
);
/* GPU Boost Mode ON */
io_write_32
(
QOSCTRL_SL_INIT
,
SL_INIT_REFFSSLOT
|
SL_INIT_SLOTSSLOT
|
SL_INIT_SSLOTCLK_M3_11
);
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
io_write_32
(
QOSCTRL_REF_ARS
,
((
QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11
<<
16
)));
#else
io_write_32
(
QOSCTRL_REF_ARS
,
0x00330000U
);
#endif
/* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
{
uint32_t
i
;
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_fix
);
i
++
)
{
io_write_64
(
QOSBW_FIX_QOS_BANK0
+
i
*
8
,
mstat_fix
[
i
]);
io_write_64
(
QOSBW_FIX_QOS_BANK1
+
i
*
8
,
mstat_fix
[
i
]);
}
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_be
);
i
++
)
{
io_write_64
(
QOSBW_BE_QOS_BANK0
+
i
*
8
,
mstat_be
[
i
]);
io_write_64
(
QOSBW_BE_QOS_BANK1
+
i
*
8
,
mstat_be
[
i
]);
}
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
qoswt_fix
);
i
++
)
{
io_write_64
(
QOSWT_FIX_WTQOS_BANK0
+
i
*
8
,
qoswt_fix
[
i
]);
io_write_64
(
QOSWT_FIX_WTQOS_BANK1
+
i
*
8
,
qoswt_fix
[
i
]);
}
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
qoswt_be
);
i
++
)
{
io_write_64
(
QOSWT_BE_WTQOS_BANK0
+
i
*
8
,
qoswt_be
[
i
]);
io_write_64
(
QOSWT_BE_WTQOS_BANK1
+
i
*
8
,
qoswt_be
[
i
]);
}
#endif
/* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
}
/* 3DG bus Leaf setting */
io_write_32
(
GPU_ACT_GRD
,
0x00001234U
);
io_write_32
(
GPU_ACT0
,
0x00000000U
);
io_write_32
(
GPU_ACT1
,
0x00000000U
);
io_write_32
(
GPU_ACT2
,
0x00000000U
);
io_write_32
(
GPU_ACT3
,
0x00000000U
);
/* RT bus Leaf setting */
io_write_32
(
RT_ACT0
,
0x00000000U
);
io_write_32
(
RT_ACT1
,
0x00000000U
);
/* CCI bus Leaf setting */
io_write_32
(
CPU_ACT0
,
0x00000003U
);
io_write_32
(
CPU_ACT1
,
0x00000003U
);
io_write_32
(
CPU_ACT2
,
0x00000003U
);
io_write_32
(
CPU_ACT3
,
0x00000003U
);
io_write_32
(
QOSCTRL_RAEN
,
0x00000001U
);
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
/* re-write training setting */
io_write_32
(
QOSWT_WTREF
,
((
QOSWT_WTREF_SLOT1_EN
<<
16
)
|
QOSWT_WTREF_SLOT0_EN
));
io_write_32
(
QOSWT_WTSET0
,
((
QOSWT_WTSET0_PERIOD0_M3_11
<<
16
)
|
(
QOSWT_WTSET0_SSLOT0
<<
8
)
|
QOSWT_WTSET0_SLOTSLOT0
));
io_write_32
(
QOSWT_WTSET1
,
((
QOSWT_WTSET1_PERIOD1_M3_11
<<
16
)
|
(
QOSWT_WTSET1_SSLOT1
<<
8
)
|
QOSWT_WTSET1_SLOTSLOT1
));
io_write_32
(
QOSWT_WTEN
,
QOSWT_WTEN_ENABLE
);
#endif
/* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
io_write_32
(
QOSCTRL_STATQC
,
0x00000001U
);
#else
NOTICE
(
"BL2: QoS is None
\n
"
);
io_write_32
(
QOSCTRL_RAEN
,
0x00000001U
);
#endif
/* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
}
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef QOS_INIT_H_M3_V11__
#define QOS_INIT_H_M3_V11__
void
qos_init_m3_v11
(
void
);
#endif
/* QOS_INIT_H_M3_V11__ */
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat195.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
static
uint64_t
mstat_fix
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x001004040000FFFFUL
,
/* 0x0038, */
0x001004040000FFFFUL
,
/* 0x0040, */
0x001414090000FFFFUL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x001404010000FFFFUL
,
/* 0x0058, */
0x00140C0A0000FFFFUL
,
/* 0x0060, */
0x00140C0A0000FFFFUL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x001404010000FFFFUL
,
/* 0x0078, */
0x001004030000FFFFUL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x001414090000FFFFUL
,
/* 0x0090, */
0x001408070000FFFFUL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x000C04020000FFFFUL
,
/* 0x00a8, */
0x000C04010000FFFFUL
,
/* 0x00b0, */
0x000C04010000FFFFUL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x000C04020000FFFFUL
,
/* 0x00c8, */
0x000C04010000FFFFUL
,
/* 0x00d0, */
0x000C04010000FFFFUL
,
/* 0x00d8, */
0x000C08050000FFFFUL
,
/* 0x00e0, */
0x000C14120000FFFFUL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x001024090000FFFFUL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x00100C090000FFFFUL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x00100C0B0000FFFFUL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0010100D0000FFFFUL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x00100C0B0000FFFFUL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x001008060000FFFFUL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x00102C2C0000FFFFUL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x00100C0B0000FFFFUL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x000C04010000FFFFUL
,
/* 0x01c8, */
0x000C04010000FFFFUL
,
/* 0x01d0, */
0x000C04010000FFFFUL
,
/* 0x01d8, */
0x000C04010000FFFFUL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x000C04010000FFFFUL
,
/* 0x01f0, */
0x000C04010000FFFFUL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x000C04010000FFFFUL
,
/* 0x0210, */
0x000C04010000FFFFUL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x000C08020000FFFFUL
,
/* 0x0268, */
0x001408010000FFFFUL
,
/* 0x0270, */
0x001404010000FFFFUL
,
/* 0x0278, */
0x000C04010000FFFFUL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x001408010000FFFFUL
,
/* 0x0298, */
0x001404010000FFFFUL
,
/* 0x02a0, */
0x000C04010000FFFFUL
,
/* 0x02a8, */
0x000C04010000FFFFUL
,
/* 0x02b0, */
0x001408010000FFFFUL
,
/* 0x02b8, */
0x000C04010000FFFFUL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x000C04010000FFFFUL
,
/* 0x02d8, */
0x000C04010000FFFFUL
,
/* 0x02e0, */
0x001408010000FFFFUL
,
/* 0x02e8, */
0x000C04010000FFFFUL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
};
static
uint64_t
mstat_be
[]
=
{
/* 0x0000, */
0x001200200BDFFC01UL
,
/* 0x0008, */
0x001200200BDFFC01UL
,
/* 0x0010, */
0x001200200BDFFC01UL
,
/* 0x0018, */
0x001200200BDFFC01UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x001200100BD03401UL
,
/* 0x0030, */
0x0000000000000000UL
,
/* 0x0038, */
0x0000000000000000UL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x0000000000000000UL
,
/* 0x0060, */
0x0000000000000000UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0000000000000000UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x002100600BDFFC01UL
,
/* 0x01c8, */
0x002100600BDFFC01UL
,
/* 0x01d0, */
0x002100600BDFFC01UL
,
/* 0x01d8, */
0x002100600BDFFC01UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x002100200BDFFC01UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x002100200BDFFC01UL
,
/* 0x0218, */
0x001100200BDFFC01UL
,
/* 0x0220, */
0x001100200BDFFC01UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x001100200BDFFC01UL
,
/* 0x0238, */
0x001100200BDFFC01UL
,
/* 0x0240, */
0x001200200BDFFC01UL
,
/* 0x0248, */
0x001100200BDFFC01UL
,
/* 0x0250, */
0x001200200BDFFC01UL
,
/* 0x0258, */
0x001100200BDFFC01UL
,
/* 0x0260, */
0x0000000000000000UL
,
/* 0x0268, */
0x0000000000000000UL
,
/* 0x0270, */
0x0000000000000000UL
,
/* 0x0278, */
0x0000000000000000UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x0000000000000000UL
,
/* 0x0298, */
0x0000000000000000UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x001100400BDFFC01UL
,
/* 0x02f8, */
0x001100600BDFFC01UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x001100400BDFFC01UL
,
/* 0x0310, */
0x001100600BDFFC01UL
,
/* 0x0318, */
0x001200100BD03401UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
};
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat390.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
static
uint64_t
mstat_fix
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x001008070000FFFFUL
,
/* 0x0038, */
0x001008070000FFFFUL
,
/* 0x0040, */
0x001424120000FFFFUL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x001404010000FFFFUL
,
/* 0x0058, */
0x001414130000FFFFUL
,
/* 0x0060, */
0x001414130000FFFFUL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x001404010000FFFFUL
,
/* 0x0078, */
0x001008050000FFFFUL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x001424120000FFFFUL
,
/* 0x0090, */
0x0014100D0000FFFFUL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x000C08040000FFFFUL
,
/* 0x00a8, */
0x000C04020000FFFFUL
,
/* 0x00b0, */
0x000C04020000FFFFUL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x000C08040000FFFFUL
,
/* 0x00c8, */
0x000C04020000FFFFUL
,
/* 0x00d0, */
0x000C04020000FFFFUL
,
/* 0x00d8, */
0x000C0C0A0000FFFFUL
,
/* 0x00e0, */
0x000C24230000FFFFUL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x001044110000FFFFUL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x001014110000FFFFUL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x001018150000FFFFUL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x00101C190000FFFFUL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x001018150000FFFFUL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x00100C0B0000FFFFUL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x001058570000FFFFUL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x001018150000FFFFUL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x000C04010000FFFFUL
,
/* 0x01c8, */
0x000C04010000FFFFUL
,
/* 0x01d0, */
0x000C04010000FFFFUL
,
/* 0x01d8, */
0x000C04010000FFFFUL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x000C04010000FFFFUL
,
/* 0x01f0, */
0x000C04010000FFFFUL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x000C04010000FFFFUL
,
/* 0x0210, */
0x000C04010000FFFFUL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x000C0C030000FFFFUL
,
/* 0x0268, */
0x001410010000FFFFUL
,
/* 0x0270, */
0x001404010000FFFFUL
,
/* 0x0278, */
0x000C08020000FFFFUL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x001410010000FFFFUL
,
/* 0x0298, */
0x001404010000FFFFUL
,
/* 0x02a0, */
0x000C04010000FFFFUL
,
/* 0x02a8, */
0x000C04010000FFFFUL
,
/* 0x02b0, */
0x00140C010000FFFFUL
,
/* 0x02b8, */
0x000C04010000FFFFUL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x000C04010000FFFFUL
,
/* 0x02d8, */
0x000C04010000FFFFUL
,
/* 0x02e0, */
0x00140C010000FFFFUL
,
/* 0x02e8, */
0x000C04010000FFFFUL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
};
static
uint64_t
mstat_be
[]
=
{
/* 0x0000, */
0x0012003005EFFC01UL
,
/* 0x0008, */
0x0012003005EFFC01UL
,
/* 0x0010, */
0x0012003005EFFC01UL
,
/* 0x0018, */
0x0012003005EFFC01UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0012001005E03401UL
,
/* 0x0030, */
0x0000000000000000UL
,
/* 0x0038, */
0x0000000000000000UL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x0000000000000000UL
,
/* 0x0060, */
0x0000000000000000UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0000000000000000UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x002100B005EFFC01UL
,
/* 0x01c8, */
0x002100B005EFFC01UL
,
/* 0x01d0, */
0x002100B005EFFC01UL
,
/* 0x01d8, */
0x002100B005EFFC01UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0021003005EFFC01UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0021003005EFFC01UL
,
/* 0x0218, */
0x0011003005EFFC01UL
,
/* 0x0220, */
0x0011003005EFFC01UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0011003005EFFC01UL
,
/* 0x0238, */
0x0011003005EFFC01UL
,
/* 0x0240, */
0x0012003005EFFC01UL
,
/* 0x0248, */
0x0011003005EFFC01UL
,
/* 0x0250, */
0x0012003005EFFC01UL
,
/* 0x0258, */
0x0011003005EFFC01UL
,
/* 0x0260, */
0x0000000000000000UL
,
/* 0x0268, */
0x0000000000000000UL
,
/* 0x0270, */
0x0000000000000000UL
,
/* 0x0278, */
0x0000000000000000UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x0000000000000000UL
,
/* 0x0298, */
0x0000000000000000UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0011007005EFFC01UL
,
/* 0x02f8, */
0x001100B005EFFC01UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0011007005EFFC01UL
,
/* 0x0310, */
0x001100B005EFFC01UL
,
/* 0x0318, */
0x0012001005E03401UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
};
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt195.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
static
uint64_t
qoswt_fix
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x001004040000C010UL
,
/* 0x0038, */
0x001004040000C010UL
,
/* 0x0040, */
0x001414090000FFF0UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x00140C0A0000C010UL
,
/* 0x0060, */
0x00140C0A0000C010UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x001004030000C010UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x001414090000FFF0UL
,
/* 0x0090, */
0x001408070000C010UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x0000000000000000UL
,
/* 0x01c8, */
0x0000000000000000UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0000000000000000UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0000000000000000UL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x000C08020000FFF0UL
,
/* 0x0268, */
0x001408010000FFF0UL
,
/* 0x0270, */
0x001404010000FFF0UL
,
/* 0x0278, */
0x000C04010000FFF0UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x001408010000FFF0UL
,
/* 0x0298, */
0x001404010000FFF0UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
};
static
uint64_t
qoswt_be
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x0000000000000000UL
,
/* 0x0038, */
0x0000000000000000UL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x0000000000000000UL
,
/* 0x0060, */
0x0000000000000000UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0000000000000000UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x0000000000000000UL
,
/* 0x01c8, */
0x0000000000000000UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0000000000000000UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0000000000000000UL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x0000000000000000UL
,
/* 0x0268, */
0x0000000000000000UL
,
/* 0x0270, */
0x0000000000000000UL
,
/* 0x0278, */
0x0000000000000000UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x0000000000000000UL
,
/* 0x0298, */
0x0000000000000000UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
};
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt390.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
static
uint64_t
qoswt_fix
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x001008070000C010UL
,
/* 0x0038, */
0x001008070000C010UL
,
/* 0x0040, */
0x001424120000FFF0UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x001414130000C010UL
,
/* 0x0060, */
0x001414130000C010UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x001008050000C010UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x001424120000FFF0UL
,
/* 0x0090, */
0x0014100D0000C010UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x0000000000000000UL
,
/* 0x01c8, */
0x0000000000000000UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0000000000000000UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0000000000000000UL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x000C0C030000FFF0UL
,
/* 0x0268, */
0x001410010000FFF0UL
,
/* 0x0270, */
0x001404010000FFF0UL
,
/* 0x0278, */
0x000C08020000FFF0UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x001410010000FFF0UL
,
/* 0x0298, */
0x001404010000FFF0UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
};
static
uint64_t
qoswt_be
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x0000000000000000UL
,
/* 0x0038, */
0x0000000000000000UL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x0000000000000000UL
,
/* 0x0060, */
0x0000000000000000UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0000000000000000UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x0000000000000000UL
,
/* 0x01c8, */
0x0000000000000000UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0000000000000000UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0000000000000000UL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x0000000000000000UL
,
/* 0x0268, */
0x0000000000000000UL
,
/* 0x0270, */
0x0000000000000000UL
,
/* 0x0278, */
0x0000000000000000UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x0000000000000000UL
,
/* 0x0298, */
0x0000000000000000UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
};
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <debug.h>
#include "../qos_common.h"
#include "../qos_reg.h"
#include "qos_init_m3n_v10.h"
#define RCAR_QOS_VERSION "rev.0.06"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
#define REF_ARS_ARBSTOPCYCLE_M3N (((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
#define QOSWT_TIME_BANK0 (20000000U)
/* unit:ns */
#define QOSWT_WTEN_ENABLE (0x1U)
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTREF_SLOT1_EN QOSWT_WTREF_SLOT0_EN
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
#define WT_BASE_SUB_SLOT_NUM0 (12U)
#define QOSWT_WTSET0_PERIOD0_M3N ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3N)-1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
#define QOSWT_WTSET1_PERIOD1_M3N QOSWT_WTSET0_PERIOD0_M3N
#define QOSWT_WTSET1_SSLOT1 QOSWT_WTSET0_SSLOT0
#define QOSWT_WTSET1_SLOTSLOT1 QOSWT_WTSET0_SLOTSLOT0
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
#if RCAR_REF_INT == RCAR_REF_DEFAULT
#include "qos_init_m3n_v10_mstat195.h"
#else
#include "qos_init_m3n_v10_mstat390.h"
#endif
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
#if RCAR_REF_INT == RCAR_REF_DEFAULT
#include "qos_init_m3n_v10_qoswt195.h"
#else
#include "qos_init_m3n_v10_qoswt390.h"
#endif
#endif
/* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
#endif
static
void
dbsc_setting
(
void
)
{
uint32_t
md
=
0
;
/* Register write enable */
io_write_32
(
DBSC_DBSYSCNT0
,
0x00001234U
);
/* BUFCAM settings */
io_write_32
(
DBSC_DBCAM0CNF1
,
0x00043218
);
/* dbcam0cnf1 */
io_write_32
(
DBSC_DBCAM0CNF2
,
0x000000F4
);
/* dbcam0cnf2 */
io_write_32
(
DBSC_DBSCHCNT0
,
0x000F0037
);
/* dbschcnt0 */
io_write_32
(
DBSC_DBSCHSZ0
,
0x00000001
);
/* dbschsz0 */
io_write_32
(
DBSC_DBSCHRW0
,
0x22421111
);
/* dbschrw0 */
md
=
(
*
((
volatile
uint32_t
*
)
RST_MODEMR
)
&
0x000A0000
)
>>
17
;
switch
(
md
)
{
case
0x0
:
/* DDR3200 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
case
0x1
:
/* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
/* DDR2800 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
case
0x4
:
/* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
/* DDR2400 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
default:
/* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
/* DDR1600 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
}
/* QoS Settings */
io_write_32
(
DBSC_DBSCHQOS00
,
0x00000F00
);
io_write_32
(
DBSC_DBSCHQOS01
,
0x00000B00
);
io_write_32
(
DBSC_DBSCHQOS02
,
0x00000000
);
io_write_32
(
DBSC_DBSCHQOS03
,
0x00000000
);
io_write_32
(
DBSC_DBSCHQOS40
,
0x00000300
);
io_write_32
(
DBSC_DBSCHQOS41
,
0x000002F0
);
io_write_32
(
DBSC_DBSCHQOS42
,
0x00000200
);
io_write_32
(
DBSC_DBSCHQOS43
,
0x00000100
);
io_write_32
(
DBSC_DBSCHQOS90
,
0x00000100
);
io_write_32
(
DBSC_DBSCHQOS91
,
0x000000F0
);
io_write_32
(
DBSC_DBSCHQOS92
,
0x000000A0
);
io_write_32
(
DBSC_DBSCHQOS93
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS130
,
0x00000100
);
io_write_32
(
DBSC_DBSCHQOS131
,
0x000000F0
);
io_write_32
(
DBSC_DBSCHQOS132
,
0x000000A0
);
io_write_32
(
DBSC_DBSCHQOS133
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS140
,
0x000000C0
);
io_write_32
(
DBSC_DBSCHQOS141
,
0x000000B0
);
io_write_32
(
DBSC_DBSCHQOS142
,
0x00000080
);
io_write_32
(
DBSC_DBSCHQOS143
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS150
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS151
,
0x00000030
);
io_write_32
(
DBSC_DBSCHQOS152
,
0x00000020
);
io_write_32
(
DBSC_DBSCHQOS153
,
0x00000010
);
/* Register write protect */
io_write_32
(
DBSC_DBSYSCNT0
,
0x00000000U
);
}
void
qos_init_m3n_v10
(
void
)
{
dbsc_setting
();
/* DRAM Split Address mapping */
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
#if RCAR_LSI == RCAR_M3N
#error "Don't set DRAM Split 4ch(M3N)"
#else
ERROR
(
"DRAM Split 4ch not supported.(M3N)"
);
panic
();
#endif
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
#if RCAR_LSI == RCAR_M3N
#error "Don't set DRAM Split 2ch(M3N)"
#else
ERROR
(
"DRAM Split 2ch not supported.(M3N)"
);
panic
();
#endif
#else
NOTICE
(
"BL2: DRAM Split is OFF
\n
"
);
#endif
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
NOTICE
(
"BL2: QoS is default setting(%s)
\n
"
,
RCAR_QOS_VERSION
);
#endif
#if RCAR_REF_INT == RCAR_REF_DEFAULT
NOTICE
(
"BL2: DRAM refresh interval 1.95 usec
\n
"
);
#else
NOTICE
(
"BL2: DRAM refresh interval 3.9 usec
\n
"
);
#endif
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
NOTICE
(
"BL2: Periodic Write DQ Training
\n
"
);
#endif
/* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
io_write_32
(
QOSCTRL_RAS
,
0x00000028U
);
io_write_64
(
QOSCTRL_DANN
,
0x0402000002020201UL
);
io_write_32
(
QOSCTRL_DANT
,
0x00100804U
);
io_write_32
(
QOSCTRL_FSS
,
0x0000000AU
);
io_write_32
(
QOSCTRL_INSFC
,
0x06330001U
);
io_write_32
(
QOSCTRL_EARLYR
,
0x00000001U
);
io_write_32
(
QOSCTRL_RACNT0
,
0x00010003U
);
io_write_32
(
QOSCTRL_SL_INIT
,
SL_INIT_REFFSSLOT
|
SL_INIT_SLOTSSLOT
|
SL_INIT_SSLOTCLK_M3N
);
io_write_32
(
QOSCTRL_REF_ARS
,
REF_ARS_ARBSTOPCYCLE_M3N
);
{
uint32_t
i
;
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_fix
);
i
++
)
{
io_write_64
(
QOSBW_FIX_QOS_BANK0
+
i
*
8
,
mstat_fix
[
i
]);
io_write_64
(
QOSBW_FIX_QOS_BANK1
+
i
*
8
,
mstat_fix
[
i
]);
}
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_be
);
i
++
)
{
io_write_64
(
QOSBW_BE_QOS_BANK0
+
i
*
8
,
mstat_be
[
i
]);
io_write_64
(
QOSBW_BE_QOS_BANK1
+
i
*
8
,
mstat_be
[
i
]);
}
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
qoswt_fix
);
i
++
)
{
io_write_64
(
QOSWT_FIX_WTQOS_BANK0
+
i
*
8
,
qoswt_fix
[
i
]);
io_write_64
(
QOSWT_FIX_WTQOS_BANK1
+
i
*
8
,
qoswt_fix
[
i
]);
}
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
qoswt_be
);
i
++
)
{
io_write_64
(
QOSWT_BE_WTQOS_BANK0
+
i
*
8
,
qoswt_be
[
i
]);
io_write_64
(
QOSWT_BE_WTQOS_BANK1
+
i
*
8
,
qoswt_be
[
i
]);
}
#endif
/* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
}
/* 3DG bus Leaf setting */
io_write_32
(
GPU_ACT_GRD
,
0x00001234U
);
io_write_32
(
GPU_ACT0
,
0x00000000U
);
io_write_32
(
GPU_ACT1
,
0x00000000U
);
io_write_32
(
GPU_ACT2
,
0x00000000U
);
io_write_32
(
GPU_ACT3
,
0x00000000U
);
io_write_32
(
GPU_ACT_GRD
,
0x00000000U
);
/* RT bus Leaf setting */
io_write_32
(
RT_ACT0
,
0x00000000U
);
io_write_32
(
RT_ACT1
,
0x00000000U
);
/* CCI bus Leaf setting */
io_write_32
(
CPU_ACT0
,
0x00000003U
);
io_write_32
(
CPU_ACT1
,
0x00000003U
);
io_write_32
(
QOSCTRL_RAEN
,
0x00000001U
);
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
/* re-write training setting */
io_write_32
(
QOSWT_WTREF
,
((
QOSWT_WTREF_SLOT1_EN
<<
16
)
|
QOSWT_WTREF_SLOT0_EN
));
io_write_32
(
QOSWT_WTSET0
,
((
QOSWT_WTSET0_PERIOD0_M3N
<<
16
)
|
(
QOSWT_WTSET0_SSLOT0
<<
8
)
|
QOSWT_WTSET0_SLOTSLOT0
));
io_write_32
(
QOSWT_WTSET1
,
((
QOSWT_WTSET1_PERIOD1_M3N
<<
16
)
|
(
QOSWT_WTSET1_SSLOT1
<<
8
)
|
QOSWT_WTSET1_SLOTSLOT1
));
io_write_32
(
QOSWT_WTEN
,
QOSWT_WTEN_ENABLE
);
#endif
/* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
io_write_32
(
QOSCTRL_STATQC
,
0x00000001U
);
#else
NOTICE
(
"BL2: QoS is None
\n
"
);
io_write_32
(
QOSCTRL_RAEN
,
0x00000001U
);
#endif
/* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
}
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef QOS_INIT_H_M3N_V10__
#define QOS_INIT_H_M3N_V10__
void
qos_init_m3n_v10
(
void
);
#endif
/* QOS_INIT_H_M3N_V10__ */
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
static
uint64_t
mstat_fix
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x001004320000FFFFUL
,
/* 0x0038, */
0x001004320000FFFFUL
,
/* 0x0040, */
0x00140C5D0000FFFFUL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x001404040000FFFFUL
,
/* 0x0058, */
0x00140C940000FFFFUL
,
/* 0x0060, */
0x00140C940000FFFFUL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x001404040000FFFFUL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0014041F0000FFFFUL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x000C041D0000FFFFUL
,
/* 0x00a8, */
0x000C04090000FFFFUL
,
/* 0x00b0, */
0x000C04090000FFFFUL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x000C041D0000FFFFUL
,
/* 0x00c8, */
0x000C04090000FFFFUL
,
/* 0x00d0, */
0x000C04090000FFFFUL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x001024840000FFFFUL
,
/* 0x00f8, */
0x000C084F0000FFFFUL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x00100C840000FFFFUL
,
/* 0x0118, */
0x000C21E60000FFFFUL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x00100CA50000FFFFUL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x001010C90000FFFFUL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x00100CA50000FFFFUL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x001008530000FFFFUL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x00101D9D0000FFFFUL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x00100CA50000FFFFUL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x000C04010000FFFFUL
,
/* 0x01c8, */
0x000C04010000FFFFUL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x000C04010000FFFFUL
,
/* 0x01f0, */
0x000C04050000FFFFUL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x000C04050000FFFFUL
,
/* 0x0210, */
0x000C04050000FFFFUL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x000C08150000FFFFUL
,
/* 0x0268, */
0x001408020000FFFFUL
,
/* 0x0270, */
0x001404010000FFFFUL
,
/* 0x0278, */
0x000C04090000FFFFUL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x001408020000FFFFUL
,
/* 0x0298, */
0x001404010000FFFFUL
,
/* 0x02a0, */
0x000C04050000FFFFUL
,
/* 0x02a8, */
0x000C04050000FFFFUL
,
/* 0x02b0, */
0x001408050000FFFFUL
,
/* 0x02b8, */
0x000C04010000FFFFUL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x000C04050000FFFFUL
,
/* 0x02d8, */
0x000C04050000FFFFUL
,
/* 0x02e0, */
0x001408050000FFFFUL
,
/* 0x02e8, */
0x000C04010000FFFFUL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x0000000000000000UL
,
/* 0x0360, */
0x0000000000000000UL
,
/* 0x0368, */
0x0000000000000000UL
,
/* 0x0370, */
0x000C04010000FFFFUL
,
/* 0x0378, */
0x000C04010000FFFFUL
,
/* 0x0380, */
0x000C04050000FFFFUL
,
/* 0x0388, */
0x000C04050000FFFFUL
,
/* 0x0390, */
0x0000000000000000UL
,
};
static
uint64_t
mstat_be
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x001200100BD03401UL
,
/* 0x0030, */
0x0000000000000000UL
,
/* 0x0038, */
0x0000000000000000UL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x0000000000000000UL
,
/* 0x0060, */
0x0000000000000000UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0000000000000000UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x002106000BDFFC01UL
,
/* 0x01c8, */
0x002106000BDFFC01UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x002101000BDF2401UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x002101000BDF2401UL
,
/* 0x0218, */
0x001101000BDF2401UL
,
/* 0x0220, */
0x001101000BDF2401UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x001101000BDF2401UL
,
/* 0x0238, */
0x001101000BDF2401UL
,
/* 0x0240, */
0x001201000BDF2401UL
,
/* 0x0248, */
0x001101000BDF2401UL
,
/* 0x0250, */
0x001201000BDF2401UL
,
/* 0x0258, */
0x001101000BDF2401UL
,
/* 0x0260, */
0x0000000000000000UL
,
/* 0x0268, */
0x0000000000000000UL
,
/* 0x0270, */
0x0000000000000000UL
,
/* 0x0278, */
0x0000000000000000UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x0000000000000000UL
,
/* 0x0298, */
0x0000000000000000UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x001106000BDFFC01UL
,
/* 0x02f8, */
0x001106000BDFFC01UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x001200100BD03401UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x001206000BDFFC01UL
,
/* 0x0360, */
0x001206000BDFFC01UL
,
/* 0x0368, */
0x001200100BD03401UL
,
/* 0x0370, */
0x0000000000000000UL
,
/* 0x0378, */
0x0000000000000000UL
,
/* 0x0380, */
0x0000000000000000UL
,
/* 0x0388, */
0x0000000000000000UL
,
/* 0x0390, */
0x001200100BD03401UL
,
};
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
static
uint64_t
mstat_fix
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x001008630000FFFFUL
,
/* 0x0038, */
0x001008630000FFFFUL
,
/* 0x0040, */
0x001418BA0000FFFFUL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x001404070000FFFFUL
,
/* 0x0058, */
0x001415270000FFFFUL
,
/* 0x0060, */
0x001415270000FFFFUL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x001404070000FFFFUL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0014083E0000FFFFUL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x000C08390000FFFFUL
,
/* 0x00a8, */
0x000C04110000FFFFUL
,
/* 0x00b0, */
0x000C04110000FFFFUL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x000C08390000FFFFUL
,
/* 0x00c8, */
0x000C04110000FFFFUL
,
/* 0x00d0, */
0x000C04110000FFFFUL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x001045080000FFFFUL
,
/* 0x00f8, */
0x000C0C9E0000FFFFUL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x001015080000FFFFUL
,
/* 0x0118, */
0x000C43CB0000FFFFUL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0010194A0000FFFFUL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x00101D910000FFFFUL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0010194A0000FFFFUL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x00100CA50000FFFFUL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x001037390000FFFFUL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0010194A0000FFFFUL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x000C04010000FFFFUL
,
/* 0x01c8, */
0x000C04010000FFFFUL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x000C04020000FFFFUL
,
/* 0x01f0, */
0x000C04090000FFFFUL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x000C04090000FFFFUL
,
/* 0x0210, */
0x000C04090000FFFFUL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x000C0C2A0000FFFFUL
,
/* 0x0268, */
0x001410040000FFFFUL
,
/* 0x0270, */
0x001404020000FFFFUL
,
/* 0x0278, */
0x000C08110000FFFFUL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x001410040000FFFFUL
,
/* 0x0298, */
0x001404020000FFFFUL
,
/* 0x02a0, */
0x000C04090000FFFFUL
,
/* 0x02a8, */
0x000C04090000FFFFUL
,
/* 0x02b0, */
0x00140C090000FFFFUL
,
/* 0x02b8, */
0x000C04020000FFFFUL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x000C04090000FFFFUL
,
/* 0x02d8, */
0x000C04090000FFFFUL
,
/* 0x02e0, */
0x00140C090000FFFFUL
,
/* 0x02e8, */
0x000C04020000FFFFUL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x0000000000000000UL
,
/* 0x0360, */
0x0000000000000000UL
,
/* 0x0368, */
0x0000000000000000UL
,
/* 0x0370, */
0x000C04020000FFFFUL
,
/* 0x0378, */
0x000C04020000FFFFUL
,
/* 0x0380, */
0x000C04090000FFFFUL
,
/* 0x0388, */
0x000C04090000FFFFUL
,
/* 0x0390, */
0x0000000000000000UL
,
};
static
uint64_t
mstat_be
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0012001005E03401UL
,
/* 0x0030, */
0x0000000000000000UL
,
/* 0x0038, */
0x0000000000000000UL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x0000000000000000UL
,
/* 0x0060, */
0x0000000000000000UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0000000000000000UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x0021060005EFFC01UL
,
/* 0x01c8, */
0x0021060005EFFC01UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0021010005E79401UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0021010005E79401UL
,
/* 0x0218, */
0x0011010005E79401UL
,
/* 0x0220, */
0x0011010005E79401UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0011010005E79401UL
,
/* 0x0238, */
0x0011010005E79401UL
,
/* 0x0240, */
0x0012010005E79401UL
,
/* 0x0248, */
0x0011010005E79401UL
,
/* 0x0250, */
0x0012010005E79401UL
,
/* 0x0258, */
0x0011010005E79401UL
,
/* 0x0260, */
0x0000000000000000UL
,
/* 0x0268, */
0x0000000000000000UL
,
/* 0x0270, */
0x0000000000000000UL
,
/* 0x0278, */
0x0000000000000000UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x0000000000000000UL
,
/* 0x0298, */
0x0000000000000000UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0011060005EFFC01UL
,
/* 0x02f8, */
0x0011060005EFFC01UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0012001005E03401UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x0012060005EFFC01UL
,
/* 0x0360, */
0x0012060005EFFC01UL
,
/* 0x0368, */
0x0012001005E03401UL
,
/* 0x0370, */
0x0000000000000000UL
,
/* 0x0378, */
0x0000000000000000UL
,
/* 0x0380, */
0x0000000000000000UL
,
/* 0x0388, */
0x0000000000000000UL
,
/* 0x0390, */
0x0012001005E03401UL
,
};
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt195.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
static
uint64_t
qoswt_fix
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x001004320000C010UL
,
/* 0x0038, */
0x001004320000C010UL
,
/* 0x0040, */
0x00140C5D0000FFF0UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x00140C940000C010UL
,
/* 0x0060, */
0x00140C940000C010UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0014041F0000FFF0UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x0000000000000000UL
,
/* 0x01c8, */
0x0000000000000000UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0000000000000000UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0000000000000000UL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x000C08150000FFF0UL
,
/* 0x0268, */
0x001408020000FFF0UL
,
/* 0x0270, */
0x001404010000FFF0UL
,
/* 0x0278, */
0x000C04090000FFF0UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x001408020000FFF0UL
,
/* 0x0298, */
0x001404010000FFF0UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x0000000000000000UL
,
/* 0x0360, */
0x0000000000000000UL
,
/* 0x0368, */
0x0000000000000000UL
,
/* 0x0370, */
0x0000000000000000UL
,
/* 0x0378, */
0x0000000000000000UL
,
/* 0x0380, */
0x0000000000000000UL
,
/* 0x0388, */
0x0000000000000000UL
,
/* 0x0390, */
0x0000000000000000UL
,
};
static
uint64_t
qoswt_be
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x0000000000000000UL
,
/* 0x0038, */
0x0000000000000000UL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x0000000000000000UL
,
/* 0x0060, */
0x0000000000000000UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0000000000000000UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x0000000000000000UL
,
/* 0x01c8, */
0x0000000000000000UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0000000000000000UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0000000000000000UL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x0000000000000000UL
,
/* 0x0268, */
0x0000000000000000UL
,
/* 0x0270, */
0x0000000000000000UL
,
/* 0x0278, */
0x0000000000000000UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x0000000000000000UL
,
/* 0x0298, */
0x0000000000000000UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x0000000000000000UL
,
/* 0x0360, */
0x0000000000000000UL
,
/* 0x0368, */
0x0000000000000000UL
,
/* 0x0370, */
0x0000000000000000UL
,
/* 0x0378, */
0x0000000000000000UL
,
/* 0x0380, */
0x0000000000000000UL
,
/* 0x0388, */
0x0000000000000000UL
,
/* 0x0390, */
0x0000000000000000UL
,
};
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt390.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
static
uint64_t
qoswt_fix
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x001008630000C010UL
,
/* 0x0038, */
0x001008630000C010UL
,
/* 0x0040, */
0x001418BA0000FFF0UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x001415270000C010UL
,
/* 0x0060, */
0x001415270000C010UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0014083E0000FFF0UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x0000000000000000UL
,
/* 0x01c8, */
0x0000000000000000UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0000000000000000UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0000000000000000UL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x000C0C2A0000FFF0UL
,
/* 0x0268, */
0x001410040000FFF0UL
,
/* 0x0270, */
0x001404020000FFF0UL
,
/* 0x0278, */
0x000C08110000FFF0UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x001410040000FFF0UL
,
/* 0x0298, */
0x001404020000FFF0UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x0000000000000000UL
,
/* 0x0360, */
0x0000000000000000UL
,
/* 0x0368, */
0x0000000000000000UL
,
/* 0x0370, */
0x0000000000000000UL
,
/* 0x0378, */
0x0000000000000000UL
,
/* 0x0380, */
0x0000000000000000UL
,
/* 0x0388, */
0x0000000000000000UL
,
/* 0x0390, */
0x0000000000000000UL
,
};
static
uint64_t
qoswt_be
[]
=
{
/* 0x0000, */
0x0000000000000000UL
,
/* 0x0008, */
0x0000000000000000UL
,
/* 0x0010, */
0x0000000000000000UL
,
/* 0x0018, */
0x0000000000000000UL
,
/* 0x0020, */
0x0000000000000000UL
,
/* 0x0028, */
0x0000000000000000UL
,
/* 0x0030, */
0x0000000000000000UL
,
/* 0x0038, */
0x0000000000000000UL
,
/* 0x0040, */
0x0000000000000000UL
,
/* 0x0048, */
0x0000000000000000UL
,
/* 0x0050, */
0x0000000000000000UL
,
/* 0x0058, */
0x0000000000000000UL
,
/* 0x0060, */
0x0000000000000000UL
,
/* 0x0068, */
0x0000000000000000UL
,
/* 0x0070, */
0x0000000000000000UL
,
/* 0x0078, */
0x0000000000000000UL
,
/* 0x0080, */
0x0000000000000000UL
,
/* 0x0088, */
0x0000000000000000UL
,
/* 0x0090, */
0x0000000000000000UL
,
/* 0x0098, */
0x0000000000000000UL
,
/* 0x00a0, */
0x0000000000000000UL
,
/* 0x00a8, */
0x0000000000000000UL
,
/* 0x00b0, */
0x0000000000000000UL
,
/* 0x00b8, */
0x0000000000000000UL
,
/* 0x00c0, */
0x0000000000000000UL
,
/* 0x00c8, */
0x0000000000000000UL
,
/* 0x00d0, */
0x0000000000000000UL
,
/* 0x00d8, */
0x0000000000000000UL
,
/* 0x00e0, */
0x0000000000000000UL
,
/* 0x00e8, */
0x0000000000000000UL
,
/* 0x00f0, */
0x0000000000000000UL
,
/* 0x00f8, */
0x0000000000000000UL
,
/* 0x0100, */
0x0000000000000000UL
,
/* 0x0108, */
0x0000000000000000UL
,
/* 0x0110, */
0x0000000000000000UL
,
/* 0x0118, */
0x0000000000000000UL
,
/* 0x0120, */
0x0000000000000000UL
,
/* 0x0128, */
0x0000000000000000UL
,
/* 0x0130, */
0x0000000000000000UL
,
/* 0x0138, */
0x0000000000000000UL
,
/* 0x0140, */
0x0000000000000000UL
,
/* 0x0148, */
0x0000000000000000UL
,
/* 0x0150, */
0x0000000000000000UL
,
/* 0x0158, */
0x0000000000000000UL
,
/* 0x0160, */
0x0000000000000000UL
,
/* 0x0168, */
0x0000000000000000UL
,
/* 0x0170, */
0x0000000000000000UL
,
/* 0x0178, */
0x0000000000000000UL
,
/* 0x0180, */
0x0000000000000000UL
,
/* 0x0188, */
0x0000000000000000UL
,
/* 0x0190, */
0x0000000000000000UL
,
/* 0x0198, */
0x0000000000000000UL
,
/* 0x01a0, */
0x0000000000000000UL
,
/* 0x01a8, */
0x0000000000000000UL
,
/* 0x01b0, */
0x0000000000000000UL
,
/* 0x01b8, */
0x0000000000000000UL
,
/* 0x01c0, */
0x0000000000000000UL
,
/* 0x01c8, */
0x0000000000000000UL
,
/* 0x01d0, */
0x0000000000000000UL
,
/* 0x01d8, */
0x0000000000000000UL
,
/* 0x01e0, */
0x0000000000000000UL
,
/* 0x01e8, */
0x0000000000000000UL
,
/* 0x01f0, */
0x0000000000000000UL
,
/* 0x01f8, */
0x0000000000000000UL
,
/* 0x0200, */
0x0000000000000000UL
,
/* 0x0208, */
0x0000000000000000UL
,
/* 0x0210, */
0x0000000000000000UL
,
/* 0x0218, */
0x0000000000000000UL
,
/* 0x0220, */
0x0000000000000000UL
,
/* 0x0228, */
0x0000000000000000UL
,
/* 0x0230, */
0x0000000000000000UL
,
/* 0x0238, */
0x0000000000000000UL
,
/* 0x0240, */
0x0000000000000000UL
,
/* 0x0248, */
0x0000000000000000UL
,
/* 0x0250, */
0x0000000000000000UL
,
/* 0x0258, */
0x0000000000000000UL
,
/* 0x0260, */
0x0000000000000000UL
,
/* 0x0268, */
0x0000000000000000UL
,
/* 0x0270, */
0x0000000000000000UL
,
/* 0x0278, */
0x0000000000000000UL
,
/* 0x0280, */
0x0000000000000000UL
,
/* 0x0288, */
0x0000000000000000UL
,
/* 0x0290, */
0x0000000000000000UL
,
/* 0x0298, */
0x0000000000000000UL
,
/* 0x02a0, */
0x0000000000000000UL
,
/* 0x02a8, */
0x0000000000000000UL
,
/* 0x02b0, */
0x0000000000000000UL
,
/* 0x02b8, */
0x0000000000000000UL
,
/* 0x02c0, */
0x0000000000000000UL
,
/* 0x02c8, */
0x0000000000000000UL
,
/* 0x02d0, */
0x0000000000000000UL
,
/* 0x02d8, */
0x0000000000000000UL
,
/* 0x02e0, */
0x0000000000000000UL
,
/* 0x02e8, */
0x0000000000000000UL
,
/* 0x02f0, */
0x0000000000000000UL
,
/* 0x02f8, */
0x0000000000000000UL
,
/* 0x0300, */
0x0000000000000000UL
,
/* 0x0308, */
0x0000000000000000UL
,
/* 0x0310, */
0x0000000000000000UL
,
/* 0x0318, */
0x0000000000000000UL
,
/* 0x0320, */
0x0000000000000000UL
,
/* 0x0328, */
0x0000000000000000UL
,
/* 0x0330, */
0x0000000000000000UL
,
/* 0x0338, */
0x0000000000000000UL
,
/* 0x0340, */
0x0000000000000000UL
,
/* 0x0348, */
0x0000000000000000UL
,
/* 0x0350, */
0x0000000000000000UL
,
/* 0x0358, */
0x0000000000000000UL
,
/* 0x0360, */
0x0000000000000000UL
,
/* 0x0368, */
0x0000000000000000UL
,
/* 0x0370, */
0x0000000000000000UL
,
/* 0x0378, */
0x0000000000000000UL
,
/* 0x0380, */
0x0000000000000000UL
,
/* 0x0388, */
0x0000000000000000UL
,
/* 0x0390, */
0x0000000000000000UL
,
};
drivers/staging/renesas/rcar/qos/qos.mk
0 → 100644
View file @
a51443fa
#
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq
(${RCAR_LSI},${RCAR_AUTO})
# E3, H3N not available for LSI_AUTO
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
else
ifdef
RCAR_LSI_CUT_COMPAT
ifeq
(${RCAR_LSI},${RCAR_H3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
endif
ifeq
(${RCAR_LSI},${RCAR_H3N})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
endif
ifeq
(${RCAR_LSI},${RCAR_M3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
endif
ifeq
(${RCAR_LSI},${RCAR_M3N})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
endif
ifeq
(${RCAR_LSI},${RCAR_E3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
endif
else
ifeq
(${RCAR_LSI},${RCAR_H3})
ifeq
(${LSI_CUT},10)
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
else
ifeq
(${LSI_CUT},11)
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
else
ifeq
(${LSI_CUT},20)
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
else
ifeq
(${LSI_CUT},30)
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
else
# LSI_CUT 30 or later
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
endif
endif
ifeq
(${RCAR_LSI},${RCAR_H3N})
ifeq
(${LSI_CUT},30)
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
else
# LSI_CUT 30 or later
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
endif
endif
ifeq
(${RCAR_LSI},${RCAR_M3})
ifeq
(${LSI_CUT},10)
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
else
ifeq
(${LSI_CUT},11)
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
else
# LSI_CUT 11 or later
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
endif
endif
ifeq
(${RCAR_LSI},${RCAR_M3N})
ifeq
(${LSI_CUT},10)
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
else
# LSI_CUT 10 or later
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
endif
endif
ifeq
(${RCAR_LSI},${RCAR_E3})
ifeq
(${LSI_CUT},10)
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
else
# LSI_CUT 10 or later
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
endif
endif
endif
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/qos_init.c
drivers/staging/renesas/rcar/qos/qos_common.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef QOS_COMMON_H_
#define QOS_COMMON_H_
#define RCAR_REF_DEFAULT (0U)
#if (RCAR_LSI == RCAR_E3)
/* define used for E3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)
/* REF 3.9usec */
#define SUB_SLOT_CYCLE_E3 (0xAFU)
/* 175 */
#else
/* REF 7.8usec */
#define SUB_SLOT_CYCLE_E3 (0x15EU)
/* 350 */
#endif
/* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define OPERATING_FREQ_E3 (266U)
/* MHz */
#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U)
#define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3)
/* unit:ns */
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
/* define used for M3N */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)
/* REF 1.95usec */
#define SUB_SLOT_CYCLE_M3N (0x84U)
/* 132 */
#else
/* REF 3.9usec */
#define SUB_SLOT_CYCLE_M3N (0x108U)
/* 264 */
#endif
/* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N -1U)
#define QOSWT_WTSET0_CYCLE_M3N ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)
/* unit:ns */
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
/* define used for H3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)
/* REF 1.95usec */
#define SUB_SLOT_CYCLE_H3_20 (0x84U)
/* 132 */
#else
/* REF 3.9usec */
#define SUB_SLOT_CYCLE_H3_20 (0x108U)
/* 264 */
#endif
/* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 -1U)
#define QOSWT_WTSET0_CYCLE_H3_20 ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)
/* unit:ns */
/* define used for H3 Cut 30 */
#define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20)
/* same as H3 Cut 20 */
#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 -1U)
#define QOSWT_WTSET0_CYCLE_H3_30 ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)
/* unit:ns */
#endif
#if (RCAR_LSI == RCAR_H3N)
/* define used for H3N */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)
/* REF 1.95usec */
#define SUB_SLOT_CYCLE_H3N (0x84U)
/* 132 */
#else
/* REF 3.9usec */
#define SUB_SLOT_CYCLE_H3N (0x108U)
/* 264 */
#endif
/* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N -1U)
#define QOSWT_WTSET0_CYCLE_H3N ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)
/* unit:ns */
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
/* define used for M3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)
/* REF 1.95usec */
#define SUB_SLOT_CYCLE_M3_11 (0x84U)
/* 132 */
#else
/* REF 3.9usec */
#define SUB_SLOT_CYCLE_M3_11 (0x108U)
/* 264 */
#endif
/* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U)
#define QOSWT_WTSET0_CYCLE_M3_11 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)
/* unit:ns */
#endif
#define OPERATING_FREQ (400U)
/* MHz */
#define BASE_SUB_SLOT_NUM (0x6U)
#define SUB_SLOT_CYCLE (0x7EU)
/* 126 */
#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)
/* unit:ns */
#define SL_INIT_REFFSSLOT (0x3U << 24U)
#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE -1U)
static
inline
void
io_write_32
(
uintptr_t
addr
,
uint32_t
value
)
{
*
(
volatile
uint32_t
*
)
addr
=
value
;
}
static
inline
uint32_t
io_read_32
(
uintptr_t
addr
)
{
return
*
(
volatile
uint32_t
*
)
addr
;
}
static
inline
void
io_write_64
(
uintptr_t
addr
,
uint64_t
value
)
{
*
(
volatile
uint64_t
*
)
addr
=
value
;
}
typedef
struct
{
uintptr_t
addr
;
uint64_t
value
;
}
mstat_slot_t
;
extern
uint32_t
qos_init_ddr_ch
;
extern
uint8_t
qos_init_ddr_phyvalid
;
#endif
/* QOS_COMMON_H_ */
drivers/staging/renesas/rcar/qos/qos_init.c
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <debug.h>
#include <mmio.h>
#include "qos_init.h"
#include "qos_common.h"
#if RCAR_LSI == RCAR_AUTO
#include "H3/qos_init_h3_v10.h"
#include "H3/qos_init_h3_v11.h"
#include "H3/qos_init_h3_v20.h"
#include "H3/qos_init_h3_v30.h"
#include "M3/qos_init_m3_v10.h"
#include "M3/qos_init_m3_v11.h"
#include "M3N/qos_init_m3n_v10.h"
#endif
#if RCAR_LSI == RCAR_H3
/* H3 */
#include "H3/qos_init_h3_v10.h"
#include "H3/qos_init_h3_v11.h"
#include "H3/qos_init_h3_v20.h"
#include "H3/qos_init_h3_v30.h"
#endif
#if RCAR_LSI == RCAR_H3N
/* H3 */
#include "H3/qos_init_h3n_v30.h"
#endif
#if RCAR_LSI == RCAR_M3
/* M3 */
#include "M3/qos_init_m3_v10.h"
#include "M3/qos_init_m3_v11.h"
#endif
#if RCAR_LSI == RCAR_M3N
/* M3N */
#include "M3N/qos_init_m3n_v10.h"
#endif
#if RCAR_LSI == RCAR_E3
/* E3 */
#include "E3/qos_init_e3_v10.h"
#endif
/* Product Register */
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_H3 (0x00004F00U)
/* R-Car H3 */
#define PRR_PRODUCT_M3 (0x00005200U)
/* R-Car M3 */
#define PRR_PRODUCT_M3N (0x00005500U)
/* R-Car M3N */
#define PRR_PRODUCT_E3 (0x00005700U)
/* R-Car E3 */
#define PRR_PRODUCT_10 (0x00U)
#define PRR_PRODUCT_11 (0x01U)
#define PRR_PRODUCT_20 (0x10U)
#define PRR_PRODUCT_30 (0x20U)
#if !(RCAR_LSI == RCAR_E3)
#define DRAM_CH_CNT 0x04
uint32_t
qos_init_ddr_ch
;
uint8_t
qos_init_ddr_phyvalid
;
#endif
#define PRR_PRODUCT_ERR(reg) \
do{ \
ERROR("LSI Product ID(PRR=0x%x) QoS " \
"initialize not supported.\n",reg); \
panic(); \
} while(0)
#define PRR_CUT_ERR(reg) \
do{ \
ERROR("LSI Cut ID(PRR=0x%x) QoS " \
"initialize not supported.\n",reg); \
panic(); \
} while(0)
void
rcar_qos_init
(
void
)
{
uint32_t
reg
;
#if !(RCAR_LSI == RCAR_E3)
uint32_t
i
;
qos_init_ddr_ch
=
0
;
qos_init_ddr_phyvalid
=
get_boardcnf_phyvalid
();
for
(
i
=
0
;
i
<
DRAM_CH_CNT
;
i
++
)
{
if
((
qos_init_ddr_phyvalid
&
(
1
<<
i
)))
{
qos_init_ddr_ch
++
;
}
}
#endif
reg
=
mmio_read_32
(
PRR
);
#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
switch
(
reg
&
PRR_PRODUCT_MASK
)
{
case
PRR_PRODUCT_H3
:
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
switch
(
reg
&
PRR_CUT_MASK
)
{
case
PRR_PRODUCT_10
:
qos_init_h3_v10
();
break
;
case
PRR_PRODUCT_11
:
qos_init_h3_v11
();
break
;
case
PRR_PRODUCT_20
:
qos_init_h3_v20
();
break
;
case
PRR_PRODUCT_30
:
default:
qos_init_h3_v30
();
break
;
}
#elif (RCAR_LSI == RCAR_H3N)
switch
(
reg
&
PRR_CUT_MASK
)
{
case
PRR_PRODUCT_30
:
default:
qos_init_h3n_v30
();
break
;
}
#else
PRR_PRODUCT_ERR
(
reg
);
#endif
break
;
case
PRR_PRODUCT_M3
:
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
switch
(
reg
&
PRR_CUT_MASK
)
{
case
PRR_PRODUCT_10
:
qos_init_m3_v10
();
break
;
case
PRR_PRODUCT_20
:
/* M3 Cut 11 */
default:
qos_init_m3_v11
();
break
;
}
#else
PRR_PRODUCT_ERR
(
reg
);
#endif
break
;
case
PRR_PRODUCT_M3N
:
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
switch
(
reg
&
PRR_CUT_MASK
)
{
case
PRR_PRODUCT_10
:
default:
qos_init_m3n_v10
();
break
;
}
#else
PRR_PRODUCT_ERR
(
reg
);
#endif
break
;
case
PRR_PRODUCT_E3
:
#if (RCAR_LSI == RCAR_E3)
switch
(
reg
&
PRR_CUT_MASK
)
{
case
PRR_PRODUCT_10
:
default:
qos_init_e3_v10
();
break
;
}
#else
PRR_PRODUCT_ERR
(
reg
);
#endif
break
;
default:
PRR_PRODUCT_ERR
(
reg
);
break
;
}
#else
#if RCAR_LSI == RCAR_H3
/* H3 */
#if RCAR_LSI_CUT == RCAR_CUT_10
/* H3 Cut 10 */
if
((
PRR_PRODUCT_H3
|
PRR_PRODUCT_10
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
|
PRR_CUT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
qos_init_h3_v10
();
#elif RCAR_LSI_CUT == RCAR_CUT_11
/* H3 Cut 11 */
if
((
PRR_PRODUCT_H3
|
PRR_PRODUCT_11
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
|
PRR_CUT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
qos_init_h3_v11
();
#elif RCAR_LSI_CUT == RCAR_CUT_20
/* H3 Cut 20 */
if
((
PRR_PRODUCT_H3
|
PRR_PRODUCT_20
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
|
PRR_CUT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
qos_init_h3_v20
();
#else
/* H3 Cut 30 or later */
if
((
PRR_PRODUCT_H3
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
qos_init_h3_v30
();
#endif
#elif RCAR_LSI == RCAR_H3N
/* H3 */
/* H3N Cut 30 or later */
if
((
PRR_PRODUCT_H3
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
qos_init_h3n_v30
();
#elif RCAR_LSI == RCAR_M3
/* M3 */
#if RCAR_LSI_CUT == RCAR_CUT_10
/* M3 Cut 10 */
if
((
PRR_PRODUCT_M3
|
PRR_PRODUCT_10
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
|
PRR_CUT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
qos_init_m3_v10
();
#else
/* M3 Cut 11 or later */
if
((
PRR_PRODUCT_M3
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
qos_init_m3_v11
();
#endif
#elif RCAR_LSI == RCAR_M3N
/* M3N */
/* M3N Cut 10 or later */
if
((
PRR_PRODUCT_M3N
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
qos_init_m3n_v10
();
#elif RCAR_LSI == RCAR_E3
/* E3 */
/* E3 Cut 10 or later */
if
((
PRR_PRODUCT_E3
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
qos_init_e3_v10
();
#else
#error "Don't have QoS initialize routine(Unknown chip)."
#endif
#endif
}
uint32_t
get_refperiod
(
void
)
{
uint32_t
refperiod
=
QOSWT_WTSET0_CYCLE
;
#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
uint32_t
reg
;
reg
=
mmio_read_32
(
PRR
);
switch
(
reg
&
PRR_PRODUCT_MASK
)
{
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
case
PRR_PRODUCT_H3
:
switch
(
reg
&
PRR_CUT_MASK
)
{
case
PRR_PRODUCT_10
:
case
PRR_PRODUCT_11
:
break
;
case
PRR_PRODUCT_20
:
refperiod
=
QOSWT_WTSET0_CYCLE_H3_20
;
break
;
case
PRR_PRODUCT_30
:
default:
refperiod
=
QOSWT_WTSET0_CYCLE_H3_30
;
break
;
}
break
;
#elif (RCAR_LSI == RCAR_H3N)
case
PRR_PRODUCT_H3
:
switch
(
reg
&
PRR_CUT_MASK
)
{
case
PRR_PRODUCT_30
:
default:
refperiod
=
QOSWT_WTSET0_CYCLE_H3N
;
break
;
}
break
;
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
case
PRR_PRODUCT_M3
:
switch
(
reg
&
PRR_CUT_MASK
)
{
case
PRR_PRODUCT_10
:
break
;
case
PRR_PRODUCT_20
:
/* M3 Cut 11 */
default:
refperiod
=
QOSWT_WTSET0_CYCLE_M3_11
;
break
;
}
break
;
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
case
PRR_PRODUCT_M3N
:
refperiod
=
QOSWT_WTSET0_CYCLE_M3N
;
break
;
#endif
#if (RCAR_LSI == RCAR_E3)
case
PRR_PRODUCT_E3
:
refperiod
=
QOSWT_WTSET0_CYCLE_E3
;
break
;
#endif
default:
break
;
}
#elif RCAR_LSI == RCAR_H3
#if RCAR_LSI_CUT == RCAR_CUT_10
/* H3 Cut 10 */
#elif RCAR_LSI_CUT == RCAR_CUT_11
/* H3 Cut 11 */
#elif RCAR_LSI_CUT == RCAR_CUT_20
/* H3 Cut 20 */
refperiod
=
QOSWT_WTSET0_CYCLE_H3_20
;
#else
/* H3 Cut 30 or later */
refperiod
=
QOSWT_WTSET0_CYCLE_H3_30
;
#endif
#elif RCAR_LSI == RCAR_H3N
/* H3N Cut 30 or later */
refperiod
=
QOSWT_WTSET0_CYCLE_H3N
;
#elif RCAR_LSI == RCAR_M3
#if RCAR_LSI_CUT == RCAR_CUT_10
/* M3 Cut 10 */
#else
/* M3 Cut 11 or later */
refperiod
=
QOSWT_WTSET0_CYCLE_M3_11
;
#endif
#elif RCAR_LSI == RCAR_M3N
/* for M3N */
refperiod
=
QOSWT_WTSET0_CYCLE_M3N
;
#elif RCAR_LSI == RCAR_E3
/* for E3 */
refperiod
=
QOSWT_WTSET0_CYCLE_E3
;
#endif
return
refperiod
;
}
drivers/staging/renesas/rcar/qos/qos_init.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef QOS_INIT_H_
#define QOS_INIT_H_
extern
void
rcar_qos_init
(
void
);
extern
uint8_t
get_boardcnf_phyvalid
(
void
);
#endif
/* QOS_INIT_H_ */
drivers/staging/renesas/rcar/qos/qos_reg.h
0 → 100644
View file @
a51443fa
/*
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef QOS_REG_H_
#define QOS_REG_H_
#define RCAR_QOS_NONE (3U)
#define RCAR_QOS_TYPE_DEFAULT (0U)
#define RCAR_DRAM_SPLIT_LINEAR (0U)
#define RCAR_DRAM_SPLIT_4CH (1U)
#define RCAR_DRAM_SPLIT_2CH (2U)
#define RCAR_DRAM_SPLIT_AUTO (3U)
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
#define DBSC_BASE (0xE6790000U)
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
#define AXI_BASE (0xE6784000U)
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
#define AXI_MMCR (AXI_BASE + 0x0300U)
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
#define ADSPLCR0_SWP (0x0CU)
#define AXI_TR3CR (0xE67D100CU)
#define AXI_TR4CR (0xE67D1014U)
#define QOS_BASE0 (0xE67E0000U)
#define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U)
#define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U)
#define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U)
#define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U)
#define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U)
#define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U)
#define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U)
#define QOS_BASE1 (0xE67F0000U)
#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
#define GPU_ACT_GRD (0xFD820808U)
#define GPU_ACT0 (0xFD820800U)
#define GPU_ACT1 (0xFD821800U)
#define GPU_ACT2 (0xFD822800U)
#define GPU_ACT3 (0xFD823800U)
#define GPU_ACT4 (0xFD824800U)
#define GPU_ACT5 (0xFD825800U)
#define GPU_ACT6 (0xFD826800U)
#define GPU_ACT7 (0xFD827800U)
#define RT_ACT0 (0xFFC50800U)
#define RT_ACT1 (0xFFC51800U)
#define CPU_ACT0 (0xF1300800U)
#define CPU_ACT1 (0xF1340800U)
#define CPU_ACT2 (0xF1380800U)
#define CPU_ACT3 (0xF13C0800U)
#define RCAR_REWT_TRAINING_DISABLE (0U)
#define RCAR_REWT_TRAINING_ENABLE (1U)
#define QOSWT_FIX_WTQOS_BANK0 (QOSBW_FIX_QOS_BANK0 + 0x0800U)
#define QOSWT_FIX_WTQOS_BANK1 (QOSBW_FIX_QOS_BANK1 + 0x0800U)
#define QOSWT_BE_WTQOS_BANK0 (QOSBW_BE_QOS_BANK0 + 0x0800U)
#define QOSWT_BE_WTQOS_BANK1 (QOSBW_BE_QOS_BANK1 + 0x0800U)
#define QOSWT_WTEN (QOS_BASE0 + 0x8030U)
#define QOSWT_WTREF (QOS_BASE0 + 0x8034U)
#define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U)
#define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU)
#endif
/* QOS_REG_H_ */
maintainers.rst
View file @
a51443fa
...
...
@@ -140,6 +140,15 @@ Raspberry Pi 3 platform port
:F: docs/plat/rpi3.rst
:F: plat/rpi3/
Renesas rcar-gen3 platform port
-------------------------------
:M: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
:G: `ldts`_
:F: docs/plat/rcar-gen3.rst
:F: plat/renesas/rcar
:F: drivers/renesas/rcar
:F: tools/renesas/rcar_layout_create
RockChip platform port
----------------------
:M: Tony Xie <tony.xie@rock-chips.com>
...
...
@@ -208,6 +217,7 @@ Xilinx platform port
.. _glneo: https://github.com/glneo
.. _hzhuang1: https://github.com/hzhuang1
.. _jenswi-linaro: https://github.com/jenswi-linaro
.. _ldts: https://github.com/ldts
.. _niej: https://github.com/niej
.. _kostapr: https://github.com/kostapr
.. _masahir0y: https://github.com/masahir0y
...
...
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