From a66952750526c34c9ab420ea4cf7c2c8f4e6ef5b Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux <sandrine.bailleux@arm.com> Date: Thu, 14 May 2015 14:13:05 +0100 Subject: [PATCH] Always enable CCI coherency in BL3-1 On ARM standard platforms, snoop and DVM requests used to be enabled for the primary CPU's cluster only in the first EL3 bootloader. In other words, if the platform reset into BL1 then CCI coherency would be enabled by BL1 only, and not by BL3-1 again. However, this doesn't cater for platforms that use BL3-1 along with a non-TF ROM bootloader that doesn't enable snoop and DVM requests. In this case, CCI coherency is never enabled. This patch modifies the function bl31_early_platform_setup() on ARM standard platforms so that it always enables snoop and DVM requests regardless of whether earlier bootloader stages have already done it. There is no harm in executing this code twice. ARM Trusted Firmware Design document updated accordingly. Change-Id: Idf1bdeb24d2e1947adfbb76a509f10beef224e1c --- docs/firmware-design.md | 11 ++++------- plat/arm/board/fvp/fvp_bl31_setup.c | 10 +++++----- plat/arm/common/arm_bl31_setup.c | 10 +++++----- 3 files changed, 14 insertions(+), 17 deletions(-) diff --git a/docs/firmware-design.md b/docs/firmware-design.md index 70737b531..c5a8cba39 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -184,7 +184,7 @@ BL1 performs minimal architectural initialization as follows. #### Platform initialization -BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests from +BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests to the CCI slave interface corresponding to the cluster that includes the primary CPU. BL1 also initializes a UART (PL011 console), which enables access to the `printf` family of functions in BL1. @@ -334,7 +334,9 @@ the clock frequency of the system counter, which is provided by the platform. BL3-1 performs detailed platform initialization, which enables normal world software to function correctly. It also retrieves entrypoint information for the BL3-3 image loaded by BL2 from the platform defined memory address populated -by BL2. BL3-1 also initializes a UART (PL011 console), which enables +by BL2. It enables issuing of snoop and DVM (Distributed Virtual Memory) +requests to the CCI slave interface corresponding to the cluster that includes +the primary CPU. BL3-1 also initializes a UART (PL011 console), which enables access to the `printf` family of functions in BL3-1. It enables the system level implementation of the generic timer through the memory mapped interface. @@ -543,11 +545,6 @@ implementation via a platform defined mechanism. On a cold boot, the platform must place any secondary CPUs into a safe state while the primary CPU executes a modified BL3-1 initialization, as described below. -#### Architectural initialization - -As the first image to execute in this configuration BL3-1 must ensure that -interconnect coherency is enabled (if required) before enabling the MMU. - #### Platform initialization In this configuration, when the CPU resets to BL3-1 there are no parameters diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c index b50ae55c3..f29af6477 100644 --- a/plat/arm/board/fvp/fvp_bl31_setup.c +++ b/plat/arm/board/fvp/fvp_bl31_setup.c @@ -45,13 +45,13 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, * No need for locks as no other CPU is active. */ fvp_cci_init(); -#if RESET_TO_BL31 + /* - * Enable CCI coherency for the primary CPU's cluster - * (if earlier BL has not already done so). + * Enable CCI coherency for the primary CPU's cluster. + * Earlier bootloader stages might already do this (e.g. Trusted + * Firmware's BL1 does it) but we can't assume so. There is no harm in + * executing this code twice anyway. * FVP PSCI code will enable coherency for other clusters. */ fvp_cci_enable(); - -#endif /* RESET_TO_BL31 */ } diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index 5c321fafc..7e8856bad 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -179,16 +179,16 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, * No need for locks as no other CPU is active. */ arm_cci_init(); -#if RESET_TO_BL31 + /* - * Enable CCI coherency for the primary CPU's cluster - * (if earlier BL has not already done so). + * Enable CCI coherency for the primary CPU's cluster. + * Earlier bootloader stages might already do this (e.g. Trusted + * Firmware's BL1 does it) but we can't assume so. There is no harm in + * executing this code twice anyway. * Platform specific PSCI code will enable coherency for other * clusters. */ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); - -#endif /* RESET_TO_BL31 */ } /******************************************************************************* -- GitLab