diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c
index 7d4abf0faba59faff54eb3b867774daa5c37fde9..f66150ae898acea304316b3fb5f4ff630c34932c 100644
--- a/plat/rockchip/rk3399/drivers/dram/suspend.c
+++ b/plat/rockchip/rk3399/drivers/dram/suspend.c
@@ -726,6 +726,8 @@ __pmusramfunc void dmc_resume(void)
 	uint32_t channel_mask = 0;
 	uint32_t channel;
 
+	sram_secure_timer_init();
+
 	/*
 	 * we switch ddr clock to abpll when suspend,
 	 * we set back to dpll here
diff --git a/plat/rockchip/rk3399/drivers/secure/secure.c b/plat/rockchip/rk3399/drivers/secure/secure.c
index 6b4f3b894ad1fbc921f46d6b631be6607fbd92e7..589d833c8f243dd2f08718942fd85d3260e80e22 100644
--- a/plat/rockchip/rk3399/drivers/secure/secure.c
+++ b/plat/rockchip/rk3399/drivers/secure/secure.c
@@ -101,6 +101,19 @@ void secure_watchdog_enable(void)
 		      WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT));
 }
 
+__pmusramfunc void sram_secure_timer_init(void)
+{
+	mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
+	mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
+
+	mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
+	mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
+
+	/* auto reload & enable the timer */
+	mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
+		      TIMER_EN | TIMER_FMODE);
+}
+
 void secure_timer_init(void)
 {
 	mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
diff --git a/plat/rockchip/rk3399/drivers/secure/secure.h b/plat/rockchip/rk3399/drivers/secure/secure.h
index 7784ae7614a335900f9c2d81b1005b2eb52a2f39..334805d0d13c420d72943d080ab96b884715be2b 100644
--- a/plat/rockchip/rk3399/drivers/secure/secure.h
+++ b/plat/rockchip/rk3399/drivers/secure/secure.h
@@ -100,5 +100,6 @@ void secure_watchdog_enable(void);
 void secure_timer_init(void);
 void secure_sgrf_init(void);
 void secure_sgrf_ddr_rgn_init(void);
+__pmusramfunc void sram_secure_timer_init(void);
 
 #endif /* __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ */