From a9b3021e145c7174f08465e88e6aba65a4099fdf Mon Sep 17 00:00:00 2001
From: Haojian Zhuang <haojian.zhuang@linaro.org>
Date: Mon, 29 Jan 2018 11:42:42 +0800
Subject: [PATCH] hikey: clean dcache for SRAM after initialized

Although SRAM is initialized, DCACHE should be cleaned too.
Because MCU is a parrallel core to access SRAM. We need to make
sure that initialized value is really written to SRAM before
MCU using it.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
---
 plat/hisilicon/hikey/hikey_bl2_setup.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c
index 810f6aaa0..6080f84f2 100644
--- a/plat/hisilicon/hikey/hikey_bl2_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl2_setup.c
@@ -276,6 +276,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
 
 	/* Clear SRAM since it'll be used by MCU right now. */
 	memset((void *)SRAM_BASE, 0, SRAM_SIZE);
+	clean_dcache_range(SRAM_BASE, SRAM_SIZE);
 
 	sp804_timer_init(SP804_TIMER0_BASE, 10, 192);
 	dsb();
-- 
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