Tegra: fix defects flagged by MISRA Rule 10.3

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.

Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.

Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

plat/nvidia/tegra/common/drivers/bpmp/bpmp.c

@@ -76,7 +76,7 @@ int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz,
 			/* signal command ready to the BPMP */
 			signal_slave(ch);
 			mmio_write_32(TEGRA_PRI_ICTLR_BASE + CPU_IEP_FIR_SET,
-				      (1UL << INT_SHR_SEM_OUTBOX_FULL));
+				      (1U << INT_SHR_SEM_OUTBOX_FULL));
 
 			/* loop until the command is executed */
 			for (timeout = 0; timeout < BPMP_TIMEOUT_10US; timeout++) {
@@ -154,7 +154,7 @@ int tegra_bpmp_init(void)
 			channel_base[ch] = mmio_read_32(base);
 
 			/* increment result register offset */
-			base += 4UL;
+			base += 4U;
 		}
 
 		/* mark state as "initialized" */

plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c

@@ -302,24 +302,24 @@ static void tegra_memctrl_set_overrides(void)
 	 */
 	if ((tegra_chipid_is_t186()) &&
 	    (!tegra_platform_is_silicon() ||
-	    (tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1)))) {
+	    (tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1U)))) {
 
 		/*
 		 * GPU and NVENC settings for Tegra186 simulation and
 		 * Silicon rev. A01
 		 */
 		val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
-		val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
+		val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
 		tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
 			val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
 
 		val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
-		val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
+		val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
 		tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
 			val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
 
 		val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
-		val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
+		val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
 		tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
 			val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
 
@@ -330,7 +330,7 @@ static void tegra_memctrl_set_overrides(void)
 		 */
 		for (i = 0; i < num_txn_override_cfgs; i++) {
 			val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
-			val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
+			val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
 			tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
 				val | mc_txn_override_cfgs[i].cgid_tag);
 		}
@@ -421,7 +421,7 @@ void tegra_memctrl_restore_settings(void)
 	tegra_memctrl_set_overrides();
 
 	/* video memory carveout region */
-	if (video_mem_base) {
+	if (video_mem_base != 0ULL) {
 		tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
 				  (uint32_t)video_mem_base);
 		tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,

plat/nvidia/tegra/common/drivers/smmu/smmu.c

@@ -19,7 +19,7 @@ extern void memcpy16(void *dest, const void *src, unsigned int length);
 
 /* SMMU IDs currently supported by the driver */
 enum {
-	TEGRA_SMMU0,
+	TEGRA_SMMU0 = 0U,
 	TEGRA_SMMU1,
 	TEGRA_SMMU2
 };
@@ -86,8 +86,8 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
 	/* sanity check SMMU settings c*/
 	reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
 	pgshift = ((reg_id1 & ID1_PAGESIZE) != 0U) ? 16U : 12U;
-	cb_size = (2UL << pgshift) * \
-	(1UL << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1UL));
+	cb_size = ((uint32_t)2 << pgshift) * \
+	((uint32_t)1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1U));
 
 	assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
 	assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
@@ -111,8 +111,9 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
 	}
 
 	/* save SMMU register values */
-	for (i = 1; i < num_entries; i++)
+	for (i = 1U; i < num_entries; i++) {
 		smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
+	}
 
 	/* increment by 1 to take care of the last entry */
 	num_entries++;
@@ -139,17 +140,16 @@ void tegra_smmu_init(void)
 	uint32_t val, cb_idx, smmu_id, ctx_base;
 	uint32_t smmu_counter = plat_get_num_smmu_devices();
 
-	for (smmu_id = 0UL; smmu_id < smmu_counter; smmu_id++) {
-
+	for (smmu_id = 0U; smmu_id < smmu_counter; smmu_id++) {
 		/* Program the SMMU pagesize and reset CACHE_LOCK bit */
 		val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
 		val |= SMMU_GSR0_PGSIZE_64K;
-		val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
+		val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
 		tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
 
 		/* reset CACHE LOCK bit for NS Aux. Config. Register */
 		val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
-		val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
+		val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
 		tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
 
 		/* disable TCU prefetch for all contexts */
@@ -158,19 +158,19 @@ void tegra_smmu_init(void)
 		for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
 			val = tegra_smmu_read_32(smmu_id,
 				ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
-			val &= ~SMMU_CBn_ACTLR_CPRE_BIT;
+			val &= (uint32_t)~SMMU_CBn_ACTLR_CPRE_BIT;
 			tegra_smmu_write_32(smmu_id, ctx_base +
 				(SMMU_GSR0_PGSIZE_64K * cb_idx), val);
 		}
 
 		/* set CACHE LOCK bit for NS Aux. Config. Register */
 		val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
-		val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
+		val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
 		tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
 
 		/* set CACHE LOCK bit for S Aux. Config. Register */
 		val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
-		val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
+		val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
 		tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
 	}
 }

plat/nvidia/tegra/common/tegra_sip_calls.c

@@ -98,7 +98,7 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
 			 */
 			if (((x1 & 0xFFFFFU) != 0U) || ((local_x2_32 & 0xFFFFFU) != 0U)) {
 				ERROR("Unaligned Video Memory base address!\n");
-				SMC_RET1(handle, -ENOTSUP);
+				SMC_RET1(handle, (uint64_t)-ENOTSUP);
 			}
 
 			/*
@@ -108,9 +108,9 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
 			 */
 			regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
 					      TEGRA_GPU_RESET_REG_OFFSET);
-			if ((regval & GPU_RESET_BIT) == 0UL) {
+			if ((regval & GPU_RESET_BIT) == 0U) {
 				ERROR("GPU not in reset! Video Memory setup failed\n");
-				SMC_RET1(handle, -ENOTSUP);
+				SMC_RET1(handle, (uint64_t)-ENOTSUP);
 			}
 
 			/* new video memory carveout settings */

plat/nvidia/tegra/include/drivers/bpmp.h

@@ -10,25 +10,25 @@
 #include <stdint.h>
 
 /* macro to enable clock to the Atomics block */
-#define CAR_ENABLE_ATOMICS	(1UL << 16)
+#define CAR_ENABLE_ATOMICS	(1U << 16)
 
 /* command to get the channel base addresses from bpmp */
-#define ATOMIC_CMD_GET		4UL
+#define ATOMIC_CMD_GET		4U
 
 /* Hardware IRQ # used to signal bpmp of an incoming command */
-#define INT_SHR_SEM_OUTBOX_FULL	6UL
+#define INT_SHR_SEM_OUTBOX_FULL	6U
 
 /* macros to decode the bpmp's state */
-#define CH_MASK(ch)		(0x3UL << ((ch) * 2UL))
-#define MA_FREE(ch)		(0x2UL << ((ch) * 2UL))
-#define MA_ACKD(ch)		(0x3UL << ((ch) * 2UL))
+#define CH_MASK(ch)		((uint32_t)0x3 << ((ch) * 2U))
+#define MA_FREE(ch)		((uint32_t)0x2 << ((ch) * 2U))
+#define MA_ACKD(ch)		((uint32_t)0x3 << ((ch) * 2U))
 
 /* response from bpmp to indicate it has powered up */
-#define SIGN_OF_LIFE		0xAAAAAAAAUL
+#define SIGN_OF_LIFE		0xAAAAAAAAU
 
 /* flags to indicate bpmp driver's state */
-#define BPMP_INIT_COMPLETE	0xBEEFF00DUL
-#define BPMP_INIT_PENDING	0xDEADBEEFUL
+#define BPMP_INIT_COMPLETE	0xBEEFF00DU
+#define BPMP_INIT_PENDING	0xDEADBEEFU
 
 /* requests serviced by the bpmp */
 #define MRQ_PING		0
@@ -64,14 +64,14 @@
 #define TEGRA_PM_SC7		23
 
 /* flag to indicate if entry into a CCx power state is allowed */
-#define BPMP_CCx_ALLOWED	0UL
+#define BPMP_CCx_ALLOWED	0U
 
 /* number of communication channels to interact with the bpmp */
 #define NR_CHANNELS		4U
 
 /* flag to ask bpmp to acknowledge command packet */
-#define NO_ACK			(0UL << 0UL)
-#define DO_ACK			(1UL << 0UL)
+#define NO_ACK			(0U << 0U)
+#define DO_ACK			(1U << 0U)
 
 /* size of the command/response data */
 #define MSG_DATA_MAX_SZ		120U

plat/nvidia/tegra/include/drivers/smmu.h

@@ -586,12 +586,12 @@
 /*******************************************************************************
  * SMMU Global Aux. Control Register
  ******************************************************************************/
-#define SMMU_CBn_ACTLR_CPRE_BIT			(1UL << 1UL)
+#define SMMU_CBn_ACTLR_CPRE_BIT			(1ULL << 1U)
 
 /*******************************************************************************
  * SMMU configuration constants
  ******************************************************************************/
-#define ID1_PAGESIZE				(1U << 31)
+#define ID1_PAGESIZE				(1U << 31U)
 #define ID1_NUMPAGENDXB_SHIFT			28U
 #define ID1_NUMPAGENDXB_MASK			7U
 #define ID1_NUMS2CB_SHIFT			16U

plat/nvidia/tegra/include/t186/tegra_def.h

@@ -118,7 +118,7 @@
 /*******************************************************************************
  * Tegra General Purpose Centralised DMA constants
  ******************************************************************************/
-#define TEGRA_GPCDMA_BASE		U(0x2610000)
+#define TEGRA_GPCDMA_BASE		ULL(0x2610000)
 
 /*******************************************************************************
  * Tegra Memory Controller constants

plat/nvidia/tegra/include/t210/tegra_def.h

@@ -164,7 +164,7 @@
 #define MC_VIDEO_PROTECT_SIZE_MB	U(0x64c)
 
 /* SMMU configuration registers*/
-#define MC_SMMU_PPCS_ASID_0		0x270UL
+#define MC_SMMU_PPCS_ASID_0		0x270U
 #define  PPCS_SMMU_ENABLE		(0x1U << 31)
 
 /*******************************************************************************

plat/nvidia/tegra/soc/t186/drivers/mce/ari.c

@@ -151,7 +151,7 @@ int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
 
 		/* Enter the cstate, to be woken up after wake_time (TSC ticks) */
 		ret = ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT,
-		TEGRA_ARI_ENTER_CSTATE, state, wake_time);
+			(uint32_t)TEGRA_ARI_ENTER_CSTATE, state, wake_time);
 	}
 
 	return ret;
@@ -191,7 +191,7 @@ int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccp
 	}
 
 	/* set the updated cstate info */
-	return ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CSTATE_INFO,
+	return ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_UPDATE_CSTATE_INFO,
 				(uint32_t)val, wake_mask);
 }
 
@@ -208,8 +208,8 @@ int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t tim
 		ari_clobber_response(ari_base);
 
 		/* update crossover threshold time */
-		ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CROSSOVER,
-			type, time);
+		ret = ari_request_wait(ari_base, 0U,
+				(uint32_t)TEGRA_ARI_UPDATE_CROSSOVER, type, time);
 	}
 
 	return ret;
@@ -227,7 +227,8 @@ uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state)
 		/* clean the previous response state */
 		ari_clobber_response(ari_base);
 
-		ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_CSTATE_STATS, state, 0U);
+		ret = ari_request_wait(ari_base, 0U,
+				(uint32_t)TEGRA_ARI_CSTATE_STATS, state, 0U);
 		if (ret != 0) {
 			result = EINVAL;
 		} else {
@@ -243,8 +244,8 @@ int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats
 	ari_clobber_response(ari_base);
 
 	/* write the cstate stats */
-	return ari_request_wait(ari_base, 0U, TEGRA_ARI_WRITE_CSTATE_STATS, state,
-			stats);
+	return ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_WRITE_CSTATE_STATS,
+			state, stats);
 }
 
 uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data)
@@ -261,7 +262,7 @@ uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data)
 		local_data = 0U;
 	}
 
-	ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC, cmd, local_data);
+	ret = ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_MISC, cmd, local_data);
 	if (ret != 0) {
 		resp = (uint64_t)ret;
 	} else {
@@ -281,8 +282,8 @@ int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time
 	/* clean the previous response state */
 	ari_clobber_response(ari_base);
 
-	ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7U,
-			wake_time);
+	ret = ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_IS_CCX_ALLOWED,
+			state & 0x7U, wake_time);
 	if (ret != 0) {
 		ERROR("%s: failed (%d)\n", __func__, ret);
 		result = 0U;
@@ -307,8 +308,8 @@ int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time
 		/* clean the previous response state */
 		ari_clobber_response(ari_base);
 
-		ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_SC7_ALLOWED, state,
-				wake_time);
+		ret = ari_request_wait(ari_base, 0U,
+			(uint32_t)TEGRA_ARI_IS_SC7_ALLOWED, state, wake_time);
 		if (ret != 0) {
 			ERROR("%s: failed (%d)\n", __func__, ret);
 			result = 0;
@@ -346,7 +347,8 @@ int32_t ari_online_core(uint32_t ari_base, uint32_t core)
 		} else {
 			/* clean the previous response state */
 			ari_clobber_response(ari_base);
-			ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_ONLINE_CORE, core, 0U);
+			ret = ari_request_wait(ari_base, 0U,
+				(uint32_t)TEGRA_ARI_ONLINE_CORE, core, 0U);
 		}
 	}
 
@@ -374,7 +376,8 @@ int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t en
 		((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
 		((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
 
-	return ari_request_wait(ari_base, 0U, TEGRA_ARI_CC3_CTRL, val, 0U);
+	return ari_request_wait(ari_base, 0U,
+			(uint32_t)TEGRA_ARI_CC3_CTRL, val, 0U);
 }
 
 int32_t ari_reset_vector_update(uint32_t ari_base)
@@ -386,7 +389,8 @@ int32_t ari_reset_vector_update(uint32_t ari_base)
 	 * Need to program the CPU reset vector one time during cold boot
 	 * and SC7 exit
 	 */
-	(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0U, 0U);
+	(void)ari_request_wait(ari_base, 0U,
+			(uint32_t)TEGRA_ARI_COPY_MISCREG_AA64_RST, 0U, 0U);
 
 	return 0;
 }
@@ -396,8 +400,8 @@ int32_t ari_roc_flush_cache_trbits(uint32_t ari_base)
 	/* clean the previous response state */
 	ari_clobber_response(ari_base);
 
-	return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS,
-			0U, 0U);
+	return ari_request_wait(ari_base, 0U,
+			(uint32_t)TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS, 0U, 0U);
 }
 
 int32_t ari_roc_flush_cache(uint32_t ari_base)
@@ -405,8 +409,8 @@ int32_t ari_roc_flush_cache(uint32_t ari_base)
 	/* clean the previous response state */
 	ari_clobber_response(ari_base);
 
-	return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY,
-			0U, 0U);
+	return ari_request_wait(ari_base, 0U,
+			(uint32_t)TEGRA_ARI_ROC_FLUSH_CACHE_ONLY, 0U, 0U);
 }
 
 int32_t ari_roc_clean_cache(uint32_t ari_base)
@@ -414,8 +418,8 @@ int32_t ari_roc_clean_cache(uint32_t ari_base)
 	/* clean the previous response state */
 	ari_clobber_response(ari_base);
 
-	return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY,
-			0U, 0U);
+	return ari_request_wait(ari_base, 0U,
+			(uint32_t)TEGRA_ARI_ROC_CLEAN_CACHE_ONLY, 0U, 0U);
 }
 
 uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data)
@@ -432,7 +436,7 @@ uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data)
 	ari_write_32(ari_base, (uint32_t)cmd, ARI_RESPONSE_DATA_LO);
 	ari_write_32(ari_base, (uint32_t)(cmd >> 32U), ARI_RESPONSE_DATA_HI);
 
-	ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MCA,
+	ret = ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_MCA,
 			       (uint32_t)mca_arg_data,
 			       (uint32_t)(mca_arg_data >> 32U));
 	if (ret == 0) {
@@ -473,7 +477,8 @@ int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx)
 		 * the ID, from the MC registers and update the internal GSC registers
 		 * of the CCPLEX.
 		 */
-		(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0U);
+		(void)ari_request_wait(ari_base, 0U,
+				(uint32_t)TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0U);
 	}
 
 	return ret;
@@ -487,7 +492,8 @@ void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx)
 	/*
 	 * The MCE will shutdown or restart the entire system
 	 */
-	(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, state_idx, 0U);
+	(void)ari_request_wait(ari_base, 0U,
+			(uint32_t)TEGRA_ARI_MISC_CCPLEX, state_idx, 0U);
 }
 
 int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req,
@@ -514,8 +520,8 @@ int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req,
 		val = (req_cmd == UNCORE_PERFMON_CMD_WRITE) ?
 			(uint32_t)*data : 0U;
 
-		ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_PERFMON, val,
-				       (uint32_t)req);
+		ret = ari_request_wait(ari_base, 0U,
+			(uint32_t)TEGRA_ARI_PERFMON, val, (uint32_t)req);
 		if (ret != 0) {
 			result = ret;
 		} else {
@@ -552,6 +558,7 @@ void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value)
 	} else {
 		/* clean the previous response state */
 		ari_clobber_response(ari_base);
-		(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, index, value);
+		(void)ari_request_wait(ari_base, 0U,
+			(uint32_t)TEGRA_ARI_MISC_CCPLEX, index, value);
 	}
 }

plat/nvidia/tegra/soc/t186/drivers/mce/mce.c

@@ -170,12 +170,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 	cpu_ari_base = mce_get_curr_cpu_ari_base();
 
 	switch (cmd) {
-	case MCE_CMD_ENTER_CSTATE:
+	case (uint64_t)MCE_CMD_ENTER_CSTATE:
 		ret = ops->enter_cstate(cpu_ari_base, arg0, arg1);
 
 		break;
 
-	case MCE_CMD_UPDATE_CSTATE_INFO:
+	case (uint64_t)MCE_CMD_UPDATE_CSTATE_INFO:
 		/*
 		 * get the parameters required for the update cstate info
 		 * command
@@ -194,12 +194,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 
 		break;
 
-	case MCE_CMD_UPDATE_CROSSOVER_TIME:
+	case (uint64_t)MCE_CMD_UPDATE_CROSSOVER_TIME:
 		ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1);
 
 		break;
 
-	case MCE_CMD_READ_CSTATE_STATS:
+	case (uint64_t)MCE_CMD_READ_CSTATE_STATS:
 		ret64 = ops->read_cstate_stats(cpu_ari_base, arg0);
 
 		/* update context to return cstate stats value */
@@ -208,12 +208,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 
 		break;
 
-	case MCE_CMD_WRITE_CSTATE_STATS:
+	case (uint64_t)MCE_CMD_WRITE_CSTATE_STATS:
 		ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1);
 
 		break;
 
-	case MCE_CMD_IS_CCX_ALLOWED:
+	case (uint64_t)MCE_CMD_IS_CCX_ALLOWED:
 		ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1);
 
 		/* update context to return CCx status value */
@@ -221,7 +221,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 
 		break;
 
-	case MCE_CMD_IS_SC7_ALLOWED:
+	case (uint64_t)MCE_CMD_IS_SC7_ALLOWED:
 		ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1);
 
 		/* update context to return SC7 status value */
@@ -230,17 +230,17 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 
 		break;
 
-	case MCE_CMD_ONLINE_CORE:
+	case (uint64_t)MCE_CMD_ONLINE_CORE:
 		ret = ops->online_core(cpu_ari_base, arg0);
 
 		break;
 
-	case MCE_CMD_CC3_CTRL:
+	case (uint64_t)MCE_CMD_CC3_CTRL:
 		ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2);
 
 		break;
 
-	case MCE_CMD_ECHO_DATA:
+	case (uint64_t)MCE_CMD_ECHO_DATA:
 		ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_ECHO,
 				arg0);
 
@@ -252,7 +252,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 
 		break;
 
-	case MCE_CMD_READ_VERSIONS:
+	case (uint64_t)MCE_CMD_READ_VERSIONS:
 		ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION,
 			arg0);
 
@@ -265,7 +265,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 
 		break;
 
-	case MCE_CMD_ENUM_FEATURES:
+	case (uint64_t)MCE_CMD_ENUM_FEATURES:
 		ret64 = ops->call_enum_misc(cpu_ari_base,
 				TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0);
 
@@ -274,22 +274,22 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 
 		break;
 
-	case MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
+	case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
 		ret = ops->roc_flush_cache_trbits(cpu_ari_base);
 
 		break;
 
-	case MCE_CMD_ROC_FLUSH_CACHE:
+	case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE:
 		ret = ops->roc_flush_cache(cpu_ari_base);
 
 		break;
 
-	case MCE_CMD_ROC_CLEAN_CACHE:
+	case (uint64_t)MCE_CMD_ROC_CLEAN_CACHE:
 		ret = ops->roc_clean_cache(cpu_ari_base);
 
 		break;
 
-	case MCE_CMD_ENUM_READ_MCA:
+	case (uint64_t)MCE_CMD_ENUM_READ_MCA:
 		ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
 
 		/* update context to return MCA data/error */
@@ -299,7 +299,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 
 		break;
 
-	case MCE_CMD_ENUM_WRITE_MCA:
+	case (uint64_t)MCE_CMD_ENUM_WRITE_MCA:
 		ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
 
 		/* update context to return MCA error */
@@ -309,7 +309,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 		break;
 
 #if ENABLE_CHIP_VERIFICATION_HARNESS
-	case MCE_CMD_ENABLE_LATIC:
+	case (uint64_t)MCE_CMD_ENABLE_LATIC:
 		/*
 		 * This call is not for production use. The constant value,
 		 * 0xFFFF0000, is specific to allowing for enabling LATIC on
@@ -327,14 +327,14 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 		break;
 #endif
 
-	case MCE_CMD_UNCORE_PERFMON_REQ:
+	case (uint64_t)MCE_CMD_UNCORE_PERFMON_REQ:
 		ret = ops->read_write_uncore_perfmon(cpu_ari_base, arg0, &arg1);
 
 		/* update context to return data */
 		write_ctx_reg(gp_regs, CTX_GPREG_X1, (arg1));
 		break;
 
-	case MCE_CMD_MISC_CCPLEX:
+	case (uint64_t)MCE_CMD_MISC_CCPLEX:
 		ops->misc_ccplex(cpu_ari_base, arg0, arg1);
 
 		break;

plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c

@@ -30,7 +30,7 @@ int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
 		ret = EINVAL;
 	} else {
 		/* time (TSC ticks) until the core is expected to get a wake event */
-		nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time);
+		nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time);
 
 		/* set the core cstate */
 		val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
@@ -81,7 +81,7 @@ int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccp
 	val |= ((uint64_t)wake_mask << CSTATE_WAKE_MASK_SHIFT);
 
 	/* set the updated cstate info */
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
+	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
 
 	return 0;
 }
@@ -192,7 +192,7 @@ int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time
 				((uint64_t)state & MCE_SC7_ALLOWED_MASK);
 
 		/* issue command to check if SC7 is allowed */
-		nvg_set_request_data(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val);
+		nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val);
 
 		/* 1 = SC7 allowed, 0 = SC7 not allowed */
 		ret = (nvg_get_result() != 0ULL) ? 1 : 0;
@@ -222,7 +222,7 @@ int32_t nvg_online_core(uint32_t ari_base, uint32_t core)
 			ret = EINVAL;
 		} else {
 			/* get a core online */
-			nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE,
+			nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE,
 				((uint64_t)core & MCE_CORE_ID_MASK));
 		}
 	}
@@ -250,7 +250,7 @@ int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t en
 		((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
 		((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
 
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val);
+	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val);
 
 	return 0;
 }

plat/nvidia/tegra/soc/t186/plat_memctrl.c

@@ -206,11 +206,11 @@ const static mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = {
  ******************************************************************************/
 static tegra_mc_settings_t tegra186_mc_settings = {
 	.streamid_override_cfg = tegra186_streamid_override_regs,
-	.num_streamid_override_cfgs = ARRAY_SIZE(tegra186_streamid_override_regs),
+	.num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_override_regs),
 	.streamid_security_cfg = tegra186_streamid_sec_cfgs,
-	.num_streamid_security_cfgs = ARRAY_SIZE(tegra186_streamid_sec_cfgs),
+	.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_sec_cfgs),
 	.txn_override_cfg = tegra186_txn_override_cfgs,
-	.num_txn_override_cfgs = ARRAY_SIZE(tegra186_txn_override_cfgs)
+	.num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_txn_override_cfgs)
 };
 
 /*******************************************************************************

plat/nvidia/tegra/soc/t186/plat_psci_handlers.c

@@ -109,7 +109,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 
 		/* Enter CPU idle/powerdown */
 		val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
-			TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7;
+			(uint32_t)TEGRA_ARI_CORE_C6 : (uint32_t)TEGRA_ARI_CORE_C7;
 		(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
 				tegra_percpu_data[cpu].wake_time, 0U);
 
@@ -134,8 +134,8 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 		tegra_smmu_save_context((uintptr_t)smmu_ctx_base);
 
 		/* Prepare for system suspend */
-		cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7;
-		cstate_info.system = TEGRA_ARI_SYSTEM_SC7;
+		cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC7;
+		cstate_info.system = (uint32_t)TEGRA_ARI_SYSTEM_SC7;
 		cstate_info.system_state_force = 1;
 		cstate_info.update_wake_mask = 1;
 		mce_update_cstate_info(&cstate_info);
@@ -143,14 +143,14 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 		do {
 			val = (uint32_t)mce_command_handler(
 					(uint64_t)MCE_CMD_IS_SC7_ALLOWED,
-					TEGRA_ARI_CORE_C7,
+					(uint64_t)TEGRA_ARI_CORE_C7,
 					MCE_CORE_SLEEP_TIME_INFINITE,
 					0U);
 		} while (val == 0U);
 
 		/* Instruct the MCE to enter system suspend state */
 		(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
-			TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
+			(uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
 	} else {
 		; /* do nothing */
 	}
@@ -243,12 +243,12 @@ static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *
  * Platform handler to calculate the proper target power level at the
  * specified affinity level
  ******************************************************************************/
-plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
+plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
 					     const plat_local_state_t *states,
 					     uint32_t ncpu)
 {
 	plat_local_state_t target = PSCI_LOCAL_STATE_RUN;
-	int cpu = plat_my_core_pos();
+	uint32_t cpu = plat_my_core_pos();
 
 	/* System Suspend */
 	if ((lvl == (uint32_t)MPIDR_AFFLVL2) &&
@@ -342,7 +342,7 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 	 */
 	if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) {
 
-		cstate_info.cluster = TEGRA_ARI_CLUSTER_CC1;
+		cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC1;
 		cstate_info.update_wake_mask = 1;
 		mce_update_cstate_info(&cstate_info);
 	}
@@ -369,8 +369,8 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 		 * and SC7 for SC7 entry which may not be requested by
 		 * non-secure SW which controls idle states.
 		 */
-		cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7;
-		cstate_info.system = TEGRA_ARI_SYSTEM_SC1;
+		cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC7;
+		cstate_info.system = (uint32_t)TEGRA_ARI_SYSTEM_SC1;
 		cstate_info.update_wake_mask = 1;
 		mce_update_cstate_info(&cstate_info);
 	}
@@ -390,8 +390,8 @@ int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
 	}
 
 	/* Turn off CPU */
-	(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7,
-			MCE_CORE_SLEEP_TIME_INFINITE, 0U);
+	(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
+			(uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
 
 	return PSCI_E_SUCCESS;
 }
@@ -399,7 +399,7 @@ int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
 __dead2 void tegra_soc_prepare_system_off(void)
 {
 	/* power off the entire system */
-	mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF);
+	mce_enter_ccplex_state((uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF);
 
 	wfi();
 
@@ -411,7 +411,7 @@ __dead2 void tegra_soc_prepare_system_off(void)
 
 int32_t tegra_soc_prepare_system_reset(void)
 {
-	mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT);
+	mce_enter_ccplex_state((uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT);
 
 	return PSCI_E_SUCCESS;
 }

plat/nvidia/tegra/soc/t210/drivers/se/se_private.h

@@ -85,23 +85,23 @@
 
 #define DRBG_MODE_SHIFT				0
 #define DRBG_MODE_NORMAL		\
-		((0UL) << DRBG_MODE_SHIFT)
+		((0U) << DRBG_MODE_SHIFT)
 #define DRBG_MODE_FORCE_INSTANTION  \
-		((1UL) << DRBG_MODE_SHIFT)
+		((1U) << DRBG_MODE_SHIFT)
 #define DRBG_MODE_FORCE_RESEED	  \
-		((2UL) << DRBG_MODE_SHIFT)
+		((2U) << DRBG_MODE_SHIFT)
 #define SE_RNG_CONFIG_MODE(x)   \
-		((x) & ((0x3UL) << DRBG_MODE_SHIFT))
+		((x) & ((0x3U) << DRBG_MODE_SHIFT))
 
 #define DRBG_SRC_SHIFT				2
 #define DRBG_SRC_NONE	   \
-		((0UL) << DRBG_SRC_SHIFT)
+		((0U) << DRBG_SRC_SHIFT)
 #define DRBG_SRC_ENTROPY	\
-		((1UL) << DRBG_SRC_SHIFT)
+		((1U) << DRBG_SRC_SHIFT)
 #define DRBG_SRC_LFSR	   \
-		((2UL) << DRBG_SRC_SHIFT)
+		((2U) << DRBG_SRC_SHIFT)
 #define SE_RNG_SRC_CONFIG_MODE(x)   \
-		((x) & ((0x3UL) << DRBG_SRC_SHIFT))
+		((x) & ((0x3U) << DRBG_SRC_SHIFT))
 
 /* DRBG random number generator entropy config */
 #define SE_RNG_SRC_CONFIG_REG_OFFSET		0x344U

plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c

@@ -20,7 +20,7 @@
  * Constants and Macros
  ******************************************************************************/
 
-#define TIMEOUT_100MS	100UL	// Timeout in 100ms
+#define TIMEOUT_100MS	100U	// Timeout in 100ms
 
 /*******************************************************************************
  * Data structure and global variables