From abbffe98ed6a2fff519cc5590b947c9751cdd235 Mon Sep 17 00:00:00 2001 From: Isla Mitchell <isla.mitchell@arm.com> Date: Thu, 3 Aug 2017 16:04:46 +0100 Subject: [PATCH] Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com> --- include/lib/cpus/aarch64/cortex_a76.h | 22 +++++++++++ include/lib/cpus/aarch64/cortex_ares.h | 22 +++++++++++ lib/cpus/aarch64/cortex_a76.S | 51 ++++++++++++++++++++++++++ lib/cpus/aarch64/cortex_ares.S | 51 ++++++++++++++++++++++++++ plat/arm/board/fvp/platform.mk | 4 +- 5 files changed, 149 insertions(+), 1 deletion(-) create mode 100644 include/lib/cpus/aarch64/cortex_a76.h create mode 100644 include/lib/cpus/aarch64/cortex_ares.h create mode 100644 lib/cpus/aarch64/cortex_a76.S create mode 100644 lib/cpus/aarch64/cortex_ares.S diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h new file mode 100644 index 000000000..de6288d8f --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_A76_H__ +#define __CORTEX_A76_H__ + +/* Cortex-A76 MIDR for revision 0 */ +#define CORTEX_A76_MIDR 0x410fd0b0 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ +#define CORTEX_A76_CORE_PWRDN_EN_MASK 0x1 + +#endif /* __CORTEX_A76_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_ares.h b/include/lib/cpus/aarch64/cortex_ares.h new file mode 100644 index 000000000..680811cf2 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_ares.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_ARES_H__ +#define __CORTEX_ARES_H__ + +/* Cortex-ARES MIDR for revision 0 */ +#define CORTEX_ARES_MIDR 0x410fd0c0 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ +#define CORTEX_ARES_CORE_PWRDN_EN_MASK 0x1 + +#endif /* __CORTEX_ARES_H__ */ diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S new file mode 100644 index 000000000..3a41802f4 --- /dev/null +++ b/lib/cpus/aarch64/cortex_a76.S @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <bl_common.h> +#include <cortex_a76.h> +#include <cpu_macros.S> +#include <plat_macros.S> + + /* --------------------------------------------- + * HW will do the cache maintenance while powering down + * --------------------------------------------- + */ +func cortex_a76_core_pwr_dwn + /* --------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------- + */ + mrs x0, CORTEX_A76_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A76_CORE_PWRDN_EN_MASK + msr CORTEX_A76_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_a76_core_pwr_dwn + + /* --------------------------------------------- + * This function provides cortex_a76 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a76_regs, "aS" +cortex_a76_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a76_cpu_reg_dump + adr x6, cortex_a76_regs + mrs x8, CORTEX_A76_CPUECTLR_EL1 + ret +endfunc cortex_a76_cpu_reg_dump + +declare_cpu_ops cortex_a76, CORTEX_A76_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_a76_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_ares.S b/lib/cpus/aarch64/cortex_ares.S new file mode 100644 index 000000000..98e904406 --- /dev/null +++ b/lib/cpus/aarch64/cortex_ares.S @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <bl_common.h> +#include <cortex_ares.h> +#include <cpu_macros.S> +#include <plat_macros.S> + + /* --------------------------------------------- + * HW will do the cache maintenance while powering down + * --------------------------------------------- + */ +func cortex_ares_core_pwr_dwn + /* --------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------- + */ + mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK + msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_ares_core_pwr_dwn + + /* --------------------------------------------- + * This function provides cortex_ares specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_ares_regs, "aS" +cortex_ares_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_ares_cpu_reg_dump + adr x6, cortex_ares_regs + mrs x8, CORTEX_ARES_CPUECTLR_EL1 + ret +endfunc cortex_ares_cpu_reg_dump + +declare_cpu_ops cortex_ares, CORTEX_ARES_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_ares_core_pwr_dwn diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index f807dc6e4..2a09bba56 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -114,7 +114,9 @@ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a72.S \ lib/cpus/aarch64/cortex_a73.S \ - lib/cpus/aarch64/cortex_a75.S + lib/cpus/aarch64/cortex_a75.S \ + lib/cpus/aarch64/cortex_a76.S \ + lib/cpus/aarch64/cortex_ares.S else FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S endif -- GitLab