Skip to content
GitLab
Menu
Projects
Groups
Snippets
Help
Projects
Groups
Snippets
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Sign in / Register
Toggle navigation
Menu
Open sidebar
adam.huang
Arm Trusted Firmware
Commits
ac1adfde
Commit
ac1adfde
authored
5 years ago
by
Soby Mathew
Committed by
TrustedFirmware Code Review
5 years ago
Browse files
Options
Download
Plain Diff
Merge "rockchip: px30: Fix build error" into integration
parents
41293407
8a079e88
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
plat/rockchip/px30/drivers/pmu/pmu.c
+3
-3
plat/rockchip/px30/drivers/pmu/pmu.c
with
3 additions
and
3 deletions
+3
-3
plat/rockchip/px30/drivers/pmu/pmu.c
View file @
ac1adfde
...
...
@@ -626,13 +626,13 @@ static void pvtm_32k_config(void)
/* select pvtm as 32k source */
mmio_write_32
(
PMUCRU_BASE
+
CRU_PMU_CLKSELS_CON
(
0
),
BITS_WITH_WMASK
(
1
,
0x3
,
14
));
BITS_WITH_WMASK
(
1
,
0x3
U
,
14
));
}
static
void
pvtm_32k_config_restore
(
void
)
{
mmio_write_32
(
PMUCRU_BASE
+
CRU_PMU_CLKSELS_CON
(
0
),
ddr_data
.
pmu_cru_clksel_con0
|
BITS_WMSK
(
0x3
,
14
));
ddr_data
.
pmu_cru_clksel_con0
|
BITS_WMSK
(
0x3
U
,
14
));
mmio_write_32
(
PMUGRF_BASE
+
PMUGRF_PVTM_CON0
,
WITH_16BITS_WMSK
(
ddr_data
.
pgrf_pvtm_con
[
0
]));
...
...
@@ -869,7 +869,7 @@ static inline void pm_pll_wait_lock(uint32_t pll_base, uint32_t pll_id)
static
inline
void
pll_pwr_ctr
(
uint32_t
pll_base
,
uint32_t
pll_id
,
uint32_t
pd
)
{
mmio_write_32
(
pll_base
+
PLL_CON
(
1
),
BITS_WITH_WMASK
(
1
,
1
,
15
));
BITS_WITH_WMASK
(
1
,
1
U
,
15
));
if
(
pd
)
mmio_write_32
(
pll_base
+
PLL_CON
(
1
),
BITS_WITH_WMASK
(
1
,
1
,
14
));
...
...
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment
Menu
Projects
Groups
Snippets
Help