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Commit ac893456 authored by Manish Pandey's avatar Manish Pandey Committed by TrustedFirmware Code Review
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Merge changes from topic "tegra-downstream-01242020" into integration 

* changes:
  Tegra186: memctrl: lock stream id security config
  Tegra194: remove support for simulated system suspend
  Tegra194: mce: fix multiple MISRA issues
  Tegra: bpmp: fix multiple MISRA issues
  Tegra194: se: fix multiple MISRA issues
  Tegra: compile PMC driver for Tegra132/Tegra210 platforms
  Tegra: memctrl_v2: remove weakly defined TZDRAM setup handler
  Tegra: remove weakly defined per-platform SiP handler
  Tegra: remove weakly defined PSCI platform handlers
  Tegra: remove weakly defined platform setup handlers
  Tegra: per-SoC DRAM base values
parents 235c8174 029b45d1
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plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
View file @ ac893456
...@@ -19,123 +19,124 @@ ...@@ -19,123 +19,124 @@
* occur when there is only new functionality. * occur when there is only new functionality.
*/ */
enum { enum {
TEGRA_NVG_VERSION_MAJOR = 6, TEGRA_NVG_VERSION_MAJOR = U(6),
TEGRA_NVG_VERSION_MINOR = 6 TEGRA_NVG_VERSION_MINOR = U(6)
}; };
typedef enum { typedef enum {
TEGRA_NVG_CHANNEL_VERSION = 0, TEGRA_NVG_CHANNEL_VERSION = U(0),
TEGRA_NVG_CHANNEL_POWER_PERF = 1, TEGRA_NVG_CHANNEL_POWER_PERF = U(1),
TEGRA_NVG_CHANNEL_POWER_MODES = 2, TEGRA_NVG_CHANNEL_POWER_MODES = U(2),
TEGRA_NVG_CHANNEL_WAKE_TIME = 3, TEGRA_NVG_CHANNEL_WAKE_TIME = U(3),
TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, TEGRA_NVG_CHANNEL_CSTATE_INFO = U(4),
TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = U(5),
TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = U(6),
TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = U(8),
TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = U(10),
TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = U(11),
TEGRA_NVG_CHANNEL_NUM_CORES = 20, TEGRA_NVG_CHANNEL_NUM_CORES = U(20),
TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID = 21, TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID = U(21),
TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING = 22, TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING = U(22),
TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR = 23, TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR = U(23),
TEGRA_NVG_CHANNEL_SHUTDOWN = 42, TEGRA_NVG_CHANNEL_SHUTDOWN = U(42),
TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = U(43),
TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, TEGRA_NVG_CHANNEL_ONLINE_CORE = U(44),
TEGRA_NVG_CHANNEL_CC3_CTRL = 45, TEGRA_NVG_CHANNEL_CC3_CTRL = U(45),
TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = U(49),
TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = U(50),
TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = U(53),
TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, TEGRA_NVG_CHANNEL_SECURITY_CONFIG = U(54),
TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, TEGRA_NVG_CHANNEL_DEBUG_CONFIG = U(55),
TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = U(56),
TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = U(57),
TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = U(58),
TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = U(59),
TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60, TEGRA_NVG_CHANNEL_DDA_MCF_ISO = U(60),
TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61, TEGRA_NVG_CHANNEL_DDA_MCF_SISO = U(61),
TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62, TEGRA_NVG_CHANNEL_DDA_MCF_NISO = U(62),
TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63, TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = U(63),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64, TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = U(64),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65, TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = U(65),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66, TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = U(66),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67, TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = U(67),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68, TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = U(68),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69, TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = U(69),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70, TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = U(70),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71, TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = U(71),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72, TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = U(72),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73, TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = U(73),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74, TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = U(74),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75, TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = U(75),
TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76, TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = U(76),
TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77, TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = U(77),
TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78, TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = U(78),
TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79, TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = U(79),
TEGRA_NVG_CHANNEL_LAST_INDEX TEGRA_NVG_CHANNEL_LAST_INDEX
} tegra_nvg_channel_id_t; } tegra_nvg_channel_id_t;
typedef enum { typedef enum {
NVG_STAT_QUERY_SC7_ENTRIES = 1, NVG_STAT_QUERY_SC7_ENTRIES = U(1),
NVG_STAT_QUERY_CC6_ENTRIES = 6, NVG_STAT_QUERY_CC6_ENTRIES = U(6),
NVG_STAT_QUERY_CG7_ENTRIES = 7, NVG_STAT_QUERY_CG7_ENTRIES = U(7),
NVG_STAT_QUERY_C6_ENTRIES = 10, NVG_STAT_QUERY_C6_ENTRIES = U(10),
NVG_STAT_QUERY_C7_ENTRIES = 14, NVG_STAT_QUERY_C7_ENTRIES = U(14),
NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, NVG_STAT_QUERY_SC7_RESIDENCY_SUM = U(32),
NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, NVG_STAT_QUERY_CC6_RESIDENCY_SUM = U(41),
NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, NVG_STAT_QUERY_CG7_RESIDENCY_SUM = U(46),
NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, NVG_STAT_QUERY_C6_RESIDENCY_SUM = U(51),
NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56, NVG_STAT_QUERY_C7_RESIDENCY_SUM = U(56),
NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM = 60, NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM = U(60),
NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM = 61, NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM = U(61),
NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM = 62, NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM = U(62),
NVG_STAT_QUERY_C6_ENTRY_TIME_SUM = 63, NVG_STAT_QUERY_C6_ENTRY_TIME_SUM = U(63),
NVG_STAT_QUERY_C7_ENTRY_TIME_SUM = 64, NVG_STAT_QUERY_C7_ENTRY_TIME_SUM = U(64),
NVG_STAT_QUERY_SC7_EXIT_TIME_SUM = 70, NVG_STAT_QUERY_SC7_EXIT_TIME_SUM = U(70),
NVG_STAT_QUERY_CC6_EXIT_TIME_SUM = 71, NVG_STAT_QUERY_CC6_EXIT_TIME_SUM = U(71),
NVG_STAT_QUERY_CG7_EXIT_TIME_SUM = 72, NVG_STAT_QUERY_CG7_EXIT_TIME_SUM = U(72),
NVG_STAT_QUERY_C6_EXIT_TIME_SUM = 73, NVG_STAT_QUERY_C6_EXIT_TIME_SUM = U(73),
NVG_STAT_QUERY_C7_EXIT_TIME_SUM = 74, NVG_STAT_QUERY_C7_EXIT_TIME_SUM = U(74),
NVG_STAT_QUERY_SC7_ENTRY_LAST = 80, NVG_STAT_QUERY_SC7_ENTRY_LAST = U(80),
NVG_STAT_QUERY_CC6_ENTRY_LAST = 81, NVG_STAT_QUERY_CC6_ENTRY_LAST = U(81),
NVG_STAT_QUERY_CG7_ENTRY_LAST = 82, NVG_STAT_QUERY_CG7_ENTRY_LAST = U(82),
NVG_STAT_QUERY_C6_ENTRY_LAST = 83, NVG_STAT_QUERY_C6_ENTRY_LAST = U(83),
NVG_STAT_QUERY_C7_ENTRY_LAST = 84, NVG_STAT_QUERY_C7_ENTRY_LAST = U(84),
NVG_STAT_QUERY_SC7_EXIT_LAST = 90, NVG_STAT_QUERY_SC7_EXIT_LAST = U(90),
NVG_STAT_QUERY_CC6_EXIT_LAST = 91, NVG_STAT_QUERY_CC6_EXIT_LAST = U(91),
NVG_STAT_QUERY_CG7_EXIT_LAST = 92, NVG_STAT_QUERY_CG7_EXIT_LAST = U(92),
NVG_STAT_QUERY_C6_EXIT_LAST = 93, NVG_STAT_QUERY_C6_EXIT_LAST = U(93),
NVG_STAT_QUERY_C7_EXIT_LAST = 94 NVG_STAT_QUERY_C7_EXIT_LAST = U(94)
} tegra_nvg_stat_query_t; } tegra_nvg_stat_query_t;
typedef enum { typedef enum {
TEGRA_NVG_CORE_C0 = 0, TEGRA_NVG_CORE_C0 = U(0),
TEGRA_NVG_CORE_C1 = 1, TEGRA_NVG_CORE_C1 = U(1),
TEGRA_NVG_CORE_C6 = 6, TEGRA_NVG_CORE_C6 = U(6),
TEGRA_NVG_CORE_C7 = 7, TEGRA_NVG_CORE_C7 = U(7),
TEGRA_NVG_CORE_WARMRSTREQ = 8 TEGRA_NVG_CORE_WARMRSTREQ = U(8)
} tegra_nvg_core_sleep_state_t; } tegra_nvg_core_sleep_state_t;
typedef enum { typedef enum {
TEGRA_NVG_SHUTDOWN = 0U, TEGRA_NVG_SHUTDOWN = U(0),
TEGRA_NVG_REBOOT = 1U TEGRA_NVG_REBOOT = U(1)
} tegra_nvg_shutdown_reboot_state_t; } tegra_nvg_shutdown_reboot_state_t;
typedef enum { typedef enum {
TEGRA_NVG_CLUSTER_CC0 = 0, TEGRA_NVG_CLUSTER_CC0 = U(0),
TEGRA_NVG_CLUSTER_AUTO_CC1 = 1, TEGRA_NVG_CLUSTER_AUTO_CC1 = U(1),
TEGRA_NVG_CLUSTER_CC6 = 6 TEGRA_NVG_CLUSTER_CC6 = U(6)
} tegra_nvg_cluster_sleep_state_t; } tegra_nvg_cluster_sleep_state_t;
typedef enum { typedef enum {
TEGRA_NVG_CG_CG0 = 0, TEGRA_NVG_CG_CG0 = U(0),
TEGRA_NVG_CG_CG7 = 7 TEGRA_NVG_CG_CG7 = U(7)
} tegra_nvg_cluster_group_sleep_state_t; } tegra_nvg_cluster_group_sleep_state_t;
typedef enum { typedef enum {
TEGRA_NVG_SYSTEM_SC0 = 0, TEGRA_NVG_SYSTEM_SC0 = U(0),
TEGRA_NVG_SYSTEM_SC7 = 7, TEGRA_NVG_SYSTEM_SC7 = U(7),
TEGRA_NVG_SYSTEM_SC8 = 8 TEGRA_NVG_SYSTEM_SC8 = U(8)
} tegra_nvg_system_sleep_state_t; } tegra_nvg_system_sleep_state_t;
// --------------------------------------------------------------------------- // ---------------------------------------------------------------------------
...@@ -145,95 +146,95 @@ typedef enum { ...@@ -145,95 +146,95 @@ typedef enum {
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_version_channel_t { struct nvg_version_channel_t {
uint32_t minor_version : 32; uint32_t minor_version : U(32);
uint32_t major_version : 32; uint32_t major_version : U(32);
} bits; } bits;
} nvg_version_data_t; } nvg_version_data_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_power_perf_channel_t { struct nvg_power_perf_channel_t {
uint32_t perf_per_watt : 1; uint32_t perf_per_watt : U(1);
uint32_t reserved_31_1 : 31; uint32_t reserved_31_1 : U(31);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_power_perf_channel_t; } nvg_power_perf_channel_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_power_modes_channel_t { struct nvg_power_modes_channel_t {
uint32_t low_battery : 1; uint32_t low_battery : U(1);
uint32_t reserved_1_1 : 1; uint32_t reserved_1_1 : U(1);
uint32_t battery_save : 1; uint32_t battery_save : U(1);
uint32_t reserved_31_3 : 29; uint32_t reserved_31_3 : U(29);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_power_modes_channel_t; } nvg_power_modes_channel_t;
typedef union nvg_channel_1_data_u { typedef union nvg_channel_1_data_u {
uint64_t flat; uint64_t flat;
struct nvg_channel_1_data_s { struct nvg_channel_1_data_s {
uint32_t perf_per_watt_mode : 1; uint32_t perf_per_watt_mode : U(1);
uint32_t reserved_31_1 : 31; uint32_t reserved_31_1 : U(31);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_channel_1_data_t; } nvg_channel_1_data_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_ccplex_cache_control_channel_t { struct nvg_ccplex_cache_control_channel_t {
uint32_t gpu_ways : 5; uint32_t gpu_ways : U(5);
uint32_t reserved_7_5 : 3; uint32_t reserved_7_5 : U(3);
uint32_t gpu_only_ways : 5; uint32_t gpu_only_ways : U(5);
uint32_t reserved_31_13 : 19; uint32_t reserved_31_13 : U(19);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_ccplex_cache_control_channel_t; } nvg_ccplex_cache_control_channel_t;
typedef union nvg_channel_2_data_u { typedef union nvg_channel_2_data_u {
uint64_t flat; uint64_t flat;
struct nvg_channel_2_data_s { struct nvg_channel_2_data_s {
uint32_t reserved_1_0 : 2; uint32_t reserved_1_0 : U(2);
uint32_t battery_saver_mode : 1; uint32_t battery_saver_mode : U(1);
uint32_t reserved_31_3 : 29; uint32_t reserved_31_3 : U(29);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_channel_2_data_t; } nvg_channel_2_data_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_wake_time_channel_t { struct nvg_wake_time_channel_t {
uint32_t wake_time : 32; uint32_t wake_time : U(32);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_wake_time_channel_t; } nvg_wake_time_channel_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_cstate_info_channel_t { struct nvg_cstate_info_channel_t {
uint32_t cluster_state : 3; uint32_t cluster_state : U(3);
uint32_t reserved_6_3 : 4; uint32_t reserved_6_3 : U(4);
uint32_t update_cluster : 1; uint32_t update_cluster : U(1);
uint32_t cg_cstate : 3; uint32_t cg_cstate : U(3);
uint32_t reserved_14_11 : 4; uint32_t reserved_14_11 : U(4);
uint32_t update_cg : 1; uint32_t update_cg : U(1);
uint32_t system_cstate : 4; uint32_t system_cstate : U(4);
uint32_t reserved_22_20 : 3; uint32_t reserved_22_20 : U(3);
uint32_t update_system : 1; uint32_t update_system : U(1);
uint32_t reserved_30_24 : 7; uint32_t reserved_30_24 : U(7);
uint32_t update_wake_mask : 1; uint32_t update_wake_mask : U(1);
union { union {
uint32_t flat : 32; uint32_t flat : U(32);
struct { struct {
uint32_t vfiq : 1; uint32_t vfiq : U(1);
uint32_t virq : 1; uint32_t virq : U(1);
uint32_t fiq : 1; uint32_t fiq : U(1);
uint32_t irq : 1; uint32_t irq : U(1);
uint32_t serror : 1; uint32_t serror : U(1);
uint32_t reserved_10_5 : 6; uint32_t reserved_10_5 : U(6);
uint32_t fiqout : 1; uint32_t fiqout : U(1);
uint32_t irqout : 1; uint32_t irqout : U(1);
uint32_t reserved_31_13 : 19; uint32_t reserved_31_13 : U(19);
} carmel; } carmel;
} wake_mask; } wake_mask;
} bits; } bits;
...@@ -242,183 +243,182 @@ typedef union { ...@@ -242,183 +243,182 @@ typedef union {
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_lower_bound_channel_t { struct nvg_lower_bound_channel_t {
uint32_t crossover_value : 32; uint32_t crossover_value : U(32);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_lower_bound_channel_t; } nvg_lower_bound_channel_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_cstate_stat_query_channel_t { struct nvg_cstate_stat_query_channel_t {
uint32_t unit_id : 4; uint32_t unit_id : U(4);
uint32_t reserved_15_4 : 12; uint32_t reserved_15_4 : U(12);
uint32_t stat_id : 16; uint32_t stat_id : U(16);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_cstate_stat_query_channel_t; } nvg_cstate_stat_query_channel_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_num_cores_channel_t { struct nvg_num_cores_channel_t {
uint32_t num_cores : 4; uint32_t num_cores : U(4);
uint32_t reserved_31_4 : 28; uint32_t reserved_31_4 : U(28);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_num_cores_channel_t; } nvg_num_cores_channel_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_unique_logical_id_channel_t { struct nvg_unique_logical_id_channel_t {
uint32_t unique_core_id : 3; uint32_t unique_core_id : U(3);
uint32_t reserved_31_3 : 29; uint32_t reserved_31_3 : U(29);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_unique_logical_id_channel_t; } nvg_unique_logical_id_channel_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_logical_to_physical_mappings_channel_t { struct nvg_logical_to_physical_mappings_channel_t {
uint32_t lcore0_pcore_id : 4; uint32_t lcore0_pcore_id : U(4);
uint32_t lcore1_pcore_id : 4; uint32_t lcore1_pcore_id : U(4);
uint32_t lcore2_pcore_id : 4; uint32_t lcore2_pcore_id : U(4);
uint32_t lcore3_pcore_id : 4; uint32_t lcore3_pcore_id : U(4);
uint32_t lcore4_pcore_id : 4; uint32_t lcore4_pcore_id : U(4);
uint32_t lcore5_pcore_id : 4; uint32_t lcore5_pcore_id : U(4);
uint32_t lcore6_pcore_id : 4; uint32_t lcore6_pcore_id : U(4);
uint32_t lcore7_pcore_id : 4; uint32_t lcore7_pcore_id : U(4);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_logical_to_physical_mappings_channel_t; } nvg_logical_to_physical_mappings_channel_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_logical_to_mpidr_channel_write_t { struct nvg_logical_to_mpidr_channel_write_t {
uint32_t lcore_id : 3; uint32_t lcore_id : U(3);
uint32_t reserved_31_3 : 29; uint32_t reserved_31_3 : U(29);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} write; } write;
struct nvg_logical_to_mpidr_channel_read_t { struct nvg_logical_to_mpidr_channel_read_t {
uint32_t mpidr : 32; uint32_t mpidr : U(32);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} read; } read;
} nvg_logical_to_mpidr_channel_t; } nvg_logical_to_mpidr_channel_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_is_sc7_allowed_channel_t { struct nvg_is_sc7_allowed_channel_t {
uint32_t is_sc7_allowed : 1; uint32_t is_sc7_allowed : U(1);
uint32_t reserved_31_1 : 31; uint32_t reserved_31_1 : U(31);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_is_sc7_allowed_channel_t; } nvg_is_sc7_allowed_channel_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_core_online_channel_t { struct nvg_core_online_channel_t {
uint32_t core_id : 4; uint32_t core_id : U(4);
uint32_t reserved_31_4 : 28; uint32_t reserved_31_4 : U(28);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_core_online_channel_t; } nvg_core_online_channel_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_cc3_control_channel_t { struct nvg_cc3_control_channel_t {
uint32_t freq_req : 9; uint32_t freq_req : U(9);
uint32_t reserved_30_9 : 22; uint32_t reserved_30_9 : U(22);
uint32_t enable : 1; uint32_t enable : U(1);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_cc3_control_channel_t; } nvg_cc3_control_channel_t;
typedef enum { typedef enum {
TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0, TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = U(0),
TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1, TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = U(1),
TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2, TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = U(2),
TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3, TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = U(3),
TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4, TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = U(4),
TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5, TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = U(5),
TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6, TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = U(6),
TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7, TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = U(7),
TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8, TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = U(8),
TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9, TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = U(9),
TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = U(10),
TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = U(11),
TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = U(12),
TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = U(13),
TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = U(14),
TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = U(15),
TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = U(16),
TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = U(17),
TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = U(18),
TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = U(19),
TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = U(20),
TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = U(21),
TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = U(22),
TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = U(23),
TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = U(24),
TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = U(25),
TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = U(26),
TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = U(27),
TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = U(28),
TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = U(29),
TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = U(30),
TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = U(31),
TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = U(32),
TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = U(33),
TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = U(34),
TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = U(35),
TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX
} tegra_nvg_channel_update_gsc_gsc_enum_t; } tegra_nvg_channel_update_gsc_gsc_enum_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_update_ccplex_gsc_channel_t { struct nvg_update_ccplex_gsc_channel_t {
uint32_t gsc_enum : 16; uint32_t gsc_enum : U(16);
uint32_t reserved_31_16 : 16; uint32_t reserved_31_16 : U(16);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_update_ccplex_gsc_channel_t; } nvg_update_ccplex_gsc_channel_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_security_config_channel_t { struct nvg_security_config_channel_t {
uint32_t strict_checking_enabled : 1; uint32_t strict_checking_enabled : U(1);
uint32_t strict_checking_locked : 1; uint32_t strict_checking_locked : U(1);
uint32_t reserved_31_2 : 30; uint32_t reserved_31_2 : U(30);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_security_config_t; } nvg_security_config_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_shutdown_channel_t { struct nvg_shutdown_channel_t {
uint32_t reboot : 1; uint32_t reboot : U(1);
uint32_t reserved_31_1 : 31; uint32_t reserved_31_1 : U(31);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_shutdown_t; } nvg_shutdown_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_debug_config_channel_t { struct nvg_debug_config_channel_t {
uint32_t enter_debug_state_on_mca : 1; uint32_t enter_debug_state_on_mca : U(1);
uint32_t reserved_31_1 : 31; uint32_t reserved_31_1 : U(31);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_debug_config_t; } nvg_debug_config_t;
typedef union { typedef union {
uint64_t flat; uint64_t flat;
struct nvg_hsm_error_ctrl_channel_t { struct nvg_hsm_error_ctrl_channel_t {
uint32_t uncorr : 1; uint32_t uncorr : U(1);
uint32_t corr : 1; uint32_t corr : U(1);
uint32_t reserved_31_2 : 30; uint32_t reserved_31_2 : U(30);
uint32_t reserved_63_32 : 32; uint32_t reserved_63_32 : U(32);
} bits; } bits;
} nvg_hsm_error_ctrl_channel_t; } nvg_hsm_error_ctrl_channel_t;
extern nvg_debug_config_t nvg_debug_config; extern nvg_debug_config_t nvg_debug_config;
#endif #endif /* T194_NVG_H */
plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
View file @ ac893456
...@@ -15,8 +15,8 @@ ...@@ -15,8 +15,8 @@
#include <t194_nvg.h> #include <t194_nvg.h>
#include <tegra_private.h> #include <tegra_private.h>
#define ID_AFR0_EL1_CACHE_OPS_SHIFT 12 #define ID_AFR0_EL1_CACHE_OPS_SHIFT U(12)
#define ID_AFR0_EL1_CACHE_OPS_MASK 0xFU #define ID_AFR0_EL1_CACHE_OPS_MASK U(0xF)
/* /*
* Reports the major and minor version of this interface. * Reports the major and minor version of this interface.
* *
...@@ -209,7 +209,7 @@ void nvg_enable_strict_checking_mode(void) ...@@ -209,7 +209,7 @@ void nvg_enable_strict_checking_mode(void)
uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET |
STRICT_CHECKING_LOCKED_SET); STRICT_CHECKING_LOCKED_SET);
nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params); nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
} }
#endif #endif
...@@ -221,7 +221,8 @@ void nvg_enable_strict_checking_mode(void) ...@@ -221,7 +221,8 @@ void nvg_enable_strict_checking_mode(void)
void nvg_system_reboot(void) void nvg_system_reboot(void)
{ {
/* issue command for reboot */ /* issue command for reboot */
nvg_set_request_data(TEGRA_NVG_CHANNEL_SHUTDOWN, TEGRA_NVG_REBOOT); nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SHUTDOWN,
(uint64_t)TEGRA_NVG_REBOOT);
} }
/* /*
...@@ -232,5 +233,6 @@ void nvg_system_reboot(void) ...@@ -232,5 +233,6 @@ void nvg_system_reboot(void)
void nvg_system_shutdown(void) void nvg_system_shutdown(void)
{ {
/* issue command for shutdown */ /* issue command for shutdown */
nvg_set_request_data(TEGRA_NVG_CHANNEL_SHUTDOWN, TEGRA_NVG_SHUTDOWN); nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SHUTDOWN,
(uint64_t)TEGRA_NVG_SHUTDOWN);
} }
plat/nvidia/tegra/soc/t194/drivers/se/se.c
View file @ ac893456
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
#include <drivers/delay_timer.h> #include <drivers/delay_timer.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/psci/psci.h> #include <lib/psci/psci.h>
#include <se.h>
#include <tegra_platform.h> #include <tegra_platform.h>
#include "se_private.h" #include "se_private.h"
...@@ -54,7 +55,7 @@ static bool tegra_se_is_operation_complete(void) ...@@ -54,7 +55,7 @@ static bool tegra_se_is_operation_complete(void)
*/ */
do { do {
val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS); val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
se_is_busy = !!(val & CTX_SAVE_AUTO_SE_BUSY); se_is_busy = ((val & CTX_SAVE_AUTO_SE_BUSY) != 0U);
/* sleep until SE finishes */ /* sleep until SE finishes */
if (se_is_busy) { if (se_is_busy) {
...@@ -186,7 +187,8 @@ int32_t tegra_se_suspend(void) ...@@ -186,7 +187,8 @@ int32_t tegra_se_suspend(void)
assert(tegra_bpmp_ipc_init() == 0); assert(tegra_bpmp_ipc_init() == 0);
/* Enable SE clock before SE context save */ /* Enable SE clock before SE context save */
tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE); ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
assert(ret == 0);
/* save SE registers */ /* save SE registers */
se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT); se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT);
...@@ -201,7 +203,8 @@ int32_t tegra_se_suspend(void) ...@@ -201,7 +203,8 @@ int32_t tegra_se_suspend(void)
} }
/* Disable SE clock after SE context save */ /* Disable SE clock after SE context save */
tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE); ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
assert(ret == 0);
return ret; return ret;
} }
...@@ -211,11 +214,14 @@ int32_t tegra_se_suspend(void) ...@@ -211,11 +214,14 @@ int32_t tegra_se_suspend(void)
*/ */
void tegra_se_resume(void) void tegra_se_resume(void)
{ {
int32_t ret = 0;
/* initialise communication channel with BPMP */ /* initialise communication channel with BPMP */
assert(tegra_bpmp_ipc_init() == 0); assert(tegra_bpmp_ipc_init() == 0);
/* Enable SE clock before SE context restore */ /* Enable SE clock before SE context restore */
tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE); ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
assert(ret == 0);
/* /*
* When TZ takes over after System Resume, TZ should first reconfigure * When TZ takes over after System Resume, TZ should first reconfigure
...@@ -229,5 +235,6 @@ void tegra_se_resume(void) ...@@ -229,5 +235,6 @@ void tegra_se_resume(void)
mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]); mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
/* Disable SE clock after SE context restore */ /* Disable SE clock after SE context restore */
tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE); ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
assert(ret == 0);
} }
plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
View file @ ac893456
...@@ -74,12 +74,12 @@ ...@@ -74,12 +74,12 @@
static inline uint32_t tegra_se_read_32(uint32_t offset) static inline uint32_t tegra_se_read_32(uint32_t offset)
{ {
return mmio_read_32(TEGRA_SE0_BASE + offset); return mmio_read_32((uint32_t)(TEGRA_SE0_BASE + offset));
} }
static inline void tegra_se_write_32(uint32_t offset, uint32_t val) static inline void tegra_se_write_32(uint32_t offset, uint32_t val)
{ {
mmio_write_32(TEGRA_SE0_BASE + offset, val); mmio_write_32((uint32_t)(TEGRA_SE0_BASE + offset), val);
} }
#endif /* SE_PRIVATE_H */ #endif /* SE_PRIVATE_H */
plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
View file @ ac893456
...@@ -44,14 +44,6 @@ static struct t19x_psci_percpu_data { ...@@ -44,14 +44,6 @@ static struct t19x_psci_percpu_data {
uint32_t wake_time; uint32_t wake_time;
} __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT]; } __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT];
/*
* tegra_fake_system_suspend acts as a boolean var controlling whether
* we are going to take fake system suspend code or normal system suspend code
* path. This variable is set inside the sip call handlers, when the kernel
* requests an SIP call to set the suspend debug flags.
*/
bool tegra_fake_system_suspend;
int32_t tegra_soc_validate_power_state(uint32_t power_state, int32_t tegra_soc_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state) psci_power_state_t *req_state)
{ {
...@@ -171,8 +163,6 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) ...@@ -171,8 +163,6 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
assert(ret == 0); assert(ret == 0);
} }
if (!tegra_fake_system_suspend) {
/* Prepare for system suspend */ /* Prepare for system suspend */
mce_update_cstate_info(&sc7_cstate_info); mce_update_cstate_info(&sc7_cstate_info);
...@@ -194,7 +184,6 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) ...@@ -194,7 +184,6 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
/* set system suspend state for house-keeping */ /* set system suspend state for house-keeping */
tegra194_set_system_suspend_entry(); tegra194_set_system_suspend_entry();
}
} else { } else {
; /* do nothing */ ; /* do nothing */
} }
...@@ -301,7 +290,6 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta ...@@ -301,7 +290,6 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta
uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
TEGRA194_STATE_ID_MASK; TEGRA194_STATE_ID_MASK;
uint64_t val; uint64_t val;
u_register_t ns_sctlr_el1;
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
/* /*
...@@ -313,35 +301,16 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta ...@@ -313,35 +301,16 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta
tegra194_get_cpu_reset_handler_size(); tegra194_get_cpu_reset_handler_size();
memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
(uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE);
/*
* In fake suspend mode, ensure that the loopback procedure
* towards system suspend exit is started, instead of calling
* WFI. This is done by disabling both MMU's of EL1 & El3
* and calling tegra_secure_entrypoint().
*/
if (tegra_fake_system_suspend) {
/*
* Disable EL1's MMU.
*/
ns_sctlr_el1 = read_sctlr_el1();
ns_sctlr_el1 &= (~((u_register_t)SCTLR_M_BIT));
write_sctlr_el1(ns_sctlr_el1);
/*
* Disable MMU to power up the CPU in a "clean"
* state
*/
disable_mmu_el3();
tegra_secure_entrypoint();
panic();
}
} }
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
} }
int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
{
return PSCI_E_NOT_SUPPORTED;
}
int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
{ {
uint64_t target_cpu = mpidr & MPIDR_CPU_MASK; uint64_t target_cpu = mpidr & MPIDR_CPU_MASK;
......
plat/nvidia/tegra/soc/t194/plat_sip_calls.c
View file @ ac893456
/* /*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -18,12 +18,9 @@ ...@@ -18,12 +18,9 @@
#include <tegra_platform.h> #include <tegra_platform.h>
#include <stdbool.h> #include <stdbool.h>
extern bool tegra_fake_system_suspend;
/******************************************************************************* /*******************************************************************************
* Tegra194 SiP SMCs * Tegra194 SiP SMCs
******************************************************************************/ ******************************************************************************/
#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03U
/******************************************************************************* /*******************************************************************************
* This function is responsible for handling all T194 SiP calls * This function is responsible for handling all T194 SiP calls
...@@ -39,25 +36,11 @@ int32_t plat_sip_handler(uint32_t smc_fid, ...@@ -39,25 +36,11 @@ int32_t plat_sip_handler(uint32_t smc_fid,
{ {
int32_t ret = -ENOTSUP; int32_t ret = -ENOTSUP;
(void)smc_fid;
(void)x1; (void)x1;
(void)x4; (void)x4;
(void)cookie; (void)cookie;
(void)flags; (void)flags;
if (smc_fid == TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND) {
/*
* System suspend mode is set if the platform ATF is
* running on VDK and there is a debug SIP call. This mode
* ensures that the debug path is exercised, instead of
* regular code path to suit the pre-silicon platform needs.
* This includes replacing the call to WFI, with calls to
* system suspend exit procedures.
*/
if (tegra_platform_is_virt_dev_kit()) {
tegra_fake_system_suspend = true;
ret = 0;
}
}
return ret; return ret;
} }
plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
View file @ ac893456
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -184,6 +185,12 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, ...@@ -184,6 +185,12 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
return target; return target;
} }
int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
{
(void)cpu_state;
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
{ {
u_register_t mpidr = read_mpidr(); u_register_t mpidr = read_mpidr();
...@@ -412,6 +419,11 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) ...@@ -412,6 +419,11 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
} }
int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
{
return PSCI_E_NOT_SUPPORTED;
}
int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{ {
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
...@@ -567,5 +579,16 @@ int tegra_soc_prepare_system_reset(void) ...@@ -567,5 +579,16 @@ int tegra_soc_prepare_system_reset(void)
/* Wait 1 ms to make sure clock source/device logic is stabilized. */ /* Wait 1 ms to make sure clock source/device logic is stabilized. */
mdelay(1); mdelay(1);
/*
* Program the PMC in order to restart the system.
*/
tegra_pmc_system_reset();
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
} }
__dead2 void tegra_soc_prepare_system_off(void)
{
ERROR("Tegra System Off: operation not handled.\n");
panic();
}
plat/nvidia/tegra/soc/t210/plat_setup.c
View file @ ac893456
/* /*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -140,6 +141,22 @@ void plat_enable_console(int32_t id) ...@@ -140,6 +141,22 @@ void plat_enable_console(int32_t id)
} }
} }
/*******************************************************************************
* Return pointer to the BL31 params from previous bootloader
******************************************************************************/
struct tegra_bl31_params *plat_get_bl31_params(void)
{
return NULL;
}
/*******************************************************************************
* Return pointer to the BL31 platform params from previous bootloader
******************************************************************************/
plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
{
return NULL;
}
/******************************************************************************* /*******************************************************************************
* Handler for early platform setup * Handler for early platform setup
******************************************************************************/ ******************************************************************************/
...@@ -168,6 +185,9 @@ static const interrupt_prop_t tegra210_interrupt_props[] = { ...@@ -168,6 +185,9 @@ static const interrupt_prop_t tegra210_interrupt_props[] = {
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
}; };
/*******************************************************************************
* Handler for late platform setup
******************************************************************************/
void plat_late_platform_setup(void) void plat_late_platform_setup(void)
{ {
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
......
plat/nvidia/tegra/soc/t210/platform_t210.mk
View file @ ac893456
# #
# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. # Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
...@@ -33,6 +34,7 @@ BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ ...@@ -33,6 +34,7 @@ BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
${COMMON_DIR}/drivers/bpmp/bpmp.c \ ${COMMON_DIR}/drivers/bpmp/bpmp.c \
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \ ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \
${COMMON_DIR}/drivers/pmc/pmc.c \
${SOC_DIR}/plat_psci_handlers.c \ ${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_setup.c \ ${SOC_DIR}/plat_setup.c \
${SOC_DIR}/drivers/se/security_engine.c \ ${SOC_DIR}/drivers/se/security_engine.c \
......
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