From b0f2361a1a060b7b75181ffe3b99169f35312042 Mon Sep 17 00:00:00 2001
From: Marcin Wojtas <mw@semihalf.com>
Date: Tue, 17 Jul 2018 15:26:21 +0200
Subject: [PATCH] plat: marvell: a80x0: reconfigure CP0 PCIE0 windows
In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)
For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.
Change-Id: Ia8177194e542078772f90941eced81b231c16887
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
---
plat/marvell/a8k/a80x0/board/marvell_plat_config.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c
index 4948c9a33..7901dd225 100644
--- a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c
+++ b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c
@@ -86,7 +86,9 @@ struct addr_map_win iob_memory_map_cp0[] = {
/* PEX2_X1 window */
{0x00000000f8000000, 0x1000000, PEX2_TID},
/* PEX0_X4 window */
- {0x00000000f6000000, 0x1000000, PEX0_TID}
+ {0x00000000f6000000, 0x1000000, PEX0_TID},
+ {0x00000000c0000000, 0x30000000, PEX0_TID},
+ {0x0000000800000000, 0x100000000, PEX0_TID},
};
struct addr_map_win iob_memory_map_cp1[] = {
@@ -130,6 +132,8 @@ struct addr_map_win ccu_memory_map[] = {
{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
#else
{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
+ {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
+ {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
#endif
};
--
GitLab