diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index f0573903de5f920967612cdc470f05998e76a30b..0d0a9c66972b151993403417738b0d7db0011f18 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -16,6 +16,8 @@
 void stm32mp_save_boot_ctx_address(uintptr_t address);
 uintptr_t stm32mp_get_boot_ctx_address(void);
 
+bool stm32mp_is_single_core(void);
+
 /* Return the base address of the DDR controller */
 uintptr_t stm32mp_ddrctrl_base(void);
 
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index c334cd1e0f6c24c8d8569ff197ddf7b266f55a9b..38ebcef64c0d1a6b16ca470c320115bab79ff969 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -254,6 +254,30 @@ void stm32mp_print_boardinfo(void)
 	}
 }
 
+/* Return true when SoC provides a single Cortex-A7 core, and false otherwise */
+bool stm32mp_is_single_core(void)
+{
+	uint32_t part_number;
+	bool ret = false;
+
+	if (get_part_number(&part_number) < 0) {
+		ERROR("Invalid part number, assume single core chip");
+		return true;
+	}
+
+	switch (part_number) {
+	case STM32MP151A_PART_NB:
+	case STM32MP151C_PART_NB:
+		ret = true;
+		break;
+
+	default:
+		break;
+	}
+
+	return ret;
+}
+
 uint32_t stm32_iwdg_get_instance(uintptr_t base)
 {
 	switch (base) {