From b24ece54e040537599d3c94bb2b2f639bd5c2509 Mon Sep 17 00:00:00 2001 From: Vijayenthiran Subramaniam Date: Mon, 6 Apr 2020 13:54:50 +0530 Subject: [PATCH] gic multichip: add support for clayton GIC-Clayton supports multichip operation mode which allows it to connect upto 16 other GIC-Clayton instances. GIC-Clayton's multichip programming and operation remains same as GIC-600 with a minor change in the SPI_BLOCKS and SPI_BLOCK_MIN shifts to accommodate additional SPI ranges. So identify if the GIC v4 extension is enabled by the platform makefile and appropriately select the SPI_BLOCKS and SPI_BLOCK_MIN shifts. Change-Id: I95fd80ef16af6c7ca09e2335539187b133052d41 Signed-off-by: Vijayenthiran Subramaniam --- drivers/arm/gic/v3/gic600_multichip_private.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/arm/gic/v3/gic600_multichip_private.h b/drivers/arm/gic/v3/gic600_multichip_private.h index b0217b6d4..fe4134cba 100644 --- a/drivers/arm/gic/v3/gic600_multichip_private.h +++ b/drivers/arm/gic/v3/gic600_multichip_private.h @@ -24,11 +24,21 @@ /* GIC600 GICD multichip related shifts */ #define GICD_CHIPRx_ADDR_SHIFT 16 -#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10 -#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5 #define GICD_CHIPSR_RTS_SHIFT 4 #define GICD_DCHIPR_RT_OWNER_SHIFT 4 +/* + * If GIC v4 extension is enabled, then use SPI macros specific to GIC-Clayton. + * Other shifts and mask remains same between GIC-600 and GIC-Clayton. + */ +#if GIC_ENABLE_V4_EXTN +#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 9 +#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 3 +#else +#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10 +#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5 +#endif + #define GICD_CHIPSR_RTS_STATE_DISCONNECTED U(0) #define GICD_CHIPSR_RTS_STATE_UPDATING U(1) #define GICD_CHIPSR_RTS_STATE_CONSISTENT U(2) -- GitLab