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adam.huang
Arm Trusted Firmware
Commits
b3ccb0f2
Commit
b3ccb0f2
authored
Apr 26, 2017
by
davidcunado-arm
Committed by
GitHub
Apr 26, 2017
Browse files
Merge pull request #917 from soby-mathew/sm/sys_susp_css
CSS: Allow system suspend only via PSCI SYSTEM_SUSPEND API
parents
79199f70
abd2aba9
Changes
4
Show whitespace changes
Inline
Side-by-side
include/plat/arm/css/common/css_pm.h
View file @
b3ccb0f2
/*
/*
* Copyright (c) 2015-201
6
, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-201
7
, ARM Limited and Contributors. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* modification, are permitted provided that the following conditions are met:
...
@@ -35,11 +35,15 @@
...
@@ -35,11 +35,15 @@
#include <psci.h>
#include <psci.h>
#include <types.h>
#include <types.h>
/* System power domain at level 2, as currently implemented by CSS platforms */
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
/* Macros to read the CSS power domain state */
/* Macros to read the CSS power domain state */
#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]
#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]
#define CSS_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > ARM_PWR_LVL1) ?\
#define CSS_SYSTEM_PWR_STATE(state) \
(state)->pwr_domain_state[ARM_PWR_LVL2] : 0)
((PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) ?\
(state)->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] : 0)
int
css_pwr_domain_on
(
u_register_t
mpidr
);
int
css_pwr_domain_on
(
u_register_t
mpidr
);
void
css_pwr_domain_on_finish
(
const
psci_power_state_t
*
target_state
);
void
css_pwr_domain_on_finish
(
const
psci_power_state_t
*
target_state
);
...
...
plat/arm/board/juno/juno_pm.c
deleted
100644 → 0
View file @
79199f70
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <css_pm.h>
#include <plat_arm.h>
/*
* Custom `validate_power_state` handler for Juno. According to PSCI
* Specification, interrupts targeted to cores in PSCI CPU SUSPEND should
* be able to resume it. On Juno, when the system power domain is suspended,
* the GIC is also powered down. The SCP resumes the final core to be suspend
* when an external wake-up event is received. But the other cores cannot be
* woken up by a targeted interrupt, because GIC doesn't forward these
* interrupts to the SCP. Due to this hardware limitation, we down-grade PSCI
* CPU SUSPEND requests targeted to the system power domain level
* to cluster power domain level.
*
* The system power domain suspend on Juno is only supported only via
* PSCI SYSTEM SUSPEND API.
*/
static
int
juno_validate_power_state
(
unsigned
int
power_state
,
psci_power_state_t
*
req_state
)
{
int
rc
;
rc
=
arm_validate_power_state
(
power_state
,
req_state
);
/*
* Ensure that the system power domain level is never suspended
* via PSCI CPU SUSPEND API. Currently system suspend is only
* supported via PSCI SYSTEM SUSPEND API.
*/
req_state
->
pwr_domain_state
[
ARM_PWR_LVL2
]
=
ARM_LOCAL_STATE_RUN
;
return
rc
;
}
/*
* Custom `translate_power_state_by_mpidr` handler for Juno. Unlike in the
* `juno_validate_power_state`, we do not down-grade the system power
* domain level request in `power_state` as it will be used to query the
* PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
*/
static
int
juno_translate_power_state_by_mpidr
(
u_register_t
mpidr
,
unsigned
int
power_state
,
psci_power_state_t
*
output_state
)
{
return
arm_validate_power_state
(
power_state
,
output_state
);
}
/*******************************************************************************
* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
* platform will take care of registering the handlers with PSCI.
******************************************************************************/
plat_psci_ops_t
plat_arm_psci_pm_ops
=
{
.
pwr_domain_on
=
css_pwr_domain_on
,
.
pwr_domain_on_finish
=
css_pwr_domain_on_finish
,
.
pwr_domain_off
=
css_pwr_domain_off
,
.
cpu_standby
=
css_cpu_standby
,
.
pwr_domain_suspend
=
css_pwr_domain_suspend
,
.
pwr_domain_suspend_finish
=
css_pwr_domain_suspend_finish
,
.
system_off
=
css_system_off
,
.
system_reset
=
css_system_reset
,
.
validate_power_state
=
juno_validate_power_state
,
.
validate_ns_entrypoint
=
arm_validate_ns_entrypoint
,
.
get_sys_suspend_power_state
=
css_get_sys_suspend_power_state
,
.
translate_power_state_by_mpidr
=
juno_translate_power_state_by_mpidr
,
.
get_node_hw_state
=
css_node_hw_state
};
plat/arm/board/juno/platform.mk
View file @
b3ccb0f2
...
@@ -73,7 +73,6 @@ BL2U_SOURCES += ${JUNO_SECURITY_SOURCES}
...
@@ -73,7 +73,6 @@ BL2U_SOURCES += ${JUNO_SECURITY_SOURCES}
BL31_SOURCES
+=
lib/cpus/aarch64/cortex_a53.S
\
BL31_SOURCES
+=
lib/cpus/aarch64/cortex_a53.S
\
lib/cpus/aarch64/cortex_a57.S
\
lib/cpus/aarch64/cortex_a57.S
\
lib/cpus/aarch64/cortex_a72.S
\
lib/cpus/aarch64/cortex_a72.S
\
plat/arm/board/juno/juno_pm.c
\
plat/arm/board/juno/juno_topology.c
\
plat/arm/board/juno/juno_topology.c
\
${JUNO_GIC_SOURCES}
\
${JUNO_GIC_SOURCES}
\
${JUNO_INTERCONNECT_SOURCES}
\
${JUNO_INTERCONNECT_SOURCES}
\
...
...
plat/arm/css/common/css_pm.c
View file @
b3ccb0f2
/*
/*
* Copyright (c) 2015-201
6
, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-201
7
, ARM Limited and Contributors. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* modification, are permitted provided that the following conditions are met:
...
@@ -75,6 +75,13 @@ const unsigned int arm_pm_idle_states[] = {
...
@@ -75,6 +75,13 @@ const unsigned int arm_pm_idle_states[] = {
CASSERT
(
PLAT_MAX_PWR_LVL
>=
ARM_PWR_LVL1
,
CASSERT
(
PLAT_MAX_PWR_LVL
>=
ARM_PWR_LVL1
,
assert_max_pwr_lvl_supported_mismatch
);
assert_max_pwr_lvl_supported_mismatch
);
/*
* Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL
* assumed by the CSS layer.
*/
CASSERT
(
PLAT_MAX_PWR_LVL
<=
CSS_SYSTEM_PWR_DMN_LVL
,
assert_max_pwr_lvl_higher_than_css_sys_lvl
);
/*******************************************************************************
/*******************************************************************************
* Handler called when a power domain is about to be turned on. The
* Handler called when a power domain is about to be turned on. The
* level and mpidr determine the affinity instance.
* level and mpidr determine the affinity instance.
...
@@ -243,7 +250,7 @@ void css_get_sys_suspend_power_state(psci_power_state_t *req_state)
...
@@ -243,7 +250,7 @@ void css_get_sys_suspend_power_state(psci_power_state_t *req_state)
* System Suspend is supported only if the system power domain node
* System Suspend is supported only if the system power domain node
* is implemented.
* is implemented.
*/
*/
assert
(
PLAT_MAX_PWR_LVL
>
=
AR
M_PWR_LVL
2
);
assert
(
PLAT_MAX_PWR_LVL
=
=
CSS_SYSTE
M_PWR_
DMN_
LVL
);
for
(
i
=
ARM_PWR_LVL0
;
i
<=
PLAT_MAX_PWR_LVL
;
i
++
)
for
(
i
=
ARM_PWR_LVL0
;
i
<=
PLAT_MAX_PWR_LVL
;
i
++
)
req_state
->
pwr_domain_state
[
i
]
=
ARM_LOCAL_STATE_OFF
;
req_state
->
pwr_domain_state
[
i
]
=
ARM_LOCAL_STATE_OFF
;
...
@@ -257,6 +264,39 @@ int css_node_hw_state(u_register_t mpidr, unsigned int power_level)
...
@@ -257,6 +264,39 @@ int css_node_hw_state(u_register_t mpidr, unsigned int power_level)
return
css_scp_get_power_state
(
mpidr
,
power_level
);
return
css_scp_get_power_state
(
mpidr
,
power_level
);
}
}
/*
* The system power domain suspend is only supported only via
* PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
* will be downgraded to the lower level.
*/
static
int
css_validate_power_state
(
unsigned
int
power_state
,
psci_power_state_t
*
req_state
)
{
int
rc
;
rc
=
arm_validate_power_state
(
power_state
,
req_state
);
/*
* Ensure that the system power domain level is never suspended
* via PSCI CPU SUSPEND API. Currently system suspend is only
* supported via PSCI SYSTEM SUSPEND API.
*/
req_state
->
pwr_domain_state
[
CSS_SYSTEM_PWR_DMN_LVL
]
=
ARM_LOCAL_STATE_RUN
;
return
rc
;
}
/*
* Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the
* `css_validate_power_state`, we do not downgrade the system power
* domain level request in `power_state` as it will be used to query the
* PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
*/
static
int
css_translate_power_state_by_mpidr
(
u_register_t
mpidr
,
unsigned
int
power_state
,
psci_power_state_t
*
output_state
)
{
return
arm_validate_power_state
(
power_state
,
output_state
);
}
/*******************************************************************************
/*******************************************************************************
* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
* platform will take care of registering the handlers with PSCI.
* platform will take care of registering the handlers with PSCI.
...
@@ -270,7 +310,9 @@ plat_psci_ops_t plat_arm_psci_pm_ops = {
...
@@ -270,7 +310,9 @@ plat_psci_ops_t plat_arm_psci_pm_ops = {
.
pwr_domain_suspend_finish
=
css_pwr_domain_suspend_finish
,
.
pwr_domain_suspend_finish
=
css_pwr_domain_suspend_finish
,
.
system_off
=
css_system_off
,
.
system_off
=
css_system_off
,
.
system_reset
=
css_system_reset
,
.
system_reset
=
css_system_reset
,
.
validate_power_state
=
arm
_validate_power_state
,
.
validate_power_state
=
css
_validate_power_state
,
.
validate_ns_entrypoint
=
arm_validate_ns_entrypoint
,
.
validate_ns_entrypoint
=
arm_validate_ns_entrypoint
,
.
get_node_hw_state
=
css_node_hw_state
.
translate_power_state_by_mpidr
=
css_translate_power_state_by_mpidr
,
.
get_node_hw_state
=
css_node_hw_state
,
.
get_sys_suspend_power_state
=
css_get_sys_suspend_power_state
};
};
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