diff --git a/docs/diagrams/default_reset_code.png b/docs/diagrams/default_reset_code.png index e7e0d8556367b14bf004866a15a4a95b3a6777bc..d8675e4a3f81b7e8bfedfb9c39c48f7f9b286344 100644 Binary files a/docs/diagrams/default_reset_code.png and b/docs/diagrams/default_reset_code.png differ diff --git a/docs/diagrams/reset_code_flow.dia b/docs/diagrams/reset_code_flow.dia index 5de00dad08cfaa4b59060fa8198ff2e9e812bf1d..133c9cf69cb3e597d62aa30b55b0dfd0fe293065 100644 Binary files a/docs/diagrams/reset_code_flow.dia and b/docs/diagrams/reset_code_flow.dia differ diff --git a/docs/diagrams/reset_code_no_boot_type_check.png b/docs/diagrams/reset_code_no_boot_type_check.png index 8ce7e97ac286b0390b9092f57b8b574836b24d19..23e865f62f98d86556eb45c409eb8cac3fc156c0 100644 Binary files a/docs/diagrams/reset_code_no_boot_type_check.png and b/docs/diagrams/reset_code_no_boot_type_check.png differ diff --git a/docs/diagrams/reset_code_no_checks.png b/docs/diagrams/reset_code_no_checks.png index 8a02f0f828a3b7c7dbc99ba7f49ba2bb453c8e01..26a179bc535b4767334b70c6fe4f759ef8597607 100644 Binary files a/docs/diagrams/reset_code_no_checks.png and b/docs/diagrams/reset_code_no_checks.png differ diff --git a/docs/diagrams/reset_code_no_cpu_check.png b/docs/diagrams/reset_code_no_cpu_check.png index 8b05ea4d88e62f48cf06a678df7854e255332692..4150dbefeb191e3ea5e01859fcef8ea8e3f7f9c4 100644 Binary files a/docs/diagrams/reset_code_no_cpu_check.png and b/docs/diagrams/reset_code_no_cpu_check.png differ diff --git a/include/common/el3_common_macros.S b/include/common/el3_common_macros.S index 6f7136f94e1ba5aabb109c0a9a25c47663040f41..32df7d76346af0dffa9f68530ba3840c583ef460 100644 --- a/include/common/el3_common_macros.S +++ b/include/common/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -171,9 +171,19 @@ do_cold_boot: .endif /* _warm_boot_mailbox */ + /* --------------------------------------------------------------------- + * It is a cold boot. + * Perform any processor specific actions upon reset e.g. cache, TLB + * invalidations etc. + * --------------------------------------------------------------------- + */ + bl reset_handler + + el3_arch_init_common \_exception_vectors + .if \_secondary_cold_boot /* ------------------------------------------------------------- - * It is a cold boot. + * Check if this is a primary or secondary CPU cold boot. * The primary CPU will set up the platform while the * secondaries are placed in a platform-specific state until the * primary CPU performs the necessary actions to bring them out @@ -193,13 +203,10 @@ .endif /* _secondary_cold_boot */ /* --------------------------------------------------------------------- - * Perform any processor specific actions upon reset e.g. cache, TLB - * invalidations etc. + * Initialize memory now. Secondary CPU initialization won't get to this + * point. * --------------------------------------------------------------------- */ - bl reset_handler - - el3_arch_init_common \_exception_vectors .if \_init_memory bl platform_mem_init