From b78f25bf3d6761b9da0dba441c3e6d9ae651f7ff Mon Sep 17 00:00:00 2001
From: Sandrine Bailleux <sandrine.bailleux@arm.com>
Date: Wed, 7 May 2014 15:53:33 +0100
Subject: [PATCH] Do not route external abort and SError interrupts to EL3
The software running at a given exception level should handle
external aborts and SError interrupts itself.
Change-Id: Ic249fdf8472e0c64306ce3913562a2ac89c78627
---
bl1/aarch64/bl1_arch_setup.c | 6 ++----
bl31/aarch64/bl31_arch_setup.c | 6 ++----
docs/firmware-design.md | 4 +---
3 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c
index 5725bac12..34f36bbf6 100644
--- a/bl1/aarch64/bl1_arch_setup.c
+++ b/bl1/aarch64/bl1_arch_setup.c
@@ -46,11 +46,9 @@ void bl1_arch_setup(void)
isb();
/*
- * Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route
- * external abort and SError interrupts to EL3
+ * Enable HVCs, route FIQs to EL3 and set the next EL to be AArch64
*/
- tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_EA_BIT |
- SCR_FIQ_BIT;
+ tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_FIQ_BIT;
write_scr(tmp_reg);
/*
diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c
index ad73de022..eb9986c32 100644
--- a/bl31/aarch64/bl31_arch_setup.c
+++ b/bl31/aarch64/bl31_arch_setup.c
@@ -51,11 +51,9 @@ void bl31_arch_setup(void)
write_sctlr_el3(tmp_reg);
/*
- * Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route
- * external abort and SError interrupts to EL3
+ * Enable HVCs, route FIQs to EL3 and set the next EL to be AArch64
*/
- tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_EA_BIT |
- SCR_FIQ_BIT;
+ tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_FIQ_BIT;
write_scr(tmp_reg);
/*
diff --git a/docs/firmware-design.md b/docs/firmware-design.md
index b20f06b35..1700007a5 100644
--- a/docs/firmware-design.md
+++ b/docs/firmware-design.md
@@ -152,9 +152,7 @@ BL1 performs minimal architectural initialization as follows.
- `SCR`. Use of the HVC instruction from EL1 is enabled by setting the
`SCR.HCE` bit. FIQ exceptions are configured to be taken in EL3 by
setting the `SCR.FIQ` bit. The register width of the next lower
- exception level is set to AArch64 by setting the `SCR.RW` bit. External
- Aborts and SError Interrupts are configured to be taken in EL3 by
- setting the `SCR.EA` bit.
+ exception level is set to AArch64 by setting the `SCR.RW` bit.
- `CPTR_EL3`. Accesses to the `CPACR_EL1` register from EL1 or EL2, or the
`CPTR_EL2` register from EL2 are configured to not trap to EL3 by
--
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