Commit bd83b396 authored by Soby Mathew's avatar Soby Mathew
Browse files

plat/arm: Use `mov_imm` macro to load immediate values



This patch makes use of mov_imm macro where possible to load
immediate values within ARM platform layer.

Change-Id: I02bc7fbc1fa334c9fccf76fbddf515952f9a1298
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
parent 931f7c61
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
.globl plat_arm_calc_core_pos .globl plat_arm_calc_core_pos
.macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID mov_imm \x_tmp, V2M_SYSREGS_BASE + V2M_SYS_ID
ldr \w_tmp, [\x_tmp] ldr \w_tmp, [\x_tmp]
ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH
cmp \w_tmp, #BLD_GIC_VE_MMAP cmp \w_tmp, #BLD_GIC_VE_MMAP
...@@ -48,7 +48,7 @@ func plat_secondary_cold_boot_setup ...@@ -48,7 +48,7 @@ func plat_secondary_cold_boot_setup
* --------------------------------------------- * ---------------------------------------------
*/ */
mrs x0, mpidr_el1 mrs x0, mpidr_el1
ldr x1, =PWRC_BASE mov_imm x1, PWRC_BASE
str w0, [x1, #PPOFFR_OFF] str w0, [x1, #PPOFFR_OFF]
/* --------------------------------------------- /* ---------------------------------------------
...@@ -72,8 +72,8 @@ func plat_secondary_cold_boot_setup ...@@ -72,8 +72,8 @@ func plat_secondary_cold_boot_setup
b secondary_cold_boot_wait b secondary_cold_boot_wait
gicv2_bypass_disable: gicv2_bypass_disable:
ldr x0, =VE_GICC_BASE mov_imm x0, VE_GICC_BASE
ldr x1, =BASE_GICC_BASE mov_imm x1, BASE_GICC_BASE
fvp_choose_gicmmap x0, x1, x2, w2, x1 fvp_choose_gicmmap x0, x1, x2, w2, x1
mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
...@@ -128,7 +128,7 @@ func plat_get_my_entrypoint ...@@ -128,7 +128,7 @@ func plat_get_my_entrypoint
* --------------------------------------------------------------------- * ---------------------------------------------------------------------
*/ */
mrs x2, mpidr_el1 mrs x2, mpidr_el1
ldr x1, =PWRC_BASE mov_imm x1, PWRC_BASE
str w2, [x1, #PSYSR_OFF] str w2, [x1, #PSYSR_OFF]
ldr w2, [x1, #PSYSR_OFF] ldr w2, [x1, #PSYSR_OFF]
ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
...@@ -171,7 +171,7 @@ endfunc plat_get_my_entrypoint ...@@ -171,7 +171,7 @@ endfunc plat_get_my_entrypoint
*/ */
func plat_is_my_cpu_primary func plat_is_my_cpu_primary
mrs x0, mpidr_el1 mrs x0, mpidr_el1
ldr x1, =MPIDR_AFFINITY_MASK mov_imm x1, MPIDR_AFFINITY_MASK
and x0, x0, x1 and x0, x0, x1
cmp x0, #FVP_PRIMARY_CPU cmp x0, #FVP_PRIMARY_CPU
cset w0, eq cset w0, eq
......
...@@ -108,7 +108,7 @@ endfunc plat_is_my_cpu_primary ...@@ -108,7 +108,7 @@ endfunc plat_is_my_cpu_primary
func plat_is_my_cpu_primary func plat_is_my_cpu_primary
mov x9, x30 mov x9, x30
bl plat_my_core_pos bl plat_my_core_pos
ldr x1, =SCP_BOOT_CFG_ADDR mov_imm x1, SCP_BOOT_CFG_ADDR
ldr x1, [x1] ldr x1, [x1]
ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \ ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
#PLAT_CSS_PRIMARY_CPU_BIT_WIDTH #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment