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Commit c5e0b3b0 authored by Konstantin Porotchkin's avatar Konstantin Porotchkin
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docs: marvell: Update build manual 



Update build manual
- remove irrelevant platforms and environemnt variables
- add links to BLE and mv_ddr Github repositories

Change-Id: Ie389c61f014751cdc0459b3f78c70ede694d27b8
Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
parent 0682291a
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docs/marvell/build.txt
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......@@ -22,14 +22,14 @@ Build Instructions
u-boot.bin should be used and not u-boot-spl.bin
Set MSS/SCP image path (mandatory only for Armada80x0 and Aramada8xxy)::
Set MSS/SCP image path (mandatory only for Armada80x0)::
> export SCP_BL2=path/to/mrvl_scp_bl2*.img
(3) Armada-37x0 build requires WTP tools installation.
See below in the section "Tools Installation for Armada37x0 Builds".
Install ARM 32-bit cross compiler, which is required by building WTMI image for CM3::
See below in the section "Tools and external components installation".
Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3::
> sudo apt-get install gcc-arm-linux-gnueabi
......@@ -42,6 +42,8 @@ Build Instructions
There are several build options:
- DEBUG: default is without debug information (=0). in order to enable it use DEBUG=1
Must be disabled when building UART recovery images due to current console driver
implementation that is not compatible with Xmodem protocol used for boot image download.
- LOG_LEVEL: defines the level of logging which will be purged to the default output port.
......@@ -55,13 +57,14 @@ Build Instructions
- USE_COHERENT_MEM: This flag determines whether to include the coherent memory region in the
BL memory map or not.
-LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1).
- LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1).
- MARVELL_SECURE_BOOT: build trusted(=1)/non trusted(=0) image, default is non trusted.
- BLE_PATH:
Points to BLE (Binary ROM extension) sources folder. Only required for A8K and A8K+ builds.
Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds.
The parameter is optional, its default value is "ble".
For the BLE source location, check the section "Tools and external components installation"
- MV_DDR_PATH:
For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0,
......@@ -70,6 +73,7 @@ Build Instructions
The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr
sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter
is necessary for A37x0.
For the mv_ddr source location, check the section "Tools and external components installation"
- DDR_TOPOLOGY: For Armada37x0 only, the DDR topology map index/name, default is 0.
Supported Options:
......@@ -106,45 +110,35 @@ Build Instructions
nothing, an image which supports EFUSE or a customized CM3 firmware binary. The default image
is wtmi.bin that built from sources in WTP folder, which is the next option. If the default
image is OK, then this option should be skipped.
- WTP: For Armada37x0 only, use this parameter to point to wtptools source code directory, which
can be found as a3700_utils.zip in the release.
Usage example: WTP=/path/to/a3700_utils
- CP_NUM: Total amount of CPs (South Bridge) chips wired to the interconnected APs.
When the parameter is omitted, the build is uses the default number of CPs equal to 2.
The parameter is valid for Armada 8K-plus SoC family (PLAT=a8xxy) and results in a build of images
suitable for a8xxY SoC, where "Y" is a number of connected CPs and "xx" is a number of CPU cores.
Valid values with CP_NUM is in a range of 0 to 8.
The CPs defined by this parameter are evenly distributed across interconnected APs that in turn
are dynamically detected. For instance, if the CP_NUM=6 and the TF-A detects 2 interconnected
APs, each AP assumed to have 3 attached CPs. With the same amount of APs and CP_NUM=3, the AP0
will have 2 CPs connected and AP1 - a just single CP.
For example, in order to build the image in debug mode with log level up to 'notice' level run::
> make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> all fip
And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level,
the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR3 2CS,
the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command
line is as following::
> make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 SECURE=0 CLOCKSPRESET=CPU_1000_DDR_800 \
DDR_TOPOLOGY=2 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip
DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip
Supported MARVELL_PLATFORM are:
- a3700
- a3700 (for both A3720 DB and EspressoBin)
- a70x0
- a70x0_amc (for AMC board)
- a70x0_cust (for customers)
- a80x0
- a80x0_mcbin (for MacciatoBin)
Special Build Flags
--------------------
- PLAT_RECOVERY_IMAGE_ENABLE: When set this option to enable secondary recovery function when build
atf. In order to build uart recovery image this operation should be disabled for a70x0 and a80x0
because of hardware limitation(boot from secondary image can interrupt uart recovery process).
atf. In order to build UART recovery image this operation should be disabled for a70x0 and a80x0
because of hardware limitation (boot from secondary image can interrupt UART recovery process).
This MACRO definition is set in plat/marvell/a8k/common/include/platform_def.h file
(for more information about build options, please refer to section 'Summary of build options' in TF-A user-guide:
......@@ -160,22 +154,44 @@ Marvell's TF-A compilation generates 7 files:
- bl31.bin - BL31 image
- fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images)
- boot-image.bin - TF-A image (contains BL1 and FIP images)
- flash-image.bin - Image which contains boot-image.bin and SPL image; should be placed on the boot flash/device.
- flash-image.bin - Image which contains boot-image.bin and SPL image;
should be placed on the boot flash/device.
Tools and external components installation
==========================================
Tools Installation for Armada37x0 Builds
-----------------------------------------
Install a cross GNU ARM tool chain for building the WTMI binary.
Any cross GNU ARM tool chain that is able to build ARM Cortex M3 binaries
is suitable.
Armada37x0 Builds require installation of 3 components
-------------------------------------------------------
On Debian/Uboot hosts the default GNU ARM tool chain can be installed
using the following command::
(1) ARM cross compiler capable of building images for the service CPU (CM3).
This component is usually included in the Linux host packages.
On Debian/Uboot hosts the default GNU ARM tool chain can be installed
using the following command::
> sudo apt-get install gcc-arm-linux-gnueabi
If required, the default tool chain prefix "arm-linux-gnueabi-" can be
overwritten using the environment variable CROSS_CM3.
Example for BASH shell::
Only if required, the default tool chain prefix "arm-linux-gnueabi-" can be
overwritten using the environment variable CROSS_CM3.
Example for BASH shell::
> export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi
(2) DDR initialization library sources (mv_ddr) available at the following repository
(use the "mv_ddr-armada-atf-mainline" branch)::
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
(3) Armada3700 tools available at the following repository (use the latest release branch)::
https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
Armada70x0 and Armada80x0 Builds require installation of 2 components
---------------------------------------------------------------------
(1) DDR initialization library sources (mv_ddr) available at the following repository
(use the "mv_ddr-armada-atf-mainline" branch)::
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
(2) BLE sources available at the following repository (use the "atf-mainline" branch)::
https://github.com/MarvellEmbeddedProcessors/ble-marvell.git
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