fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs

This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I056d3114210db71c2840a24562b51caf2546e195

include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h → include/lib/cpus/aarch64/cortex_a510.h

@@ -4,20 +4,20 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef CORTEX_MATTERHORN_ELP_ARM_H
-#define CORTEX_MATTERHORN_ELP_ARM_H
+#ifndef CORTEX_A510_H
+#define CORTEX_A510_H
 
-#define CORTEX_MATTERHORN_ELP_ARM_MIDR					U(0x410FD480)
+#define CORTEX_A510_MIDR					U(0x410FD460)
 
 /*******************************************************************************
  * CPU Extended Control register specific definitions
  ******************************************************************************/
-#define CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1				S3_0_C15_C1_4
+#define CORTEX_A510_CPUECTLR_EL1				S3_0_C15_C1_4
 
 /*******************************************************************************
  * CPU Power Control register specific definitions
  ******************************************************************************/
-#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1			S3_0_C15_C2_7
-#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
+#define CORTEX_A510_CPUPWRCTLR_EL1				S3_0_C15_C2_7
+#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
 
-#endif /* CORTEX_MATTERHORN_ELP_ARM_H */
+#endif /* CORTEX_A510_H */

include/lib/cpus/aarch64/cortex_klein.h → include/lib/cpus/aarch64/cortex_a710.h

 /*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef CORTEX_KLEIN_H
-#define CORTEX_KLEIN_H
+#ifndef CORTEX_A710_H
+#define CORTEX_A710_H
 
-#define CORTEX_KLEIN_MIDR					U(0x410FD460)
+#define CORTEX_A710_MIDR					U(0x410FD470)
 
 /*******************************************************************************
  * CPU Extended Control register specific definitions
  ******************************************************************************/
-#define CORTEX_KLEIN_CPUECTLR_EL1				S3_0_C15_C1_4
+#define CORTEX_A710_CPUECTLR_EL1				S3_0_C15_C1_4
 
 /*******************************************************************************
  * CPU Power Control register specific definitions
  ******************************************************************************/
-#define CORTEX_KLEIN_CPUPWRCTLR_EL1				S3_0_C15_C2_7
-#define CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
+#define CORTEX_A710_CPUPWRCTLR_EL1				S3_0_C15_C2_7
+#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
 
-#endif /* CORTEX_KLEIN_H */
+#endif /* CORTEX_A710_H */

include/lib/cpus/aarch64/cortex_matterhorn.h → include/lib/cpus/aarch64/cortex_x2.h

 /*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef CORTEX_MATTERHORN_H
-#define CORTEX_MATTERHORN_H
+#ifndef CORTEX_X2_H
+#define CORTEX_X2_H
 
-#define CORTEX_MATTERHORN_MIDR					U(0x410FD470)
+#define CORTEX_X2_MIDR						U(0x410FD480)
 
 /*******************************************************************************
  * CPU Extended Control register specific definitions
  ******************************************************************************/
-#define CORTEX_MATTERHORN_CPUECTLR_EL1				S3_0_C15_C1_4
+#define CORTEX_X2_CPUECTLR_EL1					S3_0_C15_C1_4
 
 /*******************************************************************************
  * CPU Power Control register specific definitions
  ******************************************************************************/
-#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1			S3_0_C15_C2_7
-#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
+#define CORTEX_X2_CPUPWRCTLR_EL1				S3_0_C15_C2_7
+#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT			U(1)
 
-#endif /* CORTEX_MATTERHORN_H */
+#endif /* CORTEX_X2_H */

lib/cpus/aarch64/cortex_klein.S → lib/cpus/aarch64/cortex_a510.S

 /*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,54 +7,54 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <common/bl_common.h>
-#include <cortex_klein.h>
+#include <cortex_a510.h>
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
 /* Hardware handled coherency */
 #if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Klein must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "Cortex A510 must be compiled with HW_ASSISTED_COHERENCY enabled"
 #endif
 
 /* 64-bit only core */
 #if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Klein supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#error "Cortex A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
 #endif
 
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
 	 */
-func cortex_klein_core_pwr_dwn
+func cortex_a510_core_pwr_dwn
 	/* ---------------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * ---------------------------------------------------
 	 */
-	mrs	x0, CORTEX_KLEIN_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	CORTEX_KLEIN_CPUPWRCTLR_EL1, x0
+	mrs	x0, CORTEX_A510_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_A510_CPUPWRCTLR_EL1, x0
 	isb
 	ret
-endfunc cortex_klein_core_pwr_dwn
+endfunc cortex_a510_core_pwr_dwn
 
 	/*
-	 * Errata printing function for Cortex Klein. Must follow AAPCS.
+	 * Errata printing function for Cortex A510. Must follow AAPCS.
 	 */
 #if REPORT_ERRATA
-func cortex_klein_errata_report
+func cortex_a510_errata_report
 	ret
-endfunc cortex_klein_errata_report
+endfunc cortex_a510_errata_report
 #endif
 
-func cortex_klein_reset_func
+func cortex_a510_reset_func
 	/* Disable speculative loads */
 	msr	SSBS, xzr
 	isb
 	ret
-endfunc cortex_klein_reset_func
+endfunc cortex_a510_reset_func
 
 	/* ---------------------------------------------
-	 * This function provides Cortex-Klein specific
+	 * This function provides Cortex-A510 specific
 	 * register information for crash reporting.
 	 * It needs to return with x6 pointing to
 	 * a list of register names in ascii and
@@ -62,16 +62,16 @@ endfunc cortex_klein_reset_func
 	 * reported.
 	 * ---------------------------------------------
 	 */
-.section .rodata.cortex_klein_regs, "aS"
-cortex_klein_regs:  /* The ascii list of register names to be reported */
+.section .rodata.cortex_a510_regs, "aS"
+cortex_a510_regs:  /* The ascii list of register names to be reported */
 	.asciz	"cpuectlr_el1", ""
 
-func cortex_klein_cpu_reg_dump
-	adr	x6, cortex_klein_regs
-	mrs	x8, CORTEX_KLEIN_CPUECTLR_EL1
+func cortex_a510_cpu_reg_dump
+	adr	x6, cortex_a510_regs
+	mrs	x8, CORTEX_A510_CPUECTLR_EL1
 	ret
-endfunc cortex_klein_cpu_reg_dump
+endfunc cortex_a510_cpu_reg_dump
 
-declare_cpu_ops cortex_klein, CORTEX_KLEIN_MIDR, \
-	cortex_klein_reset_func, \
-	cortex_klein_core_pwr_dwn
+declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \
+	cortex_a510_reset_func, \
+	cortex_a510_core_pwr_dwn

lib/cpus/aarch64/cortex_matterhorn.S → lib/cpus/aarch64/cortex_a710.S

 /*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,54 +7,54 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <common/bl_common.h>
-#include <cortex_matterhorn.h>
+#include <cortex_a710.h>
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
 /* Hardware handled coherency */
 #if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Matterhorn must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled"
 #endif
 
 /* 64-bit only core */
 #if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Matterhorn supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
 #endif
 
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
 	 */
-func cortex_matterhorn_core_pwr_dwn
+func cortex_a710_core_pwr_dwn
 	/* ---------------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * ---------------------------------------------------
 	 */
-	mrs	x0, CORTEX_MATTERHORN_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	CORTEX_MATTERHORN_CPUPWRCTLR_EL1, x0
+	mrs	x0, CORTEX_A710_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_A710_CPUPWRCTLR_EL1, x0
 	isb
 	ret
-endfunc cortex_matterhorn_core_pwr_dwn
+endfunc cortex_a710_core_pwr_dwn
 
 	/*
-	 * Errata printing function for Cortex Matterhorn. Must follow AAPCS.
+	 * Errata printing function for Cortex A710. Must follow AAPCS.
 	 */
 #if REPORT_ERRATA
-func cortex_matterhorn_errata_report
+func cortex_a710_errata_report
 	ret
-endfunc cortex_matterhorn_errata_report
+endfunc cortex_a710_errata_report
 #endif
 
-func cortex_matterhorn_reset_func
+func cortex_a710_reset_func
 	/* Disable speculative loads */
 	msr	SSBS, xzr
 	isb
 	ret
-endfunc cortex_matterhorn_reset_func
+endfunc cortex_a710_reset_func
 
 	/* ---------------------------------------------
-	 * This function provides Cortex-Matterhorn specific
+	 * This function provides Cortex-A710 specific
 	 * register information for crash reporting.
 	 * It needs to return with x6 pointing to
 	 * a list of register names in ascii and
@@ -62,16 +62,16 @@ endfunc cortex_matterhorn_reset_func
 	 * reported.
 	 * ---------------------------------------------
 	 */
-.section .rodata.cortex_matterhorn_regs, "aS"
-cortex_matterhorn_regs:  /* The ascii list of register names to be reported */
+.section .rodata.cortex_a710_regs, "aS"
+cortex_a710_regs:  /* The ascii list of register names to be reported */
 	.asciz	"cpuectlr_el1", ""
 
-func cortex_matterhorn_cpu_reg_dump
-	adr	x6, cortex_matterhorn_regs
-	mrs	x8, CORTEX_MATTERHORN_CPUECTLR_EL1
+func cortex_a710_cpu_reg_dump
+	adr	x6, cortex_a710_regs
+	mrs	x8, CORTEX_A710_CPUECTLR_EL1
 	ret
-endfunc cortex_matterhorn_cpu_reg_dump
+endfunc cortex_a710_cpu_reg_dump
 
-declare_cpu_ops cortex_matterhorn, CORTEX_MATTERHORN_MIDR, \
-	cortex_matterhorn_reset_func, \
-	cortex_matterhorn_core_pwr_dwn
+declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \
+	cortex_a710_reset_func, \
+	cortex_a710_core_pwr_dwn

lib/cpus/aarch64/cortex_matterhorn_elp_arm.S → lib/cpus/aarch64/cortex_x2.S

 /*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,54 +7,54 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <common/bl_common.h>
-#include <cortex_matterhorn_elp_arm.h>
+#include <cortex_x2.h>
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
 /* Hardware handled coherency */
 #if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Matterhorn ELP ARM must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled"
 #endif
 
 /* 64-bit only core */
 #if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Matterhorn ELP ARM supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
 #endif
 
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
 	 */
-func cortex_matterhorn_elp_arm_core_pwr_dwn
+func cortex_x2_core_pwr_dwn
 	/* ---------------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * ---------------------------------------------------
 	 */
-	mrs	x0, CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1, x0
+	mrs	x0, CORTEX_X2_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_X2_CPUPWRCTLR_EL1, x0
 	isb
 	ret
-endfunc cortex_matterhorn_elp_arm_core_pwr_dwn
+endfunc cortex_x2_core_pwr_dwn
 
 	/*
-	 * Errata printing function for Cortex Matterhorn_elp_arm. Must follow AAPCS.
+	 * Errata printing function for Cortex X2. Must follow AAPCS.
 	 */
 #if REPORT_ERRATA
-func cortex_matterhorn_elp_arm_errata_report
+func cortex_x2_errata_report
 	ret
-endfunc cortex_matterhorn_elp_arm_errata_report
+endfunc cortex_x2_errata_report
 #endif
 
-func cortex_matterhorn_elp_arm_reset_func
+func cortex_x2_reset_func
 	/* Disable speculative loads */
 	msr	SSBS, xzr
 	isb
 	ret
-endfunc cortex_matterhorn_elp_arm_reset_func
+endfunc cortex_x2_reset_func
 
 	/* ---------------------------------------------
-	 * This function provides Cortex-Matterhorn_elp_arm specific
+	 * This function provides Cortex X2 specific
 	 * register information for crash reporting.
 	 * It needs to return with x6 pointing to
 	 * a list of register names in ascii and
@@ -62,16 +62,16 @@ endfunc cortex_matterhorn_elp_arm_reset_func
 	 * reported.
 	 * ---------------------------------------------
 	 */
-.section .rodata.cortex_matterhorn_elp_arm_regs, "aS"
-cortex_matterhorn_elp_arm_regs:  /* The ascii list of register names to be reported */
+.section .rodata.cortex_x2_regs, "aS"
+cortex_x2_regs:  /* The ascii list of register names to be reported */
 	.asciz	"cpuectlr_el1", ""
 
-func cortex_matterhorn_elp_arm_cpu_reg_dump
-	adr	x6, cortex_matterhorn_elp_arm_regs
-	mrs	x8, CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1
+func cortex_x2_cpu_reg_dump
+	adr	x6, cortex_x2_regs
+	mrs	x8, CORTEX_X2_CPUECTLR_EL1
 	ret
-endfunc cortex_matterhorn_elp_arm_cpu_reg_dump
+endfunc cortex_x2_cpu_reg_dump
 
-declare_cpu_ops cortex_matterhorn_elp_arm, CORTEX_MATTERHORN_ELP_ARM_MIDR, \
-	cortex_matterhorn_elp_arm_reset_func, \
-	cortex_matterhorn_elp_arm_core_pwr_dwn
+declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \
+	cortex_x2_reset_func, \
+	cortex_x2_core_pwr_dwn

plat/arm/board/arm_fpga/platform.mk

@@ -67,8 +67,8 @@ else
 				lib/cpus/aarch64/cortex_a78_ae.S	\
 				lib/cpus/aarch64/cortex_a65.S		\
 				lib/cpus/aarch64/cortex_a65ae.S		\
-				lib/cpus/aarch64/cortex_klein.S		\
-				lib/cpus/aarch64/cortex_matterhorn.S	\
+				lib/cpus/aarch64/cortex_a510.S		\
+				lib/cpus/aarch64/cortex_a710.S	\
 				lib/cpus/aarch64/cortex_makalu.S	\
 				lib/cpus/aarch64/cortex_makalu_elp_arm.S \
 				lib/cpus/aarch64/cortex_a78c.S

plat/arm/board/fvp/platform.mk

@@ -131,8 +131,8 @@ else
 					lib/cpus/aarch64/neoverse_e1.S		\
 					lib/cpus/aarch64/neoverse_v1.S		\
 					lib/cpus/aarch64/cortex_a78_ae.S	\
-					lib/cpus/aarch64/cortex_klein.S		\
-					lib/cpus/aarch64/cortex_matterhorn.S	\
+					lib/cpus/aarch64/cortex_a510.S		\
+					lib/cpus/aarch64/cortex_a710.S	\
 					lib/cpus/aarch64/cortex_makalu.S	\
 					lib/cpus/aarch64/cortex_makalu_elp_arm.S \
 					lib/cpus/aarch64/cortex_a65.S		\

plat/arm/board/tc0/platform.mk

@@ -43,9 +43,9 @@ TC0_BASE	=	plat/arm/board/tc0
 
 PLAT_INCLUDES		+=	-I${TC0_BASE}/include/
 
-TC0_CPU_SOURCES	:=	lib/cpus/aarch64/cortex_klein.S         \
-			lib/cpus/aarch64/cortex_matterhorn.S \
-			lib/cpus/aarch64/cortex_matterhorn_elp_arm.S
+TC0_CPU_SOURCES	:=	lib/cpus/aarch64/cortex_a510.S         \
+			lib/cpus/aarch64/cortex_a710.S \
+			lib/cpus/aarch64/cortex_x2.S
 
 INTERCONNECT_SOURCES	:=	${TC0_BASE}/tc0_interconnect.c