From c6e0a64d83bed2bb7b9a2adefabc54402b460aa8 Mon Sep 17 00:00:00 2001 From: James Liao Date: Thu, 31 Oct 2019 14:19:44 +0800 Subject: [PATCH] mediatek: mt8183: Fix AARCH64 init fail on CPU0 CPU0 is default on, so it doesn't need to run pwr_domain_on() at boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may encounter race condition with other CPUs. Now AARCH64 will be set with cluster on in pwr_domain_on(), and all CPUs on this cluster will be set together. It doesn't need to set AARCH64 again in pwr_domain_suspend(), so the race condition can be avoided. Change-Id: I5693ad56e4901f82badb0fc0d8d13e4c9acfe648 Signed-off-by: James Liao --- plat/mediatek/mt8183/plat_pm.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c index efa30f611..2358ec6c4 100644 --- a/plat/mediatek/mt8183/plat_pm.c +++ b/plat/mediatek/mt8183/plat_pm.c @@ -304,13 +304,19 @@ static int plat_mtk_power_domain_on(unsigned long mpidr) { int cpu = MPIDR_AFFLVL0_VAL(mpidr); int cluster = MPIDR_AFFLVL1_VAL(mpidr); + int clst_pwr = spm_get_cluster_powerstate(cluster); + unsigned int i; mcdi_ctrl_before_hotplug_on(cluster, cpu); hotplug_ctrl_cluster_on(cluster, cpu); - /* init cpu reset arch as AARCH64 */ - mcucfg_init_archstate(cluster, cpu, 1); - mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); + if (clst_pwr == 0) { + /* init cpu reset arch as AARCH64 of cluster */ + for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) { + mcucfg_init_archstate(cluster, i, 1); + mcucfg_set_bootaddr(cluster, i, secure_entrypoint); + } + } hotplug_ctrl_cpu_on(cluster, cpu); @@ -362,10 +368,6 @@ static void plat_mtk_power_domain_suspend(const psci_power_state_t *state) bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF); bool cluster_off = MCDI_C2 && afflvl1 && clst_single_pwr(cluster, cpu); - /* init cpu reset arch as AARCH64 */ - mcucfg_init_archstate(cluster, cpu, 1); - mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); - plat_cpu_pwrdwn_common(); plat_dcm_mcsi_a_backup(); @@ -561,15 +563,23 @@ static const plat_psci_ops_t plat_plat_pm_ops = { .system_off = plat_mtk_system_off, .system_reset = plat_mtk_system_reset, .validate_power_state = plat_mtk_validate_power_state, - .get_sys_suspend_power_state = plat_mtk_get_sys_suspend_power_state, + .get_sys_suspend_power_state = plat_mtk_get_sys_suspend_power_state }; int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { + unsigned int i; + *psci_ops = &plat_plat_pm_ops; secure_entrypoint = sec_entrypoint; + /* Init cpu reset arch as AARCH64 of cluster 0 */ + for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) { + mcucfg_init_archstate(0, i, 1); + mcucfg_set_bootaddr(0, i, secure_entrypoint); + } + if (!check_mcdi_ctl_stat()) { HP_SSPM_CTRL = false; MCDI_SSPM = false; -- GitLab