stm32mp1: split code between common and private parts

Some parts of code could be shared with platform derivatives,
or new platforms.
A new folder plat/st/common is created to put common parts.

stm32mp_common.h is a common API aggregate.

Remove some casts where applicable.
Fix some types where applicable.
Remove also some platform includes that are already in stm32mp1_def.h.

Change-Id: I46d763c8d9e15732d1ee7383207fd58206d7f583
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers/st/gpio/stm32_gpio.c

@@ -254,17 +254,17 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
 	VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
 		mmio_read_32(base + GPIO_AFRH_OFFSET));
 
-	stm32mp1_clk_disable((unsigned long)clock);
+	stm32mp1_clk_disable(clock);
 }
 
 void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
 {
 	uintptr_t base = stm32_get_gpio_bank_base(bank);
-	int clock = stm32_get_gpio_bank_clock(bank);
+	unsigned long clock = stm32_get_gpio_bank_clock(bank);
 
 	assert(pin <= GPIO_PIN_MAX);
 
-	stm32mp1_clk_enable((unsigned long)clock);
+	stm32mp1_clk_enable(clock);
 
 	if (secure) {
 		mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
@@ -272,5 +272,5 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
 		mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
 	}
 
-	stm32mp1_clk_disable((unsigned long)clock);
+	stm32mp1_clk_disable(clock);
 }

plat/st/stm32mp1/bl2_io_storage.c → plat/st/common/bl2_io_storage.c

@@ -25,9 +25,6 @@
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 
-#include <boot_api.h>
-#include <stm32mp1_private.h>
-
 /* IO devices */
 static const io_dev_connector_t *dummy_dev_con;
 static uintptr_t dummy_dev_handle;

plat/st/common/include/stm32mp_common.h

+/*
+ * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_COMMON_H
+#define STM32MP_COMMON_H
+
+/* Functions to save and get boot context address given by ROM code */
+void stm32mp1_save_boot_ctx_address(uintptr_t address);
+uintptr_t stm32mp1_get_boot_ctx_address(void);
+
+/*
+ * Platform util functions for the GPIO driver
+ * @bank: Target GPIO bank ID as per DT bindings
+ *
+ * Platform shall implement these functions to provide to stm32_gpio
+ * driver the resource reference for a target GPIO bank. That are
+ * memory mapped interface base address, interface offset (see below)
+ * and clock identifier.
+ *
+ * stm32_get_gpio_bank_offset() returns a bank offset that is used to
+ * check DT configuration matches platform implementation of the banks
+ * description.
+ */
+uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
+unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
+uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
+
+/* Initialise the IO layer and register platform IO devices */
+void stm32mp1_io_setup(void);
+
+#endif /* STM32MP_COMMON_H */

plat/st/stm32mp1/include/stm32mp1_dt.h → plat/st/common/include/stm32mp_dt.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef STM32MP1_DT_H
-#define STM32MP1_DT_H
+#ifndef STM32MP_DT_H
+#define STM32MP_DT_H
 
 #include <stdbool.h>
 
@@ -27,7 +27,7 @@ struct dt_node_info {
 int dt_open_and_check(void);
 int fdt_get_address(void **fdt_addr);
 bool fdt_check_node(int node);
-uint32_t fdt_get_status(int node);
+uint8_t fdt_get_status(int node);
 uint32_t fdt_read_uint32_default(int node, const char *prop_name,
 				 uint32_t dflt_value);
 int fdt_read_uint32_array(int node, const char *prop_name,
@@ -40,4 +40,4 @@ int dt_get_stdout_node_offset(void);
 uint32_t dt_get_ddr_size(void);
 const char *dt_get_board_model(void);
 
-#endif /* STM32MP1_DT_H */
+#endif /* STM32MP_DT_H */

plat/st/common/stm32mp_common.c

+/*
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <plat/common/platform.h>
+
+uintptr_t plat_get_ns_image_entrypoint(void)
+{
+	return BL33_BASE;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	return read_cntfrq_el0();
+}
+
+static uintptr_t boot_ctx_address;
+
+void stm32mp1_save_boot_ctx_address(uintptr_t address)
+{
+	boot_ctx_address = address;
+}
+
+uintptr_t stm32mp1_get_boot_ctx_address(void)
+{
+	return boot_ctx_address;
+}
+
+uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
+{
+	if (bank == GPIO_BANK_Z) {
+		return GPIOZ_BASE;
+	}
+
+	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+
+	return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
+}
+
+unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
+{
+	if (bank == GPIO_BANK_Z) {
+		return GPIOZ;
+	}
+
+	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+
+	return GPIOA + (bank - GPIO_BANK_A);
+}
+
+uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
+{
+	if (bank == GPIO_BANK_Z) {
+		return 0;
+	}
+
+	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+
+	return bank * GPIO_BANK_OFFSET;
+}

plat/st/stm32mp1/stm32mp1_dt.c → plat/st/common/stm32mp_dt.c

@@ -14,10 +14,11 @@
 #include <common/debug.h>
 #include <drivers/st/stm32_gpio.h>
 #include <drivers/st/stm32mp1_clk.h>
-#include <drivers/st/stm32mp1_clkfunc.h>
 #include <drivers/st/stm32mp1_ddr.h>
 #include <drivers/st/stm32mp1_ram.h>
 
+#include <stm32mp_dt.h>
+
 static int fdt_checked;
 
 static void *fdt = (void *)(uintptr_t)STM32MP1_DTB_BASE;
@@ -68,9 +69,9 @@ bool fdt_check_node(int node)
 /*******************************************************************************
  * This function return global node status (generic use of fdt library).
  ******************************************************************************/
-uint32_t fdt_get_status(int node)
+uint8_t fdt_get_status(int node)
 {
-	uint32_t status = DT_DISABLED;
+	uint8_t status = DT_DISABLED;
 	int len;
 	const char *cchar;
 

plat/st/stm32mp1/bl2_plat_setup.c

@@ -26,10 +26,7 @@
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
 
-#include <boot_api.h>
 #include <stm32mp1_context.h>
-#include <stm32mp1_dt.h>
-#include <stm32mp1_private.h>
 
 static struct console_stm32 console;
 

plat/st/stm32mp1/include/stm32mp1_private.h

@@ -9,20 +9,12 @@
 
 #include <stdint.h>
 
-void stm32mp1_io_setup(void);
 void configure_mmu(void);
 
 void stm32mp1_arch_security_setup(void);
 void stm32mp1_security_setup(void);
 
-void stm32mp1_save_boot_ctx_address(uintptr_t address);
-uintptr_t stm32mp1_get_boot_ctx_address(void);
-
 void stm32mp1_gic_pcpu_init(void);
 void stm32mp1_gic_init(void);
 
-uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
-unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
-uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
-
 #endif /* STM32MP1_PRIVATE_H */

plat/st/stm32mp1/platform.mk

@@ -21,7 +21,8 @@ $(eval $(call add_define,STM32_TF_A_COPIES))
 PLAT_PARTITION_MAX_ENTRIES	:=	$(shell echo $$(($(STM32_TF_A_COPIES) + 1)))
 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
 
-PLAT_INCLUDES		:=	-Iplat/st/stm32mp1/include/
+PLAT_INCLUDES		:=	-Iplat/st/common/include/
+PLAT_INCLUDES		+=	-Iplat/st/stm32mp1/include/
 
 # Device tree
 DTB_FILE_NAME		?=	stm32mp157c-ev1.dtb
@@ -30,7 +31,8 @@ DTC_FLAGS		+=	-Wno-unit_address_vs_reg
 
 include lib/libfdt/libfdt.mk
 
-PLAT_BL_COMMON_SOURCES	:=	plat/st/stm32mp1/stm32mp1_common.c
+PLAT_BL_COMMON_SOURCES	:=	plat/st/common/stm32mp_common.c				\
+				plat/st/stm32mp1/stm32mp1_private.c
 
 PLAT_BL_COMMON_SOURCES	+=	drivers/st/uart/aarch32/stm32_console.S
 
@@ -56,8 +58,8 @@ PLAT_BL_COMMON_SOURCES	+=	${LIBFDT_SRCS}						\
 				drivers/st/pmic/stm32mp_pmic.c				\
 				drivers/st/pmic/stpmic1.c				\
 				drivers/st/reset/stm32mp1_reset.c			\
+				plat/st/common/stm32mp_dt.c				\
 				plat/st/stm32mp1/stm32mp1_context.c			\
-				plat/st/stm32mp1/stm32mp1_dt.c				\
 				plat/st/stm32mp1/stm32mp1_helper.S			\
 				plat/st/stm32mp1/stm32mp1_security.c
 
@@ -65,7 +67,7 @@ BL2_SOURCES		+=	drivers/io/io_block.c					\
 				drivers/io/io_dummy.c					\
 				drivers/io/io_storage.c					\
 				drivers/st/io/io_stm32image.c				\
-				plat/st/stm32mp1/bl2_io_storage.c			\
+				plat/st/common/bl2_io_storage.c				\
 				plat/st/stm32mp1/bl2_plat_setup.c
 
 BL2_SOURCES		+=	drivers/mmc/mmc.c					\

plat/st/stm32mp1/sp_min/sp_min_setup.c

@@ -27,8 +27,6 @@
 #include <plat/common/platform.h>
 
 #include <platform_sp_min.h>
-#include <stm32mp1_dt.h>
-#include <stm32mp1_private.h>
 
 /******************************************************************************
  * Placeholder variables for copying the arguments that have been passed to

plat/st/stm32mp1/stm32mp1_def.h

@@ -13,7 +13,8 @@
 
 #ifndef __ASSEMBLY__
 #include <boot_api.h>
-#include <stm32mp1_dt.h>
+#include <stm32mp_common.h>
+#include <stm32mp_dt.h>
 #include <stm32mp1_private.h>
 #endif
 

plat/st/stm32mp1/stm32mp1_gic.c

@@ -15,9 +15,6 @@
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 
-#include <stm32mp1_dt.h>
-#include <stm32mp1_private.h>
-
 struct stm32_gic_instance {
 	uint32_t cells;
 	uint32_t phandle_node;

plat/st/stm32mp1/stm32mp1_pm.c

@@ -20,9 +20,6 @@
 #include <lib/psci/psci.h>
 #include <plat/common/platform.h>
 
-#include <boot_api.h>
-#include <stm32mp1_private.h>
-
 static uintptr_t stm32_sec_entrypoint;
 static uint32_t cntfrq_core0;
 

plat/st/stm32mp1/stm32mp1_common.c → plat/st/stm32mp1/stm32mp1_private.c

@@ -4,20 +4,9 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <assert.h>
-
 #include <platform_def.h>
 
-#include <arch_helpers.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/gicv2.h>
-#include <dt-bindings/clock/stm32mp1-clks.h>
-#include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
-#include <plat/common/platform.h>
-
-#include <stm32mp1_private.h>
 
 #define MAP_SRAM	MAP_REGION_FLAT(STM32MP1_SRAM_BASE, \
 					STM32MP1_SRAM_SIZE, \
@@ -64,60 +53,3 @@ void configure_mmu(void)
 
 	enable_mmu_svc_mon(0);
 }
-
-uintptr_t plat_get_ns_image_entrypoint(void)
-{
-	return BL33_BASE;
-}
-
-unsigned int plat_get_syscnt_freq2(void)
-{
-	return read_cntfrq_el0();
-}
-
-/* Functions to save and get boot context address given by ROM code */
-static uintptr_t boot_ctx_address;
-
-void stm32mp1_save_boot_ctx_address(uintptr_t address)
-{
-	boot_ctx_address = address;
-}
-
-uintptr_t stm32mp1_get_boot_ctx_address(void)
-{
-	return boot_ctx_address;
-}
-
-uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
-{
-	switch (bank) {
-	case GPIO_BANK_A ... GPIO_BANK_K:
-		return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
-	case GPIO_BANK_Z:
-		return GPIOZ_BASE;
-	default:
-		panic();
-	}
-}
-
-/* Return clock ID on success, negative value on error */
-unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
-{
-	switch (bank) {
-	case GPIO_BANK_A ... GPIO_BANK_K:
-		return GPIOA + (bank - GPIO_BANK_A);
-	case GPIO_BANK_Z:
-		return GPIOZ;
-	default:
-		panic();
-	}
-}
-
-uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
-{
-	if (bank == GPIO_BANK_Z) {
-		return 0;
-	} else {
-		return bank * GPIO_BANK_OFFSET;
-	}
-}

plat/st/stm32mp1/stm32mp1_security.c

@@ -15,9 +15,6 @@
 #include <dt-bindings/clock/stm32mp1-clks.h>
 #include <lib/mmio.h>
 
-#include <stm32mp1_dt.h>
-#include <stm32mp1_private.h>
-
 /*******************************************************************************
  * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
  * and allow Non-Secure masters full access.