From ca0225a5dcdd496e1ed1808ff0925dc911098654 Mon Sep 17 00:00:00 2001 From: Achin Gupta Date: Mon, 18 May 2015 10:56:47 +0100 Subject: [PATCH] Fix reporting of interrupt ID in ARM GIC driver The ARM GIC driver treats the entire contents of the GICC_HPPIR as the interrupt ID instead of just bits[9:0]. This could result in an SGI being treated as a Group 1 interrupt on a GICv2 system. This patch introduces a mask to retrieve only the ID from a read of GICC_HPPIR, GICC_IAR and similar registers. The value read from these registers is masked with this constant prior to use as an interrupt ID. Fixes ARM-software/tf-issues#306 Change-Id: Ie3885157de33b71df9781a41f6ef015a30c4608d --- drivers/arm/gic/arm_gic.c | 6 +++--- include/drivers/arm/gic_v2.h | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/arm/gic/arm_gic.c b/drivers/arm/gic/arm_gic.c index 2888e719f..52174719d 100644 --- a/drivers/arm/gic/arm_gic.c +++ b/drivers/arm/gic/arm_gic.c @@ -401,7 +401,7 @@ uint32_t arm_gic_get_pending_interrupt_type(void) uint32_t id; assert(g_gicc_base); - id = gicc_read_hppir(g_gicc_base); + id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK; /* Assume that all secure interrupts are S-EL1 interrupts */ if (id < 1022) @@ -423,7 +423,7 @@ uint32_t arm_gic_get_pending_interrupt_id(void) uint32_t id; assert(g_gicc_base); - id = gicc_read_hppir(g_gicc_base); + id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK; if (id < 1022) return id; @@ -435,7 +435,7 @@ uint32_t arm_gic_get_pending_interrupt_id(void) * Find out which non-secure interrupt it is under the assumption that * the GICC_CTLR.AckCtl bit is 0. */ - return gicc_read_ahppir(g_gicc_base); + return gicc_read_ahppir(g_gicc_base) & INT_ID_MASK; } /******************************************************************************* diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h index a2d3eeec7..54276b806 100644 --- a/include/drivers/arm/gic_v2.h +++ b/include/drivers/arm/gic_v2.h @@ -99,6 +99,9 @@ #define GICC_DIR 0x1000 #define GICC_PRIODROP GICC_EOIR +/* Common CPU Interface definitions */ +#define INT_ID_MASK 0x3ff + /* GICC_CTLR bit definitions */ #define EOI_MODE_NS (1 << 10) #define EOI_MODE_S (1 << 9) -- GitLab