Merge "lib: cpu: Add additional field definition for A72 L2 control" into integration

include/lib/cpus/aarch64/cortex_a72.h

@@ -43,7 +43,14 @@
  ******************************************************************************/
 #define CORTEX_A72_L2ACTLR_EL1					S3_1_C15_C0_0
 
+#define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE		(ULL(1) << 28)
+#define CORTEX_A72_L2ACTLR_FORCE_L2_LOGIC_CLK_ACTIVE		(ULL(1) << 27)
+#define CORTEX_A72_L2ACTLR_FORCE_L2_GIC_TIMER_RCG_CLK_ACTIVE	(ULL(1) << 26)
 #define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN			(ULL(1) << 14)
+#define CORTEX_A72_L2ACTLR_DISABLE_DSB_WITH_NO_DVM_SYNC		(ULL(1) << 11)
+#define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST		(ULL(1) << 8)
+#define CORTEX_A72_L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT		(ULL(1) << 7)
+#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI		(ULL(1) << 6)
 
 /*******************************************************************************
  * L2 Control register specific definitions.
@@ -51,8 +58,12 @@
 #define CORTEX_A72_L2CTLR_EL1				S3_1_C11_C0_2
 
 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT	U(0)
+#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT		U(5)
 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT		U(6)
+#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT		U(9)
 
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK		U(0x7)
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK		U(0x7)
 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES		U(0x2)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES		U(0x1)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES		U(0x2)