drivers: renesas: rcar: pwrc: Code cleanup

This patches fixes checkpatch warnings, replace TAB with space
after #define macros and arrange header as per TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Iba009587e0b499b3ae58876be390602ae14175b2

drivers/renesas/rcar/pwrc/pwrc.c

 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,10 +16,10 @@
 #include <plat/common/platform.h>
 
 #include "iic_dvfs.h"
-#include "rcar_def.h"
-#include "rcar_private.h"
 #include "micro_delay.h"
 #include "pwrc.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
 
 /*
  * Someday there will be a generic power controller api. At the moment each
@@ -30,13 +30,13 @@ RCAR_INSTANTIATE_LOCK
 #define WUP_IRQ_SHIFT				(0U)
 #define WUP_FIQ_SHIFT				(8U)
 #define WUP_CSD_SHIFT				(16U)
-#define	BIT_SOFTRESET				(1U<<15)
-#define	BIT_CA53_SCU				(1U<<21)
-#define	BIT_CA57_SCU				(1U<<12)
-#define	REQ_RESUME				(1U<<1)
-#define	REQ_OFF					(1U<<0)
-#define	STATUS_PWRUP				(1U<<4)
-#define	STATUS_PWRDOWN				(1U<<0)
+#define BIT_SOFTRESET				(1U << 15)
+#define BIT_CA53_SCU				(1U << 21)
+#define BIT_CA57_SCU				(1U << 12)
+#define REQ_RESUME				(1U << 1)
+#define REQ_OFF					(1U << 0)
+#define STATUS_PWRUP				(1U << 4)
+#define STATUS_PWRDOWN				(1U << 0)
 #define STATE_CA57_CPU				(27U)
 #define STATE_CA53_CPU				(22U)
 #define MODE_L2_DOWN				(0x00000002U)
@@ -140,7 +140,7 @@ RCAR_INSTANTIATE_LOCK
 #define PMIC_BKUP_MODE_CNT			(0x20U)
 #define PMIC_QLLM_CNT				(0x27U)
 #define PMIC_RETRY_MAX				(100U)
-#endif
+#endif /* PMIC_ROHM_BD9571 */
 #define SCTLR_EL3_M_BIT				((uint32_t)1U << 0)
 #define RCAR_CA53CPU_NUM_MAX			(4U)
 #define RCAR_CA57CPU_NUM_MAX			(4U)
@@ -320,11 +320,13 @@ void rcar_pwrc_clusteroff(uint64_t mpidr)
 	c = rcar_pwrc_get_mpidr_cluster(mpidr);
 	dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
 
-	if (PRR_PRODUCT_M3 == product && cut < PRR_PRODUCT_30)
+	if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
 		goto done;
+	}
 
-	if (PRR_PRODUCT_H3 == product && cut <= PRR_PRODUCT_20)
+	if (product == PRR_PRODUCT_H3 && cut <= PRR_PRODUCT_20) {
 		goto done;
+	}
 
 	/* all of the CPUs in the cluster is in the CoreStandby mode */
 	mmio_write_32(dst, MODE_L2_DOWN);
@@ -343,7 +345,7 @@ static void rcar_pwrc_save_timer_state(void)
 	rcar_pwrc_saved_cntfid =
 		mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF));
 }
-#endif
+#endif /* RCAR_SYSTEM_SUSPEND */
 
 void rcar_pwrc_restore_timer_state(void)
 {
@@ -427,11 +429,13 @@ static void __attribute__ ((section(".system_ram")))
 	product = reg & PRR_PRODUCT_MASK;
 	cut = reg & PRR_CUT_MASK;
 
-	if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
+	if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
 		goto self_refresh;
+	}
 
-	if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
+	if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) {
 		goto self_refresh;
+	}
 
 	mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
 
@@ -509,7 +513,7 @@ self_refresh:
 }
 
 static void __attribute__ ((section(".system_ram")))
-    rcar_pwrc_set_self_refresh_e3(void)
+rcar_pwrc_set_self_refresh_e3(void)
 {
 	uint32_t ddr_md;
 	uint32_t reg;
@@ -533,8 +537,10 @@ static void __attribute__ ((section(".system_ram")))
 	while (mmio_read_32(DBSC4_REG_DBWAIT))
 		;
 
-	/* Set the auto-refresh enable register */
-	/* Set the ARFEN bit to 0 in the DBRFEN */
+	/*
+	 * Set the auto-refresh enable register
+	 * Set the ARFEN bit to 0 in the DBRFEN
+	 */
 	mmio_write_32(DBSC4_REG_DBRFEN, 0);
 
 	mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
@@ -638,7 +644,7 @@ static void __attribute__ ((section(".system_ram")))
 }
 
 void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
-    rcar_pwrc_go_suspend_to_ram(void)
+rcar_pwrc_go_suspend_to_ram(void)
 {
 #if PMIC_ROHM_BD9571
 	int32_t rc = -1, qllm = -1;
@@ -713,7 +719,7 @@ void rcar_pwrc_suspend_to_ram(void)
 
 	error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
 	if (error) {
-		ERROR("Failed send KEEP10 init ret=%d \n", error);
+		ERROR("Failed send KEEP10 init ret=%d\n", error);
 		return;
 	}
 #endif
@@ -835,7 +841,6 @@ int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
 	uint64_t my_cpu;
 	int32_t rtn;
 	uint32_t my_cluster_type;
-
 	const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = {
 			RCAR_CLUSTER_CA53,
 			RCAR_CLUSTER_CA57
@@ -861,6 +866,6 @@ int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
 			}
 		}
 	}
-	return (rtn);
 
+	return rtn;
 }

drivers/renesas/rcar/pwrc/pwrc.h

 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */