Commit cb60e71e authored by Soby Mathew's avatar Soby Mathew Committed by TrustedFirmware Code Review
Browse files

Merge changes from topic "jts/ti_fix" into integration

* changes:
  ti: k3: common: Remove coherency workaround for AM65x
  ti: k3: common: Use coherent memory for shared data
parents f5b904ea 48d6b264
...@@ -279,13 +279,11 @@ endfunc cortex_a53_reset_func ...@@ -279,13 +279,11 @@ endfunc cortex_a53_reset_func
func cortex_a53_core_pwr_dwn func cortex_a53_core_pwr_dwn
mov x18, x30 mov x18, x30
#if !TI_AM65X_WORKAROUND
/* --------------------------------------------- /* ---------------------------------------------
* Turn off caches. * Turn off caches.
* --------------------------------------------- * ---------------------------------------------
*/ */
bl cortex_a53_disable_dcache bl cortex_a53_disable_dcache
#endif
/* --------------------------------------------- /* ---------------------------------------------
* Flush L1 caches. * Flush L1 caches.
...@@ -305,13 +303,11 @@ endfunc cortex_a53_core_pwr_dwn ...@@ -305,13 +303,11 @@ endfunc cortex_a53_core_pwr_dwn
func cortex_a53_cluster_pwr_dwn func cortex_a53_cluster_pwr_dwn
mov x18, x30 mov x18, x30
#if !TI_AM65X_WORKAROUND
/* --------------------------------------------- /* ---------------------------------------------
* Turn off caches. * Turn off caches.
* --------------------------------------------- * ---------------------------------------------
*/ */
bl cortex_a53_disable_dcache bl cortex_a53_disable_dcache
#endif
/* --------------------------------------------- /* ---------------------------------------------
* Flush L1 caches. * Flush L1 caches.
......
...@@ -17,11 +17,6 @@ ...@@ -17,11 +17,6 @@
#include <k3_gicv3.h> #include <k3_gicv3.h>
#include <ti_sci.h> #include <ti_sci.h>
#ifdef TI_AM65X_WORKAROUND
/* Need to flush psci internal locks before shutdown or their values are lost */
#include "../../../../lib/psci/psci_private.h"
#endif
uintptr_t k3_sec_entrypoint; uintptr_t k3_sec_entrypoint;
static void k3_cpu_standby(plat_local_state_t cpu_state) static void k3_cpu_standby(plat_local_state_t cpu_state)
...@@ -115,16 +110,6 @@ void k3_pwr_domain_on_finish(const psci_power_state_t *target_state) ...@@ -115,16 +110,6 @@ void k3_pwr_domain_on_finish(const psci_power_state_t *target_state)
k3_gic_cpuif_enable(); k3_gic_cpuif_enable();
} }
#ifdef TI_AM65X_WORKAROUND
static void __dead2 k3_pwr_domain_pwr_down_wfi(const psci_power_state_t
*target_state)
{
flush_cpu_data(psci_svc_cpu_data);
flush_dcache_range((uintptr_t) psci_locks, sizeof(psci_locks));
psci_power_down_wfi();
}
#endif
static void __dead2 k3_system_reset(void) static void __dead2 k3_system_reset(void)
{ {
/* Send the system reset request to system firmware */ /* Send the system reset request to system firmware */
...@@ -154,9 +139,6 @@ static const plat_psci_ops_t k3_plat_psci_ops = { ...@@ -154,9 +139,6 @@ static const plat_psci_ops_t k3_plat_psci_ops = {
.pwr_domain_on = k3_pwr_domain_on, .pwr_domain_on = k3_pwr_domain_on,
.pwr_domain_off = k3_pwr_domain_off, .pwr_domain_off = k3_pwr_domain_off,
.pwr_domain_on_finish = k3_pwr_domain_on_finish, .pwr_domain_on_finish = k3_pwr_domain_on_finish,
#ifdef TI_AM65X_WORKAROUND
.pwr_domain_pwr_down_wfi = k3_pwr_domain_pwr_down_wfi,
#endif
.system_reset = k3_system_reset, .system_reset = k3_system_reset,
.validate_power_state = k3_validate_power_state, .validate_power_state = k3_validate_power_state,
.validate_ns_entrypoint = k3_validate_ns_entrypoint .validate_ns_entrypoint = k3_validate_ns_entrypoint
......
...@@ -12,8 +12,8 @@ COLD_BOOT_SINGLE_CPU := 1 ...@@ -12,8 +12,8 @@ COLD_BOOT_SINGLE_CPU := 1
PROGRAMMABLE_RESET_ADDRESS:= 1 PROGRAMMABLE_RESET_ADDRESS:= 1
# System coherency is managed in hardware # System coherency is managed in hardware
HW_ASSISTED_COHERENCY := 1 WARMBOOT_ENABLE_DCACHE_EARLY := 1
USE_COHERENT_MEM := 0 USE_COHERENT_MEM := 1
# A53 erratum for SoC. (enable them all) # A53 erratum for SoC. (enable them all)
ERRATA_A53_826319 := 1 ERRATA_A53_826319 := 1
...@@ -28,10 +28,6 @@ ERRATA_A72_859971 := 1 ...@@ -28,10 +28,6 @@ ERRATA_A72_859971 := 1
# Split out RO data into a non-executable section # Split out RO data into a non-executable section
SEPARATE_CODE_AND_RODATA := 1 SEPARATE_CODE_AND_RODATA := 1
# Leave the caches enabled on core powerdown path
TI_AM65X_WORKAROUND := 1
$(eval $(call add_define,TI_AM65X_WORKAROUND))
MULTI_CONSOLE_API := 1 MULTI_CONSOLE_API := 1
TI_16550_MDR_QUIRK := 1 TI_16550_MDR_QUIRK := 1
$(eval $(call add_define,TI_16550_MDR_QUIRK)) $(eval $(call add_define,TI_16550_MDR_QUIRK))
......
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