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Commit cbaad533 authored by Carlo Caione's avatar Carlo Caione
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amlogic: Fix prefixes in the MHU code 



Make the MHU code AML specific adding a new aml_* prefix and remove the
GXBB prefix from the register names.
Signed-off-by: default avatarCarlo Caione <ccaione@baylibre.com>
Change-Id: I8f20918e29f08542bd71bd679f88e65b4efaa7d2
parent 381b901f
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plat/amlogic/common/aml_mhu.c
View file @ cbaad533
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -10,43 +10,43 @@
static DEFINE_BAKERY_LOCK(mhu_lock);
void mhu_secure_message_start(void)
void aml_mhu_secure_message_start(void)
{
bakery_lock_get(&mhu_lock);
while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
while (mmio_read_32(AML_HIU_MAILBOX_STAT_3) != 0)
;
}
void mhu_secure_message_send(uint32_t msg)
void aml_mhu_secure_message_send(uint32_t msg)
{
mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg);
mmio_write_32(AML_HIU_MAILBOX_SET_3, msg);
while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
while (mmio_read_32(AML_HIU_MAILBOX_STAT_3) != 0)
;
}
uint32_t mhu_secure_message_wait(void)
uint32_t aml_mhu_secure_message_wait(void)
{
uint32_t val;
do {
val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0);
val = mmio_read_32(AML_HIU_MAILBOX_STAT_0);
} while (val == 0);
return val;
}
void mhu_secure_message_end(void)
void aml_mhu_secure_message_end(void)
{
mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF);
mmio_write_32(AML_HIU_MAILBOX_CLR_0, 0xFFFFFFFF);
bakery_lock_release(&mhu_lock);
}
void mhu_secure_init(void)
void aml_mhu_secure_init(void)
{
bakery_lock_init(&mhu_lock);
mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF);
mmio_write_32(AML_HIU_MAILBOX_CLR_3, 0xFFFFFFFF);
}
plat/amlogic/common/aml_scpi.c
View file @ cbaad533
......@@ -37,12 +37,12 @@ static inline uint32_t scpi_cmd(uint32_t command, uint32_t size)
static void scpi_secure_message_send(uint32_t command, uint32_t size)
{
mhu_secure_message_send(scpi_cmd(command, size));
aml_mhu_secure_message_send(scpi_cmd(command, size));
}
uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out)
{
uint32_t response = mhu_secure_message_wait();
uint32_t response = aml_mhu_secure_message_wait();
size_t size = (response >> SIZE_SHIFT) & SIZE_MASK;
......@@ -52,7 +52,7 @@ uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out)
*size_out = size;
if (message_out != NULL)
*message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD;
*message_out = (void *)AML_MHU_SECURE_SCP_TO_AP_PAYLOAD;
return response;
}
......@@ -66,11 +66,11 @@ void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
(cluster_state << 12) |
(css_state << 16);
mhu_secure_message_start();
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state);
mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4));
mhu_secure_message_wait();
mhu_secure_message_end();
aml_mhu_secure_message_start();
mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, state);
aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4));
aml_mhu_secure_message_wait();
aml_mhu_secure_message_end();
}
uint32_t scpi_sys_power_state(uint64_t system_state)
......@@ -78,11 +78,11 @@ uint32_t scpi_sys_power_state(uint64_t system_state)
uint32_t *response;
size_t size;
mhu_secure_message_start();
mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state);
mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1));
aml_mhu_secure_message_start();
mmio_write_8(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state);
aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1));
scpi_secure_message_receive((void *)&response, &size);
mhu_secure_message_end();
aml_mhu_secure_message_end();
return *response;
}
......@@ -96,12 +96,12 @@ void scpi_jtag_set_state(uint32_t state, uint8_t select)
return;
}
mhu_secure_message_start();
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD,
aml_mhu_secure_message_start();
mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD,
(state << 8) | (uint32_t)select);
mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4));
mhu_secure_message_wait();
mhu_secure_message_end();
aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4));
aml_mhu_secure_message_wait();
aml_mhu_secure_message_end();
}
uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
......@@ -112,12 +112,12 @@ uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
if (size > 0x1FC)
return 0;
mhu_secure_message_start();
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base);
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size);
mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8));
aml_mhu_secure_message_start();
mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, base);
mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size);
aml_mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8));
scpi_secure_message_receive((void *)&response, &resp_size);
mhu_secure_message_end();
aml_mhu_secure_message_end();
/*
* response[0] is the size of the response message.
......@@ -132,57 +132,57 @@ uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
uint32_t arg2, uint32_t arg3)
{
mhu_secure_message_start();
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0);
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1);
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2);
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3);
mhu_secure_message_send(scpi_cmd(0xC3, 16));
mhu_secure_message_wait();
mhu_secure_message_end();
aml_mhu_secure_message_start();
mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0);
mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1);
mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2);
mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3);
aml_mhu_secure_message_send(scpi_cmd(0xC3, 16));
aml_mhu_secure_message_wait();
aml_mhu_secure_message_end();
}
static inline void scpi_copy_scp_data(uint8_t *data, size_t len)
{
void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD;
void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD;
size_t sz;
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
scpi_secure_message_send(SCPI_CMD_FW_SIZE, len);
mhu_secure_message_wait();
aml_mhu_secure_message_wait();
for (sz = 0; sz < len; sz += SIZE_FWBLK) {
memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz));
mhu_secure_message_send(SCPI_CMD_COPY_FW);
aml_mhu_secure_message_send(SCPI_CMD_COPY_FW);
}
}
static inline void scpi_set_scp_addr(uint64_t addr, size_t len)
{
volatile uint64_t *dst = (uint64_t *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD;
volatile uint64_t *dst = (uint64_t *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD;
/*
* It is ok as GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as
* It is ok as AML_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as
* non cachable
*/
*dst = addr;
scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr));
mhu_secure_message_wait();
aml_mhu_secure_message_wait();
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
scpi_secure_message_send(SCPI_CMD_FW_SIZE, len);
mhu_secure_message_wait();
aml_mhu_secure_message_wait();
}
static inline void scpi_send_fw_hash(uint8_t hash[], size_t len)
{
void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD;
void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD;
memcpy(dst, hash, len);
mhu_secure_message_send(0xd0);
mhu_secure_message_send(0xd1);
mhu_secure_message_send(0xd5);
mhu_secure_message_end();
aml_mhu_secure_message_send(0xd0);
aml_mhu_secure_message_send(0xd1);
aml_mhu_secure_message_send(0xd5);
aml_mhu_secure_message_end();
}
/**
......@@ -201,7 +201,7 @@ void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send)
asd_sha_update(&ctx, (void *)addr, size);
asd_sha_finalize(&ctx);
mhu_secure_message_start();
aml_mhu_secure_message_start();
if (send == 0)
scpi_set_scp_addr(addr, size);
else
......
plat/amlogic/common/include/aml_private.h
View file @ cbaad533
......@@ -16,11 +16,11 @@ void aml_console_init(void);
void aml_setup_page_tables(void);
/* MHU functions */
void mhu_secure_message_start(void);
void mhu_secure_message_send(uint32_t msg);
uint32_t mhu_secure_message_wait(void);
void mhu_secure_message_end(void);
void mhu_secure_init(void);
void aml_mhu_secure_message_start(void);
void aml_mhu_secure_message_send(uint32_t msg);
uint32_t aml_mhu_secure_message_wait(void);
void aml_mhu_secure_message_end(void);
void aml_mhu_secure_init(void);
/* SCPI functions */
void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
......
plat/amlogic/gxbb/gxbb_bl31_setup.c
View file @ cbaad533
......@@ -135,7 +135,7 @@ static const gicv2_driver_data_t gxbb_gic_data = {
void bl31_platform_setup(void)
{
mhu_secure_init();
aml_mhu_secure_init();
gicv2_driver_init(&gxbb_gic_data);
gicv2_distif_init();
......
plat/amlogic/gxbb/gxbb_def.h
View file @ cbaad533
......@@ -42,8 +42,8 @@
/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
/* Mailboxes */
#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00)
#define GXBB_TZROM_BASE UL(0xD9040000)
......@@ -88,12 +88,12 @@
#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C)
#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404)
#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428)
#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
#define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404)
#define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
#define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
#define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428)
#define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
#define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
/*******************************************************************************
* System Monitor Call IDs and arguments
......
plat/amlogic/gxl/gxl_bl31_setup.c
View file @ cbaad533
......@@ -149,7 +149,7 @@ static const gicv2_driver_data_t gxbb_gic_data = {
void bl31_platform_setup(void)
{
mhu_secure_init();
aml_mhu_secure_init();
gicv2_driver_init(&gxbb_gic_data);
gicv2_distif_init();
......
plat/amlogic/gxl/gxl_def.h
View file @ cbaad533
......@@ -42,8 +42,8 @@
/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
/* Mailboxes */
#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00)
// * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
......@@ -98,12 +98,12 @@
((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \
GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK)
#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404)
#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428)
#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
#define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404)
#define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
#define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
#define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428)
#define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
#define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
/*******************************************************************************
* System Monitor Call IDs and arguments
......
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