diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 777115a6598a5bfde82fb4be1d25c1e4d213f80b..1af196209d3589f6dc62a0aed24ca83415eaf988 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -143,6 +143,10 @@ SECTIONS
"cpu_ops not defined for this platform.")
#if ENABLE_SPM
+#ifndef SPM_SHIM_EXCEPTIONS_VMA
+#define SPM_SHIM_EXCEPTIONS_VMA RAM
+#endif
+
/*
* Exception vectors of the SPM shim layer. They must be aligned to a 2K
* address, but we need to place them in a separate page so that we can set
@@ -156,7 +160,10 @@ SECTIONS
*(.spm_shim_exceptions)
. = ALIGN(PAGE_SIZE);
__SPM_SHIM_EXCEPTIONS_END__ = .;
- } >RAM
+ } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM
+
+ PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions));
+ . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions);
#endif
/*
diff --git a/include/plat/arm/common/arm_spm_def.h b/include/plat/arm/common/arm_spm_def.h
index 1c6f6e73d33ba24628f4876fc346060938fdf18e..997e156eea3fcf76ddc6933f488dc1c052a7095f 100644
--- a/include/plat/arm/common/arm_spm_def.h
+++ b/include/plat/arm/common/arm_spm_def.h
@@ -86,12 +86,12 @@
* requests. Mapped as RW and NS. Placed after the shared memory between EL3 and
* S-EL0.
*/
-#define ARM_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)
-#define ARM_SP_IMAGE_NS_BUF_SIZE ULL(0x10000)
+#define PLAT_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)
+#define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x10000)
#define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \
- ARM_SP_IMAGE_NS_BUF_BASE, \
- ARM_SP_IMAGE_NS_BUF_BASE, \
- ARM_SP_IMAGE_NS_BUF_SIZE, \
+ PLAT_SP_IMAGE_NS_BUF_BASE, \
+ PLAT_SP_IMAGE_NS_BUF_BASE, \
+ PLAT_SP_IMAGE_NS_BUF_SIZE, \
MT_RW_DATA | MT_NS | MT_USER, \
PAGE_SIZE)
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 628160824535d458065d864c2c89ea67bfb88ce8..d1c03be688c738a0b9c1a5f04decdec6cf23f8c7 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -46,8 +46,8 @@ typedef struct arm_tzc_regions_info {
PLAT_ARM_TZC_NS_DEV_ACCESS}, \
{ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- {ARM_SP_IMAGE_NS_BUF_BASE, (ARM_SP_IMAGE_NS_BUF_BASE + \
- ARM_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
+ {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \
+ PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
PLAT_ARM_TZC_NS_DEV_ACCESS}
#else
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 1a27fc469e5f936c8e39a66278472ff7207429a6..4da807a4c725cb27f7d2026a02cdc9e2113af9d5 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -215,12 +215,12 @@ const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
.sp_image_base = ARM_SP_IMAGE_BASE,
.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
.sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
- .sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE,
+ .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
.sp_shared_buf_base = PLAT_SPM_BUF_BASE,
.sp_image_size = ARM_SP_IMAGE_SIZE,
.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
.sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
- .sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE,
+ .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
.sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
.num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
.num_cpus = PLATFORM_CORE_COUNT,
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index ca4bd53996aac20401bec6d9e4eb1d35a78e0931..31f06a9881b2239a9a7378c10efca8028a3ad043 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -271,8 +271,8 @@
#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
#define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS
-#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
- ARM_SP_IMAGE_NS_BUF_SIZE)
+#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
+ PLAT_SP_IMAGE_NS_BUF_SIZE)
#define PLAT_SP_PRI PLAT_RAS_PRI
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index ad7ab81d958536f204945fda1f7e8395d888d03e..4afaae1d9ad528f3c7cd28f7a6adaebbe4304cc8 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -147,8 +147,8 @@
/* Allocate 128KB for CPER buffers */
#define PLAT_SP_BUF_BASE ULL(0x20000)
-#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
- ARM_SP_IMAGE_NS_BUF_SIZE + \
+#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
+ PLAT_SP_IMAGE_NS_BUF_SIZE + \
PLAT_SP_BUF_BASE)
/* Platform specific SMC FID's used for RAS */
@@ -171,8 +171,8 @@
SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL),
#define PLAT_ARM_SHARED_SDEI_EVENTS
-#define ARM_SP_CPER_BUF_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
- ARM_SP_IMAGE_NS_BUF_SIZE)
+#define ARM_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
+ PLAT_SP_IMAGE_NS_BUF_SIZE)
#define ARM_SP_CPER_BUF_SIZE ULL(0x20000)
#define ARM_SP_CPER_BUF_MMAP MAP_REGION2( \
ARM_SP_CPER_BUF_BASE, \
@@ -182,8 +182,8 @@
PAGE_SIZE)
#else
-#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
- ARM_SP_IMAGE_NS_BUF_SIZE)
+#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
+ PLAT_SP_IMAGE_NS_BUF_SIZE)
#endif /* RAS_EXTENSION */
/* Platform ID address */
diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c
index ca90aada9facde0355dd77cf9e530193be84e653..72cda7f15d22463b1a088e52c54f740b19071592 100644
--- a/plat/arm/css/sgi/sgi_plat.c
+++ b/plat/arm/css/sgi/sgi_plat.c
@@ -124,12 +124,12 @@ const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
.sp_image_base = ARM_SP_IMAGE_BASE,
.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
.sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
- .sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE,
+ .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
.sp_shared_buf_base = PLAT_SPM_BUF_BASE,
.sp_image_size = ARM_SP_IMAGE_SIZE,
.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
.sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
- .sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE,
+ .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
.sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
.num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
.num_cpus = PLATFORM_CORE_COUNT,
diff --git a/plat/socionext/synquacer/include/plat.ld.S b/plat/socionext/synquacer/include/plat.ld.S
new file mode 100644
index 0000000000000000000000000000000000000000..1b7f69989ebe1d1344f50a7fae2bb488fa8fcdd0
--- /dev/null
+++ b/plat/socionext/synquacer/include/plat.ld.S
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SYNQUACER_PLAT_LD_S__
+#define SYNQUACER_PLAT_LD_S__
+
+#include <xlat_tables_defs.h>
+
+#define SPM_SHIM_EXCEPTIONS_VMA SP_DRAM
+
+MEMORY {
+ SP_DRAM (rw): ORIGIN = PLAT_SQ_SP_PRIV_BASE, LENGTH = PLAT_SQ_SP_PRIV_SIZE
+}
+
+SECTIONS
+{
+ /*
+ * Put the page tables in secure DRAM so that the PTW can make cacheable
+ * accesses, as the core SPM code expects. (The SRAM on SynQuacer does
+ * not support inner shareable WBWA mappings so it is mapped normal
+ * non-cacheable)
+ */
+ sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) {
+ *(sp_xlat_table)
+ *(.bss.sp_base_xlat_table)
+ } >SP_DRAM
+}
+
+#endif /* SYNQUACER_PLAT_LD_S__ */
diff --git a/plat/socionext/synquacer/include/platform_def.h b/plat/socionext/synquacer/include/platform_def.h
index de6be7d231f4c89fd3de48e48cf42c042f801b9f..0cec81b8d0dce67aec7191422cb15bd98424b740 100644
--- a/plat/socionext/synquacer/include/platform_def.h
+++ b/plat/socionext/synquacer/include/platform_def.h
@@ -29,8 +29,8 @@
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#define MAX_XLAT_TABLES 4
-#define MAX_MMAP_REGIONS 6
+#define MAX_XLAT_TABLES 8
+#define MAX_MMAP_REGIONS 8
#define PLATFORM_STACK_SIZE 0x400
@@ -38,6 +38,10 @@
#define BL31_SIZE 0x00080000
#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
+#define BL32_BASE 0xfc000000
+#define BL32_SIZE 0x03c00000
+#define BL32_LIMIT (BL32_BASE + BL32_SIZE)
+
#define PLAT_SQ_CCN_BASE 0x32000000
#define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \
0, /* Cluster 0 */ \
@@ -79,4 +83,77 @@
#define PLAT_SQ_GPIO_BASE 0x51000000
+#define PLAT_SPM_BUF_BASE (BL32_LIMIT - 32 * PLAT_SPM_BUF_SIZE)
+#define PLAT_SPM_BUF_SIZE ULL(0x10000)
+#define PLAT_SPM_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \
+ PLAT_SPM_BUF_BASE, \
+ PLAT_SPM_BUF_SIZE, \
+ MT_RO_DATA | MT_SECURE | \
+ MT_USER, PAGE_SIZE)
+
+#define PLAT_SP_IMAGE_NS_BUF_BASE BL32_LIMIT
+#define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x200000)
+#define PLAT_SP_IMAGE_NS_BUF_MMAP MAP_REGION2(PLAT_SP_IMAGE_NS_BUF_BASE, \
+ PLAT_SP_IMAGE_NS_BUF_BASE, \
+ PLAT_SP_IMAGE_NS_BUF_SIZE, \
+ MT_RW_DATA | MT_NS | \
+ MT_USER, PAGE_SIZE)
+
+#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000)
+#define PLAT_SP_IMAGE_STACK_SIZE (32 * PLAT_SP_IMAGE_STACK_PCPU_SIZE)
+#define PLAT_SP_IMAGE_STACK_BASE (PLAT_SQ_SP_HEAP_BASE + PLAT_SQ_SP_HEAP_SIZE)
+
+#define PLAT_SQ_SP_IMAGE_SIZE ULL(0x200000)
+#define PLAT_SQ_SP_IMAGE_MMAP MAP_REGION2(BL32_BASE, BL32_BASE, \
+ PLAT_SQ_SP_IMAGE_SIZE, \
+ MT_CODE | MT_SECURE | \
+ MT_USER, PAGE_SIZE)
+
+#define PLAT_SQ_SP_HEAP_BASE (BL32_BASE + PLAT_SQ_SP_IMAGE_SIZE)
+#define PLAT_SQ_SP_HEAP_SIZE ULL(0x800000)
+
+#define PLAT_SQ_SP_IMAGE_RW_MMAP MAP_REGION2(PLAT_SQ_SP_HEAP_BASE, \
+ PLAT_SQ_SP_HEAP_BASE, \
+ (PLAT_SQ_SP_HEAP_SIZE + \
+ PLAT_SP_IMAGE_STACK_SIZE), \
+ MT_RW_DATA | MT_SECURE | \
+ MT_USER, PAGE_SIZE)
+
+#define PLAT_SQ_SP_PRIV_BASE (PLAT_SP_IMAGE_STACK_BASE + \
+ PLAT_SP_IMAGE_STACK_SIZE)
+#define PLAT_SQ_SP_PRIV_SIZE ULL(0x40000)
+
+#define PLAT_SP_PRI 0x20
+#define PLAT_PRI_BITS 2
+#define PLAT_SPM_COOKIE_0 ULL(0)
+#define PLAT_SPM_COOKIE_1 ULL(0)
+
+/* Total number of memory regions with distinct properties */
+#define PLAT_SP_IMAGE_NUM_MEM_REGIONS 6
+
+#define PLAT_SP_IMAGE_MMAP_REGIONS 30
+#define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20
+#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "sp_xlat_table"
+
+#define PLAT_SQ_UART1_BASE PLAT_SQ_BOOT_UART_BASE
+#define PLAT_SQ_UART1_SIZE ULL(0x1000)
+#define PLAT_SQ_UART1_MMAP MAP_REGION_FLAT(PLAT_SQ_UART1_BASE, \
+ PLAT_SQ_UART1_SIZE, \
+ MT_DEVICE | MT_RW | \
+ MT_NS | MT_PRIVILEGED)
+
+#define PLAT_SQ_PERIPH_BASE 0x50000000
+#define PLAT_SQ_PERIPH_SIZE ULL(0x8000000)
+#define PLAT_SQ_PERIPH_MMAP MAP_REGION_FLAT(PLAT_SQ_PERIPH_BASE, \
+ PLAT_SQ_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | \
+ MT_NS | MT_USER)
+
+#define PLAT_SQ_FLASH_BASE 0x08000000
+#define PLAT_SQ_FLASH_SIZE ULL(0x8000000)
+#define PLAT_SQ_FLASH_MMAP MAP_REGION_FLAT(PLAT_SQ_FLASH_BASE, \
+ PLAT_SQ_FLASH_SIZE, \
+ MT_DEVICE | MT_RW | \
+ MT_NS | MT_USER)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk
index 1bee20abbb66ae21a7063c890b8e35ecdaa463e4..53c39a0fc9c87ffac15710ed126bd3498d450fb5 100644
--- a/plat/socionext/synquacer/platform.mk
+++ b/plat/socionext/synquacer/platform.mk
@@ -17,10 +17,6 @@ ERRATA_A53_855873 := 1
# Libraries
include lib/xlat_tables_v2/xlat_tables.mk
-ifeq (${SPD},opteed)
-TF_CFLAGS_aarch64 += -DBL32_BASE=0xfc000000
-endif
-
PLAT_PATH := plat/socionext/synquacer
PLAT_INCLUDES := -I$(PLAT_PATH)/include \
-I$(PLAT_PATH)/drivers/scpi \
@@ -47,3 +43,9 @@ BL31_SOURCES += drivers/arm/ccn/ccn.c \
$(PLAT_PATH)/sq_xlat_setup.c \
$(PLAT_PATH)/drivers/scpi/sq_scpi.c \
$(PLAT_PATH)/drivers/mhu/sq_mhu.c
+
+ifeq (${ENABLE_SPM},1)
+$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
+
+BL31_SOURCES += $(PLAT_PATH)/sq_spm.c
+endif
diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c
index f8d252622c7c72f5a8ffbe7618c3d3e27e5faea6..2fac80ff00ea761547b92093736bcb1160272ed3 100644
--- a/plat/socionext/synquacer/sq_bl31_setup.c
+++ b/plat/socionext/synquacer/sq_bl31_setup.c
@@ -21,6 +21,10 @@ static console_pl011_t console;
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
+IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START);
+IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END);
+IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_LMA__, SPM_SHIM_EXCEPTIONS_LMA);
+
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
assert(sec_state_is_valid(type));
@@ -76,7 +80,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
/* Initialize power controller before setting up topology */
plat_sq_pwrc_setup();
-#ifdef BL32_BASE
+#ifdef SPD_opteed
struct draminfo di = {0};
scpi_get_draminfo(&di);
@@ -98,7 +102,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
} else {
NOTICE("OP-TEE has not been loaded by SCP firmware\n");
}
-#endif /* BL32_BASE */
+#endif /* SPD_opteed */
/* Populate entry point information for BL33 */
SET_PARAM_HEAD(&bl33_image_ep_info,
@@ -155,8 +159,27 @@ void bl31_plat_runtime_setup(void)
void bl31_plat_arch_setup(void)
{
- sq_mmap_setup(BL31_BASE, BL31_SIZE, NULL);
+ static const mmap_region_t secure_partition_mmap[] = {
+#if ENABLE_SPM && SPM_DEPRECATED
+ MAP_REGION_FLAT(PLAT_SPM_BUF_BASE,
+ PLAT_SPM_BUF_SIZE,
+ MT_RW_DATA | MT_SECURE),
+ MAP_REGION_FLAT(PLAT_SQ_SP_PRIV_BASE,
+ PLAT_SQ_SP_PRIV_SIZE,
+ MT_RW_DATA | MT_SECURE),
+#endif
+ {0},
+ };
+
+ sq_mmap_setup(BL31_BASE, BL31_SIZE, secure_partition_mmap);
enable_mmu_el3(XLAT_TABLE_NC);
+
+#if ENABLE_SPM && SPM_DEPRECATED
+ memcpy((void *)SPM_SHIM_EXCEPTIONS_START,
+ (void *)SPM_SHIM_EXCEPTIONS_LMA,
+ (uintptr_t)SPM_SHIM_EXCEPTIONS_END -
+ (uintptr_t)SPM_SHIM_EXCEPTIONS_START);
+#endif
}
void bl31_plat_enable_mmu(uint32_t flags)
diff --git a/plat/socionext/synquacer/sq_spm.c b/plat/socionext/synquacer/sq_spm.c
new file mode 100644
index 0000000000000000000000000000000000000000..01cce173992d24060fe03bd1d3e6e2a8702b09b0
--- /dev/null
+++ b/plat/socionext/synquacer/sq_spm.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <bl31/ehf.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <services/secure_partition.h>
+
+static const mmap_region_t plat_arm_secure_partition_mmap[] = {
+ PLAT_SQ_FLASH_MMAP,
+ PLAT_SQ_UART1_MMAP,
+ PLAT_SQ_PERIPH_MMAP,
+ PLAT_SQ_SP_IMAGE_MMAP,
+ PLAT_SP_IMAGE_NS_BUF_MMAP,
+ PLAT_SQ_SP_IMAGE_RW_MMAP,
+ PLAT_SPM_SPM_BUF_EL0_MMAP,
+ {0}
+};
+
+/*
+ * Boot information passed to a secure partition during initialisation. Linear
+ * indices in MP information will be filled at runtime.
+ */
+static secure_partition_mp_info_t sp_mp_info[] = {
+ {0x80000000, 0}, {0x80000001, 0}, {0x80000100, 0}, {0x80000101, 0},
+ {0x80000200, 0}, {0x80000201, 0}, {0x80000300, 0}, {0x80000301, 0},
+ {0x80000400, 0}, {0x80000401, 0}, {0x80000500, 0}, {0x80000501, 0},
+ {0x80000600, 0}, {0x80000601, 0}, {0x80000700, 0}, {0x80000701, 0},
+ {0x80000800, 0}, {0x80000801, 0}, {0x80000900, 0}, {0x80000901, 0},
+ {0x80000a00, 0}, {0x80000a01, 0}, {0x80000b00, 0}, {0x80000b01, 0},
+};
+
+const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
+ .h.type = PARAM_SP_IMAGE_BOOT_INFO,
+ .h.version = VERSION_1,
+ .h.size = sizeof(secure_partition_boot_info_t),
+ .h.attr = 0,
+ .sp_mem_base = BL32_BASE,
+ .sp_mem_limit = BL32_LIMIT,
+ .sp_image_base = BL32_BASE,
+ .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
+ .sp_heap_base = PLAT_SQ_SP_HEAP_BASE,
+ .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
+ .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
+ .sp_image_size = PLAT_SQ_SP_IMAGE_SIZE,
+ .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
+ .sp_heap_size = PLAT_SQ_SP_HEAP_SIZE,
+ .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
+ .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
+ .num_sp_mem_regions = PLAT_SP_IMAGE_NUM_MEM_REGIONS,
+ .num_cpus = PLATFORM_CORE_COUNT,
+ .mp_info = sp_mp_info,
+};
+
+const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
+{
+ return plat_arm_secure_partition_mmap;
+}
+
+const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
+ void *cookie)
+{
+ return &plat_arm_secure_partition_boot_info;
+}
+
+static ehf_pri_desc_t sq_exceptions[] = {
+ EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI),
+};
+EHF_REGISTER_PRIORITIES(sq_exceptions, ARRAY_SIZE(sq_exceptions), PLAT_PRI_BITS);
diff --git a/services/std_svc/spm_deprecated/spm.mk b/services/std_svc/spm_deprecated/spm.mk
index ed36812f9bf11254a3d64a290dc5b23751db4b13..35030206bab3104eb9cfac1a537bdc7fdbdafd86 100644
--- a/services/std_svc/spm_deprecated/spm.mk
+++ b/services/std_svc/spm_deprecated/spm.mk
@@ -21,3 +21,6 @@ SPM_SOURCES := $(addprefix services/std_svc/spm_deprecated/, \
# Let the top-level Makefile know that we intend to include a BL32 image
NEED_BL32 := yes
+
+# required so that SPM code executing at S-EL0 can access the timer registers
+NS_TIMER_SWITCH := 1
diff --git a/services/std_svc/spm_deprecated/spm_main.c b/services/std_svc/spm_deprecated/spm_main.c
index 540f257bd366ee513e15fbd9c14d85b71b8d34ab..7525763b181c00355e63d633b0689b2ec74ab45c 100644
--- a/services/std_svc/spm_deprecated/spm_main.c
+++ b/services/std_svc/spm_deprecated/spm_main.c
@@ -151,7 +151,7 @@ static int32_t spm_init(void)
INFO("Secure Partition initialized.\n");
- return rc;
+ return !rc;
}
/*******************************************************************************
diff --git a/services/std_svc/spm_deprecated/spm_setup.c b/services/std_svc/spm_deprecated/spm_setup.c
index d458f4a6a21ba27b8b544283f61daa0b37bc43e6..aae6cd5e2b4ba74b3db36920cff224f8ea4476d8 100644
--- a/services/std_svc/spm_deprecated/spm_setup.c
+++ b/services/std_svc/spm_deprecated/spm_setup.c
@@ -84,10 +84,10 @@ void spm_sp_setup(sp_context_t *sp_ctx)
unsigned int max_granule_mask = max_granule - 1U;
/* Base must be aligned to the max granularity */
- assert((ARM_SP_IMAGE_NS_BUF_BASE & max_granule_mask) == 0);
+ assert((PLAT_SP_IMAGE_NS_BUF_BASE & max_granule_mask) == 0);
/* Size must be a multiple of the max granularity */
- assert((ARM_SP_IMAGE_NS_BUF_SIZE & max_granule_mask) == 0);
+ assert((PLAT_SP_IMAGE_NS_BUF_SIZE & max_granule_mask) == 0);
#endif /* ENABLE_ASSERTIONS */
@@ -144,8 +144,6 @@ void spm_sp_setup(sp_context_t *sp_ctx)
SCTLR_SA0_BIT |
/* Allow cacheable data and instr. accesses to normal memory. */
SCTLR_C_BIT | SCTLR_I_BIT |
- /* Alignment fault checking enabled when at EL1 and EL0. */
- SCTLR_A_BIT |
/* Enable MMU. */
SCTLR_M_BIT
;
@@ -153,6 +151,11 @@ void spm_sp_setup(sp_context_t *sp_ctx)
sctlr_el1 &= ~(
/* Explicit data accesses at EL0 are little-endian. */
SCTLR_E0E_BIT |
+ /*
+ * Alignment fault checking disabled when at EL1 and EL0 as
+ * the UEFI spec permits unaligned accesses.
+ */
+ SCTLR_A_BIT |
/* Accesses to DAIF from EL0 are trapped to EL1. */
SCTLR_UMA_BIT
);
@@ -168,6 +171,9 @@ void spm_sp_setup(sp_context_t *sp_ctx)
write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1,
SPM_SHIM_EXCEPTIONS_PTR);
+ write_ctx_reg(get_sysregs_ctx(ctx), CTX_CNTKCTL_EL1,
+ EL0PTEN_BIT | EL0VTEN_BIT | EL0PCTEN_BIT | EL0VCTEN_BIT);
+
/*
* FPEN: Allow the Secure Partition to access FP/SIMD registers.
* Note that SPM will not do any saving/restoring of these registers on