Merge changes from topic "jc/shift-overflow" into integration

* changes:
  Enable -Wshift-overflow=2 to check for undefined shift behavior
  Update base code to not rely on undefined overflow behaviour
  Update hisilicon drivers to not rely on undefined overflow behaviour
  Update synopsys drivers to not rely on undefined overflow behaviour
  Update imx platform to not rely on undefined overflow behaviour
  Update mediatek platform to not rely on undefined overflow behaviour
  Update layerscape platform to not rely on undefined overflow behaviour
  Update intel platform to not rely on undefined overflow behaviour
  Update rockchip platform to not rely on undefined overflow behaviour
  Update renesas platform to not rely on undefined overflow behaviour
  Update meson platform to not rely on undefined overflow behaviour
  Update marvell platform to not rely on undefined overflow behaviour

Makefile

@@ -256,9 +256,14 @@ WARNINGS	+=		-Wunused -Wno-unused-parameter	\
 				-Wvla
 
 ifeq ($(findstring clang,$(notdir $(CC))),)
+# not using clang
 WARNINGS	+=		-Wunused-but-set-variable	\
 				-Wmaybe-uninitialized		\
-				-Wpacked-bitfield-compat
+				-Wpacked-bitfield-compat	\
+				-Wshift-overflow=2
+else
+# using clang
+WARNINGS	+=		-Wshift-overflow -Wshift-sign-overflow
 endif
 
 ifneq (${E},0)

drivers/marvell/mci.c

@@ -245,7 +245,7 @@
 				MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET)
 #define MCI_PHY_CTRL_PIDI_MODE_OFFSET			31
 #define MCI_PHY_CTRL_PIDI_MODE				\
-				(1 << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
+				(1U << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
 
 /* Number of times to wait for the MCI link ready after MCI configurations
  * Normally takes 34-35 successive reads

drivers/marvell/mochi/cp110_setup.c

@@ -56,11 +56,11 @@
 				(0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET)
 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET	16
 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK	\
-				(0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
+				(0xffffu << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
 
 #define MVEBU_SAMPLE_AT_RESET_REG	(0x440600)
 #define SAR_PCIE1_CLK_CFG_OFFSET	31
-#define SAR_PCIE1_CLK_CFG_MASK		(0x1 << SAR_PCIE1_CLK_CFG_OFFSET)
+#define SAR_PCIE1_CLK_CFG_MASK		(0x1u << SAR_PCIE1_CLK_CFG_OFFSET)
 #define SAR_PCIE0_CLK_CFG_OFFSET	30
 #define SAR_PCIE0_CLK_CFG_MASK		(0x1 << SAR_PCIE0_CLK_CFG_OFFSET)
 #define SAR_I2C_INIT_EN_OFFSET		24

drivers/meson/gxl/crypto/sha_dma.c

@@ -104,8 +104,8 @@ struct asd_desc {
 #define ASD_DESC_ERR_SET(d, v)					\
 	(ASD_DESC_SET((d)->cfg, v, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF))
 
-#define ASD_DESC_OWNER_OFF 31
-#define ASD_DESC_OWNER_MASK 0x1
+#define ASD_DESC_OWNER_OFF 31u
+#define ASD_DESC_OWNER_MASK 0x1u
 #define ASD_DESC_OWNER(d)					\
 	(ASD_DESC_GET((d)->cfg, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF))
 #define ASD_DESC_OWNER_SET(d, v)				\
@@ -126,7 +126,7 @@ static void asd_compute_sha(struct asd_ctx *ctx, void *data, size_t len,
 	assert((uintptr_t)&desc == (uintptr_t)&desc);
 
 	ASD_DESC_LEN_SET(&desc, len);
-	ASD_DESC_OWNER_SET(&desc, 1);
+	ASD_DESC_OWNER_SET(&desc, 1u);
 	ASD_DESC_ENCONLY_SET(&desc, 1);
 	ASD_DESC_EOD_SET(&desc, 1);
 	if (ctx->started == 0) {

drivers/renesas/rcar/cpld/ulcb_cpld.c

@@ -68,7 +68,7 @@ static void cpld_write(uint8_t addr, uint32_t data)
 
 	for (i = 0; i < 32; i++) {
 		/* MSB first */
-		gpio_set_value(GPIO_OUTDT6, MOSI, data & (1 << 31));
+		gpio_set_value(GPIO_OUTDT6, MOSI, data & (1U << 31));
 		gpio_set_value(GPIO_OUTDT6, SCLK, 1);
 		data <<= 1;
 		gpio_set_value(GPIO_OUTDT6, SCLK, 0);

drivers/renesas/rcar/pwrc/pwrc.c

@@ -763,10 +763,10 @@ uint32_t rcar_pwrc_get_cluster(void)
 
 	reg = mmio_read_32(RCAR_PRR);
 
-	if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
+	if (reg & (1U << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
 		return RCAR_CLUSTER_CA57;
 
-	if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
+	if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
 		return RCAR_CLUSTER_CA53;
 
 	return RCAR_CLUSTER_A53A57;
@@ -810,7 +810,7 @@ uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
 
 count_ca57:
 	if (IS_A53A57(c) || IS_CA57(c)) {
-		if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
+		if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
 			goto done;
 
 		for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {

drivers/renesas/rcar/pwrc/pwrc.h

@@ -15,7 +15,7 @@
 
 #define PWKUPR_WEN		(1ull << 31)
 
-#define PSYSR_AFF_L2		(1 << 31)
+#define PSYSR_AFF_L2		(1U << 31)
 #define PSYSR_AFF_L1		(1 << 30)
 #define PSYSR_AFF_L0		(1 << 29)
 #define PSYSR_WEN		(1 << 28)

drivers/synopsys/emmc/dw_mmc.c

@@ -14,6 +14,7 @@
 #include <drivers/delay_timer.h>
 #include <drivers/mmc.h>
 #include <drivers/synopsys/dw_mmc.h>
+#include <lib/utils_def.h>
 #include <lib/mmio.h>
 
 #define DWMMC_CTRL			(0x00)
@@ -55,7 +56,7 @@
 
 #define DWMMC_CMDARG			(0x28)
 #define DWMMC_CMD			(0x2c)
-#define CMD_START			(1 << 31)
+#define CMD_START			(U(1) << 31)
 #define CMD_USE_HOLD_REG		(1 << 29)	/* 0 if SDR50/100 */
 #define CMD_UPDATE_CLK_ONLY		(1 << 21)
 #define CMD_SEND_INIT			(1 << 15)
@@ -100,7 +101,7 @@
 #define IDMAC_DES0_CH			(1 << 4)
 #define IDMAC_DES0_ER			(1 << 5)
 #define IDMAC_DES0_CES			(1 << 30)
-#define IDMAC_DES0_OWN			(1 << 31)
+#define IDMAC_DES0_OWN			(U(1) << 31)
 #define IDMAC_DES1_BS1(x)		((x) & 0x1fff)
 #define IDMAC_DES2_BS2(x)		(((x) & 0x1fff) << 13)
 

include/drivers/ufs.h

@@ -82,7 +82,7 @@
 #define UECDME				0x48
 /* UTP Transfer Request Interrupt Aggregation Control Register */
 #define UTRIACR				0x4C
-#define UTRIACR_IAEN			(1 << 31)
+#define UTRIACR_IAEN			(1U << 31)
 #define UTRIACR_IAPWEN			(1 << 24)
 #define UTRIACR_IASB			(1 << 20)
 #define UTRIACR_CTR			(1 << 16)

lib/xlat_tables/aarch32/nonlpae_tables.c

@@ -122,8 +122,8 @@ CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
 #define DACR_DOMAIN_PERM_CLIENT		0x1
 #define DACR_DOMAIN_PERM_MANAGER	0x3
 
-#define NUM_1MB_IN_4GB		(1 << 12)
-#define NUM_4K_IN_1MB		(1 << 8)
+#define NUM_1MB_IN_4GB		(1U << 12)
+#define NUM_4K_IN_1MB		(1U << 8)
 
 #define ONE_MB_SHIFT		20
 

plat/hisilicon/hikey/hikey_ddr.c

@@ -138,7 +138,7 @@ static void init_freq(void)
 	mmio_write_32((0xf6504000 + 0x06c), data);
 
 	data = mmio_read_32((0xf6504000 + 0x06c));
-	data &= ~(0xffffff << 8);
+	data &= ~(0xffffffu << 8);
 	data |= 0xc7a << 8;
 	mmio_write_32((0xf6504000 + 0x06c), data);
 

plat/hisilicon/hikey/include/hi6220_regs_ao.h

@@ -222,14 +222,14 @@
 #define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK		(1 << 27)
 #define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK			(1 << 28)
 #define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK			(1 << 29)
-#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK			(1 << 31)
+#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK			(1U << 31)
 
 #define AO_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR			(1 << 26)
 #define AO_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR			(1 << 27)
 #define AO_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR			(1 << 28)
 #define AO_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR			(1 << 29)
 #define AO_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR			(1 << 30)
-#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR			(1 << 31)
+#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR			(1U << 31)
 
 #define AO_SC_SYS_STAT0_MCU_RST_STAT				(1 << 25)
 #define AO_SC_SYS_STAT0_MCU_SOFTRST_STAT			(1 << 26)
@@ -237,7 +237,7 @@
 #define AO_SC_SYS_STAT0_TSENSOR_HARDRST_STAT			(1 << 28)
 #define AO_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT			(1 << 29)
 #define AO_SC_SYS_STAT0_CM3_WDG1_RST_STAT			(1 << 30)
-#define AO_SC_SYS_STAT0_GLB_SRST_STAT				(1 << 31)
+#define AO_SC_SYS_STAT0_GLB_SRST_STAT				(1U << 31)
 
 #define AO_SC_SYS_STAT1_MODE_STATUS				(1 << 0)
 #define AO_SC_SYS_STAT1_BOOT_SEL_LOCK				(1 << 16)
@@ -308,7 +308,7 @@
 #define AO_SC_PERIPH_CLKEN4_CLK_JTAG_AUTH			(1 << 28)
 #define AO_SC_PERIPH_CLKEN4_CLK_CS_DAPB_ON			(1 << 29)
 #define AO_SC_PERIPH_CLKEN4_CLK_PDM				(1 << 30)
-#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD				(1 << 31)
+#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD				(1U << 31)
 
 #define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU			(1 << 0)
 #define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_CCPU			(1 << 1)

plat/hisilicon/hikey/include/hi6220_regs_peri.h

@@ -134,7 +134,7 @@
 #define PERI_CTRL4_OTG_SESSEND			(1 << 28)
 #define PERI_CTRL4_OTG_BVALID			(1 << 29)
 #define PERI_CTRL4_OTG_AVALID			(1 << 30)
-#define PERI_CTRL4_OTG_VBUSVALID		(1 << 31)
+#define PERI_CTRL4_OTG_VBUSVALID		(1U << 31)
 
 /* PERI_SC_PERIPH_CTRL5 */
 #define PERI_CTRL5_USBOTG_RES_SEL		(1 << 3)

plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c

@@ -23,7 +23,7 @@
 #define RES2_LOCK_BASE		(SOC_PCTRL_RESOURCE2_LOCK_ADDR(PCTRL_BASE))
 
 #define LOCK_BIT			(0x1 << 28)
-#define LOCK_ID_MASK			(0x7 << 29)
+#define LOCK_ID_MASK			(0x7u << 29)
 #define CPUIDLE_LOCK_ID(core)		(0x6 - (core))
 #define LOCK_UNLOCK_OFFSET		0x4
 #define LOCK_STAT_OFFSET		0x8

plat/hisilicon/hikey960/include/hi3660.h

@@ -67,7 +67,7 @@
 #define SCTRL_SCPERDIS1_REG		(SCTRL_REG_BASE + 0x174)
 #define SCTRL_SCPEREN1_REG		(SCTRL_REG_BASE + 0x170)
 #define SCTRL_SCPERDIS1_REG		(SCTRL_REG_BASE + 0x174)
-#define SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS	(1 << 31)
+#define SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS	(1u << 31)
 #define SCPEREN_GT_PCLK_MMBUFCFG	(1 << 25)
 #define SCPEREN_GT_PCLK_MMBUF		(1 << 23)
 #define SCPEREN_GT_ACLK_MMBUF		(1 << 22)

plat/hisilicon/hikey960/include/hi3660_crg.h

@@ -11,7 +11,7 @@
 #define CRG_PEREN0_REG			(CRG_REG_BASE + 0x000)
 #define CRG_PERDIS0_REG			(CRG_REG_BASE + 0x004)
 #define CRG_PERSTAT0_REG		(CRG_REG_BASE + 0x008)
-#define PEREN0_GT_CLK_AOMM		(1 << 31)
+#define PEREN0_GT_CLK_AOMM		(1U << 31)
 
 #define CRG_PEREN1_REG			(CRG_REG_BASE + 0x010)
 #define CRG_PERDIS1_REG			(CRG_REG_BASE + 0x014)
@@ -62,7 +62,7 @@
 #define CRG_PERRSTSTAT5_REG		(CRG_REG_BASE + 0x0A4)
 
 /* bit fields in CRG_PERI */
-#define PERI_PCLK_PCTRL_BIT		(1 << 31)
+#define PERI_PCLK_PCTRL_BIT		(1U << 31)
 #define PERI_TIMER12_BIT		(1 << 25)
 #define PERI_TIMER11_BIT		(1 << 24)
 #define PERI_TIMER10_BIT		(1 << 23)

plat/hisilicon/hikey960/include/hi3660_hkadc.h

@@ -13,7 +13,7 @@
 #define HKADC_DSP_START_CLR_REG			(HKADC_SSI_REG_BASE + 0x01C)
 #define HKADC_WR01_DATA_REG			(HKADC_SSI_REG_BASE + 0x020)
 
-#define WR1_WRITE_MODE				(1 << 31)
+#define WR1_WRITE_MODE				(1U << 31)
 #define WR1_READ_MODE				(0 << 31)
 #define WR1_ADDR(x)				(((x) & 0x7F) << 24)
 #define WR1_DATA(x)				(((x) & 0xFF) << 16)
@@ -47,7 +47,7 @@
 
 #define HKADC_WR01_VALUE			((HKADC_START_ADDR << 24) | \
 						 (0x1 << 16))
-#define HKADC_WR23_VALUE			((0x1 << 31) |		\
+#define HKADC_WR23_VALUE			((0x1u << 31) |		\
 						 (HKADC_DATA0_ADDR << 24) | \
 						 (1 << 15) |		\
 						 (HKADC_DATA1_ADDR << 8))

plat/imx/common/sci/imx8_mu.h

@@ -13,7 +13,7 @@
 #define MU_TR_COUNT1		4
 #define MU_RR_COUNT1		4
 
-#define MU_CR_GIEn_MASK1	(0xF << 28)
+#define MU_CR_GIEn_MASK1	(0xFu << 28)
 #define MU_CR_RIEn_MASK1	(0xF << 24)
 #define MU_CR_TIEn_MASK1	(0xF << 20)
 #define MU_CR_GIRn_MASK1	(0xF << 16)
@@ -23,7 +23,7 @@
 #define MU_SR_TE0_MASK1		(1 << 23)
 #define MU_SR_RF0_MASK1		(1 << 27)
 #define MU_CR_RIE0_MASK1	(1 << 27)
-#define MU_CR_GIE0_MASK1	(1 << 31)
+#define MU_CR_GIE0_MASK1	(1U << 31)
 
 #define MU_TR_COUNT			4
 #define MU_RR_COUNT			4

plat/intel/soc/common/drivers/qspi/cadence_qspi.h

@@ -34,7 +34,7 @@
 #define CAD_QSPI_CFG_CS(x)			(((x) << 11))
 #define CAD_QSPI_CFG_ENABLE			(1 << 0)
 #define CAD_QSPI_CFG_ENDMA_CLR_MSK		0xffff7fff
-#define CAD_QSPI_CFG_IDLE			(1 << 31)
+#define CAD_QSPI_CFG_IDLE			(1U << 31)
 #define CAD_QSPI_CFG_SELCLKPHASE_CLR_MSK	0xfffffffb
 #define CAD_QSPI_CFG_SELCLKPOL_CLR_MSK		0xfffffffd
 

plat/intel/soc/stratix10/include/s10_mailbox.h

@@ -76,7 +76,7 @@
 #define RECONFIG_STATUS_STATE		0
 #define RECONFIG_STATUS_PIN_STATUS	2
 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3
-#define PIN_STATUS_NSTATUS		(1 << 31)
+#define PIN_STATUS_NSTATUS		(1U << 31)
 #define SOFTFUNC_STATUS_SEU_ERROR	(1 << 3)
 #define SOFTFUNC_STATUS_INIT_DONE	(1 << 1)
 #define SOFTFUNC_STATUS_CONF_DONE	(1 << 0)