From d200f2306463b28fc2650939ac9bcc0d701fa2d5 Mon Sep 17 00:00:00 2001
From: John Tsichritzis <john.tsichritzis@arm.com>
Date: Mon, 1 Jul 2019 14:27:33 +0100
Subject: [PATCH] Refactor SPSR initialisation code
Change-Id: Ic3b30de13e314efca30fc71370227d3e76f1148b
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
---
bl1/aarch32/bl1_context_mgmt.c | 19 ++++++-------------
bl1/aarch64/bl1_context_mgmt.c | 19 ++++++-------------
2 files changed, 12 insertions(+), 26 deletions(-)
diff --git a/bl1/aarch32/bl1_context_mgmt.c b/bl1/aarch32/bl1_context_mgmt.c
index 005d046cc..b5a6a3417 100644
--- a/bl1/aarch32/bl1_context_mgmt.c
+++ b/bl1/aarch32/bl1_context_mgmt.c
@@ -102,7 +102,7 @@ static void flush_smc_and_cpu_ctx(void)
******************************************************************************/
void bl1_prepare_next_image(unsigned int image_id)
{
- unsigned int security_state;
+ unsigned int security_state, mode = MODE32_svc;
image_desc_t *image_desc;
entry_point_info_t *next_bl_ep;
@@ -117,20 +117,13 @@ void bl1_prepare_next_image(unsigned int image_id)
security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
/* Prepare the SPSR for the next BL image. */
- if (security_state == SECURE) {
- next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
- SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
- } else {
- /* Use HYP mode if supported else use SVC. */
- if (GET_VIRT_EXT(read_id_pfr1())) {
- next_bl_ep->spsr = SPSR_MODE32(MODE32_hyp, SPSR_T_ARM,
- SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
- } else {
- next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
- SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
- }
+ if ((security_state != SECURE) && (GET_VIRT_EXT(read_id_pfr1()))) {
+ mode = MODE32_hyp;
}
+ next_bl_ep->spsr = SPSR_MODE32(mode, SPSR_T_ARM,
+ SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
+
/* Allow platform to make change */
bl1_plat_set_ep_info(image_id, next_bl_ep);
diff --git a/bl1/aarch64/bl1_context_mgmt.c b/bl1/aarch64/bl1_context_mgmt.c
index 032631905..8be8830a3 100644
--- a/bl1/aarch64/bl1_context_mgmt.c
+++ b/bl1/aarch64/bl1_context_mgmt.c
@@ -42,7 +42,7 @@ void cm_set_context(void *context, uint32_t security_state)
******************************************************************************/
void bl1_prepare_next_image(unsigned int image_id)
{
- unsigned int security_state;
+ unsigned int security_state, mode = MODE_EL1;
image_desc_t *image_desc;
entry_point_info_t *next_bl_ep;
@@ -73,20 +73,13 @@ void bl1_prepare_next_image(unsigned int image_id)
cm_set_context(&bl1_cpu_context[security_state], security_state);
/* Prepare the SPSR for the next BL image. */
- if (security_state == SECURE) {
- next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
- } else {
- /* Use EL2 if supported; else use EL1. */
- if (el_implemented(2) != EL_IMPL_NONE) {
- next_bl_ep->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
- } else {
- next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
- }
+ if ((security_state != SECURE) && (el_implemented(2) != EL_IMPL_NONE)) {
+ mode = MODE_EL2;
}
+ next_bl_ep->spsr = SPSR_64(mode, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS);
+
/* Allow platform to make change */
bl1_plat_set_ep_info(image_id, next_bl_ep);
--
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