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Commit d232ca5f authored by Manish Pandey's avatar Manish Pandey Committed by TrustedFirmware Code Review
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Merge changes from topics "rddaniel", "rdn1edge_dual" into integration 

* changes:
  plat/arm: add board support for rd-daniel platform
  plat/arm/sgi: move GIC related constants to board files
  platform/arm/sgi: add multi-chip mode parameter in HW_CONFIG dts
  board/rdn1edge: add support for dual-chip configuration
  drivers/arm/scmi: allow use of multiple SCMI channels
  drivers/mhu: derive doorbell base address
  plat/arm/sgi: include AFF3 affinity in core position calculation
  plat/arm/sgi: add macros for remote chip device region
  plat/arm/sgi: add chip_id and multi_chip_mode to platform variant info
  plat/arm/sgi: move bl31_platform_setup to board file
parents 1f6b06c8 2103a73b
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plat/arm/board/rde1edge/rde1edge_plat.c
View file @ d232ca5f
/* /*
* Copyright (c) 2018, Arm Limited. All rights reserved. * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include <sgi_plat.h>
unsigned int plat_arm_sgi_get_platform_id(void) unsigned int plat_arm_sgi_get_platform_id(void)
{ {
...@@ -16,3 +17,13 @@ unsigned int plat_arm_sgi_get_config_id(void) ...@@ -16,3 +17,13 @@ unsigned int plat_arm_sgi_get_config_id(void)
{ {
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET); return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
} }
unsigned int plat_arm_sgi_get_multi_chip_mode(void)
{
return 0;
}
void bl31_platform_setup(void)
{
sgi_bl31_common_platform_setup();
}
plat/arm/board/rdn1edge/fdts/rdn1edge_nt_fw_config.dts
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -17,5 +17,6 @@ ...@@ -17,5 +17,6 @@
system-id { system-id {
platform-id = <0x0>; platform-id = <0x0>;
config-id = <0x0>; config-id = <0x0>;
multi-chip-mode = <0x0>;
}; };
}; };
plat/arm/board/rdn1edge/include/platform_def.h
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -16,7 +16,6 @@ ...@@ -16,7 +16,6 @@
#define CSS_SGI_MAX_PE_PER_CPU U(1) #define CSS_SGI_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000) #define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
/* Base address of DMC-620 instances */ /* Base address of DMC-620 instances */
#define RDN1EDGE_DMC620_BASE0 UL(0x4e000000) #define RDN1EDGE_DMC620_BASE0 UL(0x4e000000)
...@@ -27,15 +26,23 @@ ...@@ -27,15 +26,23 @@
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/* Virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
/* /*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/ */
#ifdef __aarch64__ #ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43)
#else #else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#endif #endif
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x300C0000)
#endif /* PLATFORM_DEF_H */ #endif /* PLATFORM_DEF_H */
plat/arm/board/rdn1edge/platform.mk
View file @ d232ca5f
...@@ -26,6 +26,7 @@ BL31_SOURCES += ${SGI_CPU_SOURCES} \ ...@@ -26,6 +26,7 @@ BL31_SOURCES += ${SGI_CPU_SOURCES} \
${RDN1EDGE_BASE}/rdn1edge_plat.c \ ${RDN1EDGE_BASE}/rdn1edge_plat.c \
${RDN1EDGE_BASE}/rdn1edge_topology.c \ ${RDN1EDGE_BASE}/rdn1edge_topology.c \
drivers/cfi/v2m/v2m_flash.c \ drivers/cfi/v2m/v2m_flash.c \
drivers/arm/gic/v3/gic600_multichip.c \
lib/utils/mem_region.c \ lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c plat/arm/common/arm_nor_psci_mem_protect.c
...@@ -34,6 +35,9 @@ BL1_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c ...@@ -34,6 +35,9 @@ BL1_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
endif endif
# Enable dynamic addition of MMAP regions in BL31
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
# Add the FDT_SOURCES and options for Dynamic Config # Add the FDT_SOURCES and options for Dynamic Config
FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
...@@ -47,9 +51,9 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb ...@@ -47,9 +51,9 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool # Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config)) $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
ifneq ($(CSS_SGI_CHIP_COUNT),1) ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),1 2))
$(error "Chip count for RDN1Edge should be 1, currently set to \ $(error "Chip count for RDN1Edge platform should either 1 or 2, currently \
${CSS_SGI_CHIP_COUNT}.") set to ${CSS_SGI_CHIP_COUNT}.")
endif endif
override CTX_INCLUDE_AARCH32_REGS := 0 override CTX_INCLUDE_AARCH32_REGS := 0
plat/arm/board/rdn1edge/rdn1edge_plat.c
View file @ d232ca5f
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <common/debug.h>
#include <drivers/arm/gic600_multichip.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include <sgi_base_platform_def.h>
#include <sgi_plat.h>
#if defined(IMAGE_BL31)
static const mmap_region_t rdn1edge_dynamic_mmap[] = {
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1)
};
static struct gic600_multichip_data rdn1e1_multichip_data __init = {
.rt_owner_base = PLAT_ARM_GICD_BASE,
.rt_owner = 0,
.chip_count = CSS_SGI_CHIP_COUNT,
.chip_addrs = {
PLAT_ARM_GICD_BASE >> 16,
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
},
.spi_ids = {
{32, 255},
{0, 0}
}
};
static uintptr_t rdn1e1_multichip_gicr_frames[] = {
PLAT_ARM_GICR_BASE, /* Chip 0's GICR Base */
PLAT_ARM_GICR_BASE +
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1), /* Chip 1's GICR BASE */
UL(0) /* Zero Termination */
};
#endif /* IMAGE_BL31 */
unsigned int plat_arm_sgi_get_platform_id(void) unsigned int plat_arm_sgi_get_platform_id(void)
{ {
...@@ -16,3 +50,48 @@ unsigned int plat_arm_sgi_get_config_id(void) ...@@ -16,3 +50,48 @@ unsigned int plat_arm_sgi_get_config_id(void)
{ {
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET); return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
} }
unsigned int plat_arm_sgi_get_multi_chip_mode(void)
{
return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
}
/*
* IMAGE_BL31 macro is added to build bl31_platform_setup function only for BL31
* because PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not
* for other stages.
*/
#if defined(IMAGE_BL31)
void bl31_platform_setup(void)
{
int i, ret;
if (plat_arm_sgi_get_multi_chip_mode() == 0 && CSS_SGI_CHIP_COUNT > 1) {
ERROR("Chip Count is set to %d but multi-chip mode not enabled\n",
CSS_SGI_CHIP_COUNT);
panic();
} else if (plat_arm_sgi_get_multi_chip_mode() == 1 &&
CSS_SGI_CHIP_COUNT > 1) {
INFO("Enabling support for multi-chip in RD-N1-Edge\n");
for (i = 0; i < ARRAY_SIZE(rdn1edge_dynamic_mmap); i++) {
ret = mmap_add_dynamic_region(
rdn1edge_dynamic_mmap[i].base_pa,
rdn1edge_dynamic_mmap[i].base_va,
rdn1edge_dynamic_mmap[i].size,
rdn1edge_dynamic_mmap[i].attr
);
if (ret != 0) {
ERROR("Failed to add dynamic mmap entry\n");
panic();
}
}
plat_arm_override_gicr_frames(rdn1e1_multichip_gicr_frames);
gic600_multichip_init(&rdn1e1_multichip_data);
}
sgi_bl31_common_platform_setup();
}
#endif /* IMAGE_BL31 */
plat/arm/board/rdn1edge/rdn1edge_topology.c
View file @ d232ca5f
...@@ -5,14 +5,19 @@ ...@@ -5,14 +5,19 @@
*/ */
#include <plat/arm/common/plat_arm.h> #include <plat/arm/common/plat_arm.h>
#include <plat/arm/css/common/css_pm.h>
/****************************************************************************** /******************************************************************************
* The power domain tree descriptor. * The power domain tree descriptor.
******************************************************************************/ ******************************************************************************/
static const unsigned char rdn1edge_pd_tree_desc[] = { static const unsigned char rdn1edge_pd_tree_desc[] = {
PLAT_ARM_CLUSTER_COUNT, (PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT),
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#if (CSS_SGI_CHIP_COUNT > 1)
CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER CSS_SGI_MAX_CPUS_PER_CLUSTER
#endif
}; };
/******************************************************************************* /*******************************************************************************
...@@ -28,5 +33,22 @@ const unsigned char *plat_get_power_domain_tree_desc(void) ...@@ -28,5 +33,22 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
* to the SCMI power domain ID implemented by SCP. * to the SCMI power domain ID implemented by SCP.
******************************************************************************/ ******************************************************************************/
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
0, 1, 2, 3, 4, 5, 6, 7 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
#if (CSS_SGI_CHIP_COUNT > 1)
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x4)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x5)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x6)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x7)),
#endif
}; };
plat/arm/board/sgi575/fdts/sgi575_nt_fw_config.dts
View file @ d232ca5f
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -17,5 +17,6 @@ ...@@ -17,5 +17,6 @@
system-id { system-id {
platform-id = <0x0>; platform-id = <0x0>;
config-id = <0x0>; config-id = <0x0>;
multi-chip-mode = <0x0>;
}; };
}; };
plat/arm/board/sgi575/include/platform_def.h
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -16,7 +16,6 @@ ...@@ -16,7 +16,6 @@
#define CSS_SGI_MAX_PE_PER_CPU U(1) #define CSS_SGI_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45000000) #define PLAT_CSS_MHU_BASE UL(0x45000000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
/* Base address of DMC-620 instances */ /* Base address of DMC-620 instances */
#define SGI575_DMC620_BASE0 UL(0x4e000000) #define SGI575_DMC620_BASE0 UL(0x4e000000)
...@@ -38,4 +37,9 @@ ...@@ -38,4 +37,9 @@
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#endif #endif
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x300C0000)
#endif /* PLATFORM_DEF_H */ #endif /* PLATFORM_DEF_H */
plat/arm/board/sgi575/sgi575_plat.c
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include <sgi_plat.h>
#include <sgi_variant.h> #include <sgi_variant.h>
unsigned int plat_arm_sgi_get_platform_id(void) unsigned int plat_arm_sgi_get_platform_id(void)
...@@ -18,3 +18,13 @@ unsigned int plat_arm_sgi_get_config_id(void) ...@@ -18,3 +18,13 @@ unsigned int plat_arm_sgi_get_config_id(void)
return (mmio_read_32(SSC_VERSION) >> SSC_VERSION_CONFIG_SHIFT) return (mmio_read_32(SSC_VERSION) >> SSC_VERSION_CONFIG_SHIFT)
& SSC_VERSION_CONFIG_MASK; & SSC_VERSION_CONFIG_MASK;
} }
unsigned int plat_arm_sgi_get_multi_chip_mode(void)
{
return 0;
}
void bl31_platform_setup(void)
{
sgi_bl31_common_platform_setup();
}
plat/arm/css/sgi/aarch64/sgi_helper.S
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -18,19 +18,22 @@ ...@@ -18,19 +18,22 @@
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr) * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
* *
* Helper function to calculate the core position. * Helper function to calculate the core position.
* (ChipId * PLAT_ARM_CLUSTER_COUNT *
* CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
* (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) + * (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
* (CPUId * CSS_SGI_MAX_PE_PER_CPU) + * (CPUId * CSS_SGI_MAX_PE_PER_CPU) +
* ThreadId * ThreadId
* *
* which can be simplified as: * which can be simplified as:
* *
* ((ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER + CPUId) * * ((((ChipId * PLAT_ARM_CLUSTER_COUNT) + ClusterId) *
* CSS_SGI_MAX_PE_PER_CPU) + ThreadId * CSS_SGI_MAX_CPUS_PER_CLUSTER) + CPUId) * CSS_SGI_MAX_PE_PER_CPU +
* ThreadId
* ------------------------------------------------------ * ------------------------------------------------------
*/ */
func plat_arm_calc_core_pos func plat_arm_calc_core_pos
mov x3, x0 mov x4, x0
/* /*
* The MT bit in MPIDR is always set for SGI platforms * The MT bit in MPIDR is always set for SGI platforms
...@@ -38,15 +41,18 @@ func plat_arm_calc_core_pos ...@@ -38,15 +41,18 @@ func plat_arm_calc_core_pos
*/ */
/* Extract individual affinity fields from MPIDR */ /* Extract individual affinity fields from MPIDR */
ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
/* Compute linear position */ /* Compute linear position */
mov x4, #PLAT_ARM_CLUSTER_COUNT
madd x2, x3, x4, x2
mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER
madd x1, x2, x4, x1 madd x1, x2, x4, x1
mov x5, #CSS_SGI_MAX_PE_PER_CPU mov x4, #CSS_SGI_MAX_PE_PER_CPU
madd x0, x1, x5, x0 madd x0, x1, x4, x0
ret ret
endfunc plat_arm_calc_core_pos endfunc plat_arm_calc_core_pos
......
plat/arm/css/sgi/include/sgi_base_platform_def.h
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -17,12 +17,16 @@ ...@@ -17,12 +17,16 @@
#include <plat/arm/soc/common/soc_css_def.h> #include <plat/arm/soc/common/soc_css_def.h>
#include <plat/common/common_def.h> #include <plat/common/common_def.h>
#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ #define PLATFORM_CORE_COUNT (CSS_SGI_CHIP_COUNT * \
CSS_SGI_MAX_CPUS_PER_CLUSTER * \ PLAT_ARM_CLUSTER_COUNT * \
CSS_SGI_MAX_CPUS_PER_CLUSTER * \
CSS_SGI_MAX_PE_PER_CPU) CSS_SGI_MAX_PE_PER_CPU)
#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
/* Remote chip address offset (4TB per chip) */
#define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) ((ULL(1) << 42) * (n))
/* /*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage. * plat_arm_mmap array defined for each BL stage.
...@@ -35,14 +39,14 @@ ...@@ -35,14 +39,14 @@
# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
# else # else
# define PLAT_ARM_MMAP_ENTRIES 8 # define PLAT_ARM_MMAP_ENTRIES 8
# define MAX_XLAT_TABLES 5 # define MAX_XLAT_TABLES 8
# endif # endif
#elif defined(IMAGE_BL32) #elif defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES 8 # define PLAT_ARM_MMAP_ENTRIES 8
# define MAX_XLAT_TABLES 5 # define MAX_XLAT_TABLES 5
#elif !USE_ROMLIB #elif !USE_ROMLIB
# define PLAT_ARM_MMAP_ENTRIES 11 # define PLAT_ARM_MMAP_ENTRIES 11
# define MAX_XLAT_TABLES 5 # define MAX_XLAT_TABLES 7
#else #else
# define PLAT_ARM_MMAP_ENTRIES 12 # define PLAT_ARM_MMAP_ENTRIES 12
# define MAX_XLAT_TABLES 6 # define MAX_XLAT_TABLES 6
...@@ -129,10 +133,29 @@ ...@@ -129,10 +133,29 @@
CSS_SGI_DEVICE_SIZE, \ CSS_SGI_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE) MT_DEVICE | MT_RW | MT_SECURE)
/* GIC related constants */ #define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n) \
#define PLAT_ARM_GICD_BASE 0x30000000 MAP_REGION_FLAT( \
#define PLAT_ARM_GICC_BASE 0x2C000000 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
#define PLAT_ARM_GICR_BASE 0x300C0000 ARM_SHARED_RAM_BASE, \
ARM_SHARED_RAM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE \
)
#define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \
MAP_REGION_FLAT( \
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
CSS_SGI_DEVICE_BASE, \
CSS_SGI_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE \
)
#define SOC_CSS_MAP_DEVICE_REMOTE_CHIP(n) \
MAP_REGION_FLAT( \
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
SOC_CSS_DEVICE_BASE, \
SOC_CSS_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE \
)
/* Map the secure region for access from S-EL0 */ /* Map the secure region for access from S-EL0 */
#define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \ #define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \
...@@ -212,4 +235,7 @@ ...@@ -212,4 +235,7 @@
#define SBSA_SECURE_WDOG_BASE UL(0x2A480000) #define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
#define SBSA_SECURE_WDOG_TIMEOUT UL(100) #define SBSA_SECURE_WDOG_TIMEOUT UL(100)
/* Number of SCMI channels on the platform */
#define PLAT_ARM_SCMI_CHANNEL_COUNT CSS_SGI_CHIP_COUNT
#endif /* SGI_BASE_PLATFORM_DEF_H */ #endif /* SGI_BASE_PLATFORM_DEF_H */
plat/arm/css/sgi/include/sgi_plat.h 0 → 100644
View file @ d232ca5f
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SGI_PLAT_H
#define SGI_PLAT_H
/* BL31 platform setup common to all SGI based platforms */
void sgi_bl31_common_platform_setup(void);
#endif /* SGI_PLAT_H */
plat/arm/css/sgi/include/sgi_variant.h
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -8,16 +8,21 @@ ...@@ -8,16 +8,21 @@
#define SGI_VARIANT_H #define SGI_VARIANT_H
/* SSC_VERSION values for SGI575 */ /* SSC_VERSION values for SGI575 */
#define SGI575_SSC_VER_PART_NUM 0x0783 #define SGI575_SSC_VER_PART_NUM 0x0783
/* SID Version values for RD-N1E1-Edge */ /* SID Version values for RD-N1E1-Edge */
#define RD_N1E1_EDGE_SID_VER_PART_NUM 0x0786 #define RD_N1E1_EDGE_SID_VER_PART_NUM 0x0786
#define RD_E1_EDGE_CONFIG_ID 0x2 #define RD_E1_EDGE_CONFIG_ID 0x2
/* SID Version values for RD-Daniel */
#define RD_DANIEL_SID_VER_PART_NUM 0x078a
/* Structure containing SGI platform variant information */ /* Structure containing SGI platform variant information */
typedef struct sgi_platform_info { typedef struct sgi_platform_info {
unsigned int platform_id; /* Part Number of the platform */ unsigned int platform_id; /* Part Number of the platform */
unsigned int config_id; /* Config Id of the platform */ unsigned int config_id; /* Config Id of the platform */
unsigned int chip_id; /* Chip Id or Node number */
unsigned int multi_chip_mode; /* Multi-chip mode availability */
} sgi_platform_info_t; } sgi_platform_info_t;
extern sgi_platform_info_t sgi_plat_info; extern sgi_platform_info_t sgi_plat_info;
...@@ -28,4 +33,7 @@ unsigned int plat_arm_sgi_get_platform_id(void); ...@@ -28,4 +33,7 @@ unsigned int plat_arm_sgi_get_platform_id(void);
/* returns the configuration id of the platform */ /* returns the configuration id of the platform */
unsigned int plat_arm_sgi_get_config_id(void); unsigned int plat_arm_sgi_get_config_id(void);
/* returns true if operating in multi-chip configuration */
unsigned int plat_arm_sgi_get_multi_chip_mode(void);
#endif /* SGI_VARIANT_H */ #endif /* SGI_VARIANT_H */
plat/arm/css/sgi/sgi_bl31_setup.c
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -28,18 +28,57 @@ static scmi_channel_plat_info_t sgi575_scmi_plat_info = { ...@@ -28,18 +28,57 @@ static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
.ring_doorbell = &mhu_ring_doorbell, .ring_doorbell = &mhu_ring_doorbell,
}; };
static scmi_channel_plat_info_t rd_n1e1_edge_scmi_plat_info = { static scmi_channel_plat_info_t rd_n1e1_edge_scmi_plat_info[] = {
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
.db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
.db_preserve_mask = 0xfffffffe, .db_preserve_mask = 0xfffffffe,
.db_modify_mask = 0x1, .db_modify_mask = 0x1,
.ring_doorbell = &mhuv2_ring_doorbell, .ring_doorbell = &mhuv2_ring_doorbell,
},
#if (CSS_SGI_CHIP_COUNT > 1)
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
.db_reg_addr = PLAT_CSS_MHU_BASE
+ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1) + SENDER_REG_SET(0),
.db_preserve_mask = 0xfffffffe,
.db_modify_mask = 0x1,
.ring_doorbell = &mhuv2_ring_doorbell,
},
#endif
#if (CSS_SGI_CHIP_COUNT > 2)
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
.db_reg_addr = PLAT_CSS_MHU_BASE +
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2) + SENDER_REG_SET(0),
.db_preserve_mask = 0xfffffffe,
.db_modify_mask = 0x1,
.ring_doorbell = &mhuv2_ring_doorbell,
},
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
.db_reg_addr = PLAT_CSS_MHU_BASE +
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3) + SENDER_REG_SET(0),
.db_preserve_mask = 0xfffffffe,
.db_modify_mask = 0x1,
.ring_doorbell = &mhuv2_ring_doorbell,
},
#endif
}; };
scmi_channel_plat_info_t *plat_css_get_scmi_info(void) scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
{ {
if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
return &rd_n1e1_edge_scmi_plat_info; sgi_plat_info.platform_id == RD_DANIEL_SID_VER_PART_NUM) {
if (channel_id >= sizeof(rd_n1e1_edge_scmi_plat_info))
panic();
return &rd_n1e1_edge_scmi_plat_info[channel_id];
}
else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM) else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM)
return &sgi575_scmi_plat_info; return &sgi575_scmi_plat_info;
else else
...@@ -51,11 +90,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, ...@@ -51,11 +90,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
{ {
sgi_plat_info.platform_id = plat_arm_sgi_get_platform_id(); sgi_plat_info.platform_id = plat_arm_sgi_get_platform_id();
sgi_plat_info.config_id = plat_arm_sgi_get_config_id(); sgi_plat_info.config_id = plat_arm_sgi_get_config_id();
sgi_plat_info.multi_chip_mode = plat_arm_sgi_get_multi_chip_mode();
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
} }
void bl31_platform_setup(void) void sgi_bl31_common_platform_setup(void)
{ {
arm_bl31_platform_setup(); arm_bl31_platform_setup();
...@@ -66,9 +106,13 @@ void bl31_platform_setup(void) ...@@ -66,9 +106,13 @@ void bl31_platform_setup(void)
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
{ {
/* For RD-E1-Edge platform only CPU ON/OFF is supported */ /*
if ((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) && * For RD-E1-Edge and RD-Daniel platforms, only CPU power ON/OFF
(sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)) { * PSCI platform callbacks are supported.
*/
if (((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
(sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)) ||
(sgi_plat_info.platform_id == RD_DANIEL_SID_VER_PART_NUM)) {
ops->cpu_standby = NULL; ops->cpu_standby = NULL;
ops->system_off = NULL; ops->system_off = NULL;
ops->system_reset = NULL; ops->system_reset = NULL;
......
plat/arm/css/sgi/sgi_image_load.c
View file @ d232ca5f
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -62,6 +62,13 @@ static int plat_sgi_append_config_node(void) ...@@ -62,6 +62,13 @@ static int plat_sgi_append_config_node(void)
return -1; return -1;
} }
platcfg = plat_arm_sgi_get_multi_chip_mode();
err = fdt_setprop_u32(fdt, nodeoffset, "multi-chip-mode", platcfg);
if (err < 0) {
ERROR("Failed to set multi-chip-mode\n");
return -1;
}
flush_dcache_range((uintptr_t)fdt, mem_params->image_info.image_size); flush_dcache_range((uintptr_t)fdt, mem_params->image_info.image_size);
return 0; return 0;
......
plat/arm/css/sgm/include/sgm_base_platform_def.h
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -86,7 +86,6 @@ ...@@ -86,7 +86,6 @@
/* MHU related constants */ /* MHU related constants */
#define PLAT_CSS_MHU_BASE 0x2b1f0000 #define PLAT_CSS_MHU_BASE 0x2b1f0000
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000
...@@ -239,4 +238,7 @@ ...@@ -239,4 +238,7 @@
/* System power domain level */ /* System power domain level */
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
/* Number of SCMI channels on the platform */
#define PLAT_ARM_SCMI_CHANNEL_COUNT U(1)
#endif /* SGM_BASE_PLATFORM_DEF_H */ #endif /* SGM_BASE_PLATFORM_DEF_H */
plat/arm/css/sgm/sgm_bl31_setup.c
View file @ d232ca5f
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -20,7 +20,7 @@ static scmi_channel_plat_info_t sgm775_scmi_plat_info = { ...@@ -20,7 +20,7 @@ static scmi_channel_plat_info_t sgm775_scmi_plat_info = {
.ring_doorbell = &mhu_ring_doorbell, .ring_doorbell = &mhu_ring_doorbell,
}; };
scmi_channel_plat_info_t *plat_css_get_scmi_info() scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
{ {
return &sgm775_scmi_plat_info; return &sgm775_scmi_plat_info;
} }
......
plat/socionext/synquacer/include/platform_def.h
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -80,7 +80,6 @@ ...@@ -80,7 +80,6 @@
#define DRAMINFO_BASE 0x2E00FFC0 #define DRAMINFO_BASE 0x2E00FFC0
#define PLAT_SQ_MHU_BASE 0x45000000 #define PLAT_SQ_MHU_BASE 0x45000000
#define PLAT_MHUV2_BASE 0xFFFFFFFF /* MHUV2 is not supported */
#define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000 #define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000
#define SCPI_CMD_GET_DRAMINFO 0x1 #define SCPI_CMD_GET_DRAMINFO 0x1
......
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