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Commit d232ca5f authored by Manish Pandey's avatar Manish Pandey Committed by TrustedFirmware Code Review
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Merge changes from topics "rddaniel", "rdn1edge_dual" into integration 

* changes:
  plat/arm: add board support for rd-daniel platform
  plat/arm/sgi: move GIC related constants to board files
  platform/arm/sgi: add multi-chip mode parameter in HW_CONFIG dts
  board/rdn1edge: add support for dual-chip configuration
  drivers/arm/scmi: allow use of multiple SCMI channels
  drivers/mhu: derive doorbell base address
  plat/arm/sgi: include AFF3 affinity in core position calculation
  plat/arm/sgi: add macros for remote chip device region
  plat/arm/sgi: add chip_id and multi_chip_mode to platform variant info
  plat/arm/sgi: move bl31_platform_setup to board file
parents 1f6b06c8 2103a73b
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drivers/arm/css/mhu/css_mhu_doorbell.c
View file @ d232ca5f
/* /*
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -20,11 +20,13 @@ void mhu_ring_doorbell(struct scmi_channel_plat_info *plat_info) ...@@ -20,11 +20,13 @@ void mhu_ring_doorbell(struct scmi_channel_plat_info *plat_info)
void mhuv2_ring_doorbell(struct scmi_channel_plat_info *plat_info) void mhuv2_ring_doorbell(struct scmi_channel_plat_info *plat_info)
{ {
uintptr_t mhuv2_base = plat_info->db_reg_addr & MHU_V2_FRAME_BASE_MASK;
/* wake receiver */ /* wake receiver */
MHU_V2_ACCESS_REQUEST(MHUV2_BASE_ADDR); MHU_V2_ACCESS_REQUEST(mhuv2_base);
/* wait for receiver to acknowledge its ready */ /* wait for receiver to acknowledge its ready */
while (MHU_V2_IS_ACCESS_READY(MHUV2_BASE_ADDR) == 0) while (MHU_V2_IS_ACCESS_READY(mhuv2_base) == 0)
; ;
MHU_RING_DOORBELL(plat_info->db_reg_addr, MHU_RING_DOORBELL(plat_info->db_reg_addr,
...@@ -32,7 +34,7 @@ void mhuv2_ring_doorbell(struct scmi_channel_plat_info *plat_info) ...@@ -32,7 +34,7 @@ void mhuv2_ring_doorbell(struct scmi_channel_plat_info *plat_info)
plat_info->db_preserve_mask); plat_info->db_preserve_mask);
/* clear the access request for the receiver */ /* clear the access request for the receiver */
MHU_V2_CLEAR_REQUEST(MHUV2_BASE_ADDR); MHU_V2_CLEAR_REQUEST(mhuv2_base);
return; return;
} }
drivers/arm/css/scp/css_pm_scmi.c
View file @ d232ca5f
/* /*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -63,16 +63,44 @@ typedef enum { ...@@ -63,16 +63,44 @@ typedef enum {
} scmi_power_state_t; } scmi_power_state_t;
/* /*
* The global handle for invoking the SCMI driver APIs after the driver * The global handles for invoking the SCMI driver APIs after the driver
* has been initialized. * has been initialized.
*/ */
static void *scmi_handle; static void *scmi_handles[PLAT_ARM_SCMI_CHANNEL_COUNT];
/* The SCMI channel global object */ /* The global SCMI channels array */
static scmi_channel_t channel; static scmi_channel_t scmi_channels[PLAT_ARM_SCMI_CHANNEL_COUNT];
/*
* Channel ID for the default SCMI channel.
* The default channel is used to issue SYSTEM level SCMI requests and is
* initialized to the channel which has the boot cpu as its resource.
*/
static uint32_t default_scmi_channel_id;
/*
* TODO: Allow use of channel specific lock instead of using a single lock for
* all the channels.
*/
ARM_SCMI_INSTANTIATE_LOCK; ARM_SCMI_INSTANTIATE_LOCK;
/*
* Function to obtain the SCMI Domain ID and SCMI Channel number from the linear
* core position. The SCMI Channel number is encoded in the upper 16 bits and
* the Domain ID is encoded in the lower 16 bits in each entry of the mapping
* array exported by the platform.
*/
static void css_scp_core_pos_to_scmi_channel(unsigned int core_pos,
unsigned int *scmi_domain_id, unsigned int *scmi_channel_id)
{
unsigned int composite_id;
composite_id = plat_css_core_pos_to_scmi_dmn_id_map[core_pos];
*scmi_channel_id = GET_SCMI_CHANNEL_ID(composite_id);
*scmi_domain_id = GET_SCMI_DOMAIN_ID(composite_id);
}
/* /*
* Helper function to suspend a CPU power domain and its parent power domains * Helper function to suspend a CPU power domain and its parent power domains
* if applicable. * if applicable.
...@@ -87,10 +115,10 @@ void css_scp_suspend(const struct psci_power_state *target_state) ...@@ -87,10 +115,10 @@ void css_scp_suspend(const struct psci_power_state *target_state)
/* Check if power down at system power domain level is requested */ /* Check if power down at system power domain level is requested */
if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) {
/* Issue SCMI command for SYSTEM_SUSPEND */ /* Issue SCMI command for SYSTEM_SUSPEND on all SCMI channels */
ret = scmi_sys_pwr_state_set(scmi_handle, ret = scmi_sys_pwr_state_set(
SCMI_SYS_PWR_FORCEFUL_REQ, scmi_handles[default_scmi_channel_id],
SCMI_SYS_PWR_SUSPEND); SCMI_SYS_PWR_FORCEFUL_REQ, SCMI_SYS_PWR_SUSPEND);
if (ret != SCMI_E_SUCCESS) { if (ret != SCMI_E_SUCCESS) {
ERROR("SCMI system power domain suspend return 0x%x unexpected\n", ERROR("SCMI system power domain suspend return 0x%x unexpected\n",
ret); ret);
...@@ -99,7 +127,7 @@ void css_scp_suspend(const struct psci_power_state *target_state) ...@@ -99,7 +127,7 @@ void css_scp_suspend(const struct psci_power_state *target_state)
return; return;
} }
#if !HW_ASSISTED_COHERENCY #if !HW_ASSISTED_COHERENCY
unsigned int lvl; unsigned int lvl, channel_id, domain_id;
uint32_t scmi_pwr_state = 0; uint32_t scmi_pwr_state = 0;
/* /*
* If we reach here, then assert that power down at system power domain * If we reach here, then assert that power down at system power domain
...@@ -127,9 +155,10 @@ void css_scp_suspend(const struct psci_power_state *target_state) ...@@ -127,9 +155,10 @@ void css_scp_suspend(const struct psci_power_state *target_state)
SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
ret = scmi_pwr_state_set(scmi_handle, css_scp_core_pos_to_scmi_channel(plat_my_core_pos(),
plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()], &domain_id, &channel_id);
scmi_pwr_state); ret = scmi_pwr_state_set(scmi_handles[channel_id],
domain_id, scmi_pwr_state);
if (ret != SCMI_E_SUCCESS) { if (ret != SCMI_E_SUCCESS) {
ERROR("SCMI set power state command return 0x%x unexpected\n", ERROR("SCMI set power state command return 0x%x unexpected\n",
...@@ -145,7 +174,7 @@ void css_scp_suspend(const struct psci_power_state *target_state) ...@@ -145,7 +174,7 @@ void css_scp_suspend(const struct psci_power_state *target_state)
*/ */
void css_scp_off(const struct psci_power_state *target_state) void css_scp_off(const struct psci_power_state *target_state)
{ {
unsigned int lvl = 0; unsigned int lvl = 0, channel_id, domain_id;
int ret; int ret;
uint32_t scmi_pwr_state = 0; uint32_t scmi_pwr_state = 0;
...@@ -168,10 +197,10 @@ void css_scp_off(const struct psci_power_state *target_state) ...@@ -168,10 +197,10 @@ void css_scp_off(const struct psci_power_state *target_state)
SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
ret = scmi_pwr_state_set(scmi_handle, css_scp_core_pos_to_scmi_channel(plat_my_core_pos(),
plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()], &domain_id, &channel_id);
scmi_pwr_state); ret = scmi_pwr_state_set(scmi_handles[channel_id],
domain_id, scmi_pwr_state);
if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) {
ERROR("SCMI set power state command return 0x%x unexpected\n", ERROR("SCMI set power state command return 0x%x unexpected\n",
ret); ret);
...@@ -185,8 +214,8 @@ void css_scp_off(const struct psci_power_state *target_state) ...@@ -185,8 +214,8 @@ void css_scp_off(const struct psci_power_state *target_state)
*/ */
void css_scp_on(u_register_t mpidr) void css_scp_on(u_register_t mpidr)
{ {
unsigned int lvl = 0; unsigned int lvl = 0, channel_id, core_pos, domain_id;
int core_pos, ret; int ret;
uint32_t scmi_pwr_state = 0; uint32_t scmi_pwr_state = 0;
for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
...@@ -196,13 +225,12 @@ void css_scp_on(u_register_t mpidr) ...@@ -196,13 +225,12 @@ void css_scp_on(u_register_t mpidr)
SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
core_pos = plat_core_pos_by_mpidr(mpidr); core_pos = plat_core_pos_by_mpidr(mpidr);
assert((core_pos >= 0) && assert(core_pos >= 0 && (core_pos < PLATFORM_CORE_COUNT));
(((unsigned int)core_pos) < PLATFORM_CORE_COUNT));
ret = scmi_pwr_state_set(scmi_handle,
plat_css_core_pos_to_scmi_dmn_id_map[core_pos],
scmi_pwr_state);
css_scp_core_pos_to_scmi_channel(core_pos, &domain_id,
&channel_id);
ret = scmi_pwr_state_set(scmi_handles[channel_id],
domain_id, scmi_pwr_state);
if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) {
ERROR("SCMI set power state command return 0x%x unexpected\n", ERROR("SCMI set power state command return 0x%x unexpected\n",
ret); ret);
...@@ -216,8 +244,9 @@ void css_scp_on(u_register_t mpidr) ...@@ -216,8 +244,9 @@ void css_scp_on(u_register_t mpidr)
*/ */
int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level) int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level)
{ {
int ret, cpu_idx; int ret;
uint32_t scmi_pwr_state = 0, lvl_state; uint32_t scmi_pwr_state = 0, lvl_state;
unsigned int channel_id, cpu_idx, domain_id;
/* We don't support get power state at the system power domain level */ /* We don't support get power state at the system power domain level */
if ((power_level > PLAT_MAX_PWR_LVL) || if ((power_level > PLAT_MAX_PWR_LVL) ||
...@@ -230,9 +259,9 @@ int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level) ...@@ -230,9 +259,9 @@ int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level)
cpu_idx = plat_core_pos_by_mpidr(mpidr); cpu_idx = plat_core_pos_by_mpidr(mpidr);
assert(cpu_idx > -1); assert(cpu_idx > -1);
ret = scmi_pwr_state_get(scmi_handle, css_scp_core_pos_to_scmi_channel(cpu_idx, &domain_id, &channel_id);
plat_css_core_pos_to_scmi_dmn_id_map[cpu_idx], ret = scmi_pwr_state_get(scmi_handles[channel_id],
&scmi_pwr_state); domain_id, &scmi_pwr_state);
if (ret != SCMI_E_SUCCESS) { if (ret != SCMI_E_SUCCESS) {
WARN("SCMI get power state command return 0x%x unexpected\n", WARN("SCMI get power state command return 0x%x unexpected\n",
...@@ -271,7 +300,7 @@ void __dead2 css_scp_system_off(int state) ...@@ -271,7 +300,7 @@ void __dead2 css_scp_system_off(int state)
* Issue SCMI command. First issue a graceful * Issue SCMI command. First issue a graceful
* request and if that fails force the request. * request and if that fails force the request.
*/ */
ret = scmi_sys_pwr_state_set(scmi_handle, ret = scmi_sys_pwr_state_set(scmi_handles[default_scmi_channel_id],
SCMI_SYS_PWR_FORCEFUL_REQ, SCMI_SYS_PWR_FORCEFUL_REQ,
state); state);
...@@ -325,17 +354,28 @@ static int scmi_ap_core_init(scmi_channel_t *ch) ...@@ -325,17 +354,28 @@ static int scmi_ap_core_init(scmi_channel_t *ch)
void __init plat_arm_pwrc_setup(void) void __init plat_arm_pwrc_setup(void)
{ {
channel.info = plat_css_get_scmi_info(); unsigned int composite_id, idx;
channel.lock = ARM_SCMI_LOCK_GET_INSTANCE;
scmi_handle = scmi_init(&channel); for (idx = 0; idx < PLAT_ARM_SCMI_CHANNEL_COUNT; idx++) {
if (scmi_handle == NULL) { INFO("Initializing driver on Channel %d\n", idx);
ERROR("SCMI Initialization failed\n");
scmi_channels[idx].info = plat_css_get_scmi_info(idx);
scmi_channels[idx].lock = ARM_SCMI_LOCK_GET_INSTANCE;
scmi_handles[idx] = scmi_init(&scmi_channels[idx]);
if (scmi_handles[idx] == NULL) {
ERROR("SCMI Initialization failed on channel %d\n", idx);
panic(); panic();
} }
if (scmi_ap_core_init(&channel) < 0) {
if (scmi_ap_core_init(&scmi_channels[idx]) < 0) {
ERROR("SCMI AP core protocol initialization failed\n"); ERROR("SCMI AP core protocol initialization failed\n");
panic(); panic();
} }
}
composite_id = plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()];
default_scmi_channel_id = GET_SCMI_CHANNEL_ID(composite_id);
} }
/****************************************************************************** /******************************************************************************
...@@ -347,6 +387,7 @@ const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops) ...@@ -347,6 +387,7 @@ const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops)
{ {
uint32_t msg_attr; uint32_t msg_attr;
int ret; int ret;
void *scmi_handle = scmi_handles[default_scmi_channel_id];
assert(scmi_handle); assert(scmi_handle);
...@@ -411,14 +452,17 @@ int css_system_reset2(int is_vendor, int reset_type, u_register_t cookie) ...@@ -411,14 +452,17 @@ int css_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
#if PROGRAMMABLE_RESET_ADDRESS #if PROGRAMMABLE_RESET_ADDRESS
void plat_arm_program_trusted_mailbox(uintptr_t address) void plat_arm_program_trusted_mailbox(uintptr_t address)
{ {
int ret; int ret, i;
assert(scmi_handle); for (i = 0; i < PLAT_ARM_SCMI_CHANNEL_COUNT; i++) {
ret = scmi_ap_core_set_reset_addr(scmi_handle, address, assert(scmi_handles[i]);
ret = scmi_ap_core_set_reset_addr(scmi_handles[i], address,
SCMI_AP_CORE_LOCK_ATTR); SCMI_AP_CORE_LOCK_ATTR);
if (ret != SCMI_E_SUCCESS) { if (ret != SCMI_E_SUCCESS) {
ERROR("CSS: Failed to program reset address: %d\n", ret); ERROR("CSS: Failed to program reset address: %d\n", ret);
panic(); panic();
} }
}
} }
#endif #endif
include/drivers/arm/css/css_mhu_doorbell.h
View file @ d232ca5f
/* /*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -11,13 +11,13 @@ ...@@ -11,13 +11,13 @@
#include <lib/mmio.h> #include <lib/mmio.h>
/* MHUv2 Base Address */ /* MHUv2 Frame Base Mask */
#define MHUV2_BASE_ADDR PLAT_MHUV2_BASE #define MHU_V2_FRAME_BASE_MASK UL(~0xFFF)
/* MHUv2 Control Registers Offsets */ /* MHUv2 Control Registers Offsets */
#define MHU_V2_MSG_NO_CAP_OFFSET 0xF80 #define MHU_V2_MSG_NO_CAP_OFFSET UL(0xF80)
#define MHU_V2_ACCESS_REQ_OFFSET 0xF88 #define MHU_V2_ACCESS_REQ_OFFSET UL(0xF88)
#define MHU_V2_ACCESS_READY_OFFSET 0xF8C #define MHU_V2_ACCESS_READY_OFFSET UL(0xF8C)
#define SENDER_REG_STAT(_channel) (0x20 * (_channel)) #define SENDER_REG_STAT(_channel) (0x20 * (_channel))
#define SENDER_REG_SET(_channel) ((0x20 * (_channel)) + 0xC) #define SENDER_REG_SET(_channel) ((0x20 * (_channel)) + 0xC)
......
include/drivers/arm/css/scmi.h
View file @ d232ca5f
/* /*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -162,7 +162,7 @@ int scmi_ap_core_set_reset_addr(void *p, uint64_t reset_addr, uint32_t attr); ...@@ -162,7 +162,7 @@ int scmi_ap_core_set_reset_addr(void *p, uint64_t reset_addr, uint32_t attr);
int scmi_ap_core_get_reset_addr(void *p, uint64_t *reset_addr, uint32_t *attr); int scmi_ap_core_get_reset_addr(void *p, uint64_t *reset_addr, uint32_t *attr);
/* API to get the platform specific SCMI channel information. */ /* API to get the platform specific SCMI channel information. */
scmi_channel_plat_info_t *plat_css_get_scmi_info(void); scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id);
/* API to override default PSCI callbacks for platforms that support SCMI. */ /* API to override default PSCI callbacks for platforms that support SCMI. */
const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops); const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops);
......
include/plat/arm/css/common/css_def.h
View file @ d232ca5f
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -29,6 +29,10 @@ ...@@ -29,6 +29,10 @@
#define SID_REG_BASE 0x2a4a0000 #define SID_REG_BASE 0x2a4a0000
#define SID_SYSTEM_ID_OFFSET 0x40 #define SID_SYSTEM_ID_OFFSET 0x40
#define SID_SYSTEM_CFG_OFFSET 0x70 #define SID_SYSTEM_CFG_OFFSET 0x70
#define SID_NODE_ID_OFFSET 0x60
#define SID_CHIP_ID_MASK 0xFF
#define SID_MULTI_CHIP_MODE_MASK 0x100
#define SID_MULTI_CHIP_MODE_SHIFT 8
/* The slave_bootsecure controls access to GPU, DMC and CS. */ /* The slave_bootsecure controls access to GPU, DMC and CS. */
#define CSS_NIC400_SLAVE_BOOTSECURE 8 #define CSS_NIC400_SLAVE_BOOTSECURE 8
......
include/plat/arm/css/common/css_pm.h
View file @ d232ca5f
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -44,4 +44,15 @@ int css_node_hw_state(u_register_t mpidr, unsigned int power_level); ...@@ -44,4 +44,15 @@ int css_node_hw_state(u_register_t mpidr, unsigned int power_level);
*/ */
extern const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[]; extern const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[];
#define SCMI_DOMAIN_ID_MASK U(0xFFFF)
#define SCMI_CHANNEL_ID_MASK U(0xFFFF)
#define SCMI_CHANNEL_ID_SHIFT U(16)
#define SET_SCMI_CHANNEL_ID(n) (((n) & SCMI_CHANNEL_ID_MASK) << \
SCMI_CHANNEL_ID_SHIFT)
#define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK)
#define GET_SCMI_CHANNEL_ID(n) (((n) >> SCMI_CHANNEL_ID_SHIFT) & \
SCMI_CHANNEL_ID_MASK)
#define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK)
#endif /* CSS_PM_H */ #endif /* CSS_PM_H */
plat/arm/board/juno/include/platform_def.h
View file @ d232ca5f
/* /*
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -224,7 +224,6 @@ ...@@ -224,7 +224,6 @@
/* MHU related constants */ /* MHU related constants */
#define PLAT_CSS_MHU_BASE UL(0x2b1f0000) #define PLAT_CSS_MHU_BASE UL(0x2b1f0000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
/* /*
* Base address of the first memory region used for communication between AP * Base address of the first memory region used for communication between AP
...@@ -301,4 +300,7 @@ ...@@ -301,4 +300,7 @@
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#endif #endif
/* Number of SCMI channels on the platform */
#define PLAT_ARM_SCMI_CHANNEL_COUNT U(1)
#endif /* PLATFORM_DEF_H */ #endif /* PLATFORM_DEF_H */
plat/arm/board/juno/juno_topology.c
View file @ d232ca5f
/* /*
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -20,7 +20,7 @@ static scmi_channel_plat_info_t juno_scmi_plat_info = { ...@@ -20,7 +20,7 @@ static scmi_channel_plat_info_t juno_scmi_plat_info = {
.ring_doorbell = &mhu_ring_doorbell, .ring_doorbell = &mhu_ring_doorbell,
}; };
scmi_channel_plat_info_t *plat_css_get_scmi_info(void) scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
{ {
return &juno_scmi_plat_info; return &juno_scmi_plat_info;
} }
......
plat/arm/board/n1sdp/include/platform_def.h
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -90,7 +90,6 @@ ...@@ -90,7 +90,6 @@
#define PLAT_ARM_NSTIMER_FRAME_ID 0 #define PLAT_ARM_NSTIMER_FRAME_ID 0
#define PLAT_CSS_MHU_BASE 0x45000000 #define PLAT_CSS_MHU_BASE 0x45000000
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
#define PLAT_MAX_PWR_LVL 2 #define PLAT_MAX_PWR_LVL 2
#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
...@@ -144,4 +143,7 @@ ...@@ -144,4 +143,7 @@
#define SBSA_SECURE_WDOG_BASE UL(0x2A480000) #define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
#define SBSA_SECURE_WDOG_TIMEOUT UL(100) #define SBSA_SECURE_WDOG_TIMEOUT UL(100)
/* Number of SCMI channels on the platform */
#define PLAT_ARM_SCMI_CHANNEL_COUNT U(1)
#endif /* PLATFORM_DEF_H */ #endif /* PLATFORM_DEF_H */
plat/arm/board/n1sdp/n1sdp_bl31_setup.c
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -74,7 +74,7 @@ static uintptr_t n1sdp_multichip_gicr_frames[3] = { ...@@ -74,7 +74,7 @@ static uintptr_t n1sdp_multichip_gicr_frames[3] = {
0 0
}; };
scmi_channel_plat_info_t *plat_css_get_scmi_info() scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
{ {
return &n1sdp_scmi_plat_info; return &n1sdp_scmi_plat_info;
} }
......
plat/arm/board/rddaniel/fdts/rddaniel_nt_fw_config.dts 0 → 100644
View file @ d232ca5f
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
/* compatible string */
compatible = "arm,rd-daniel";
/*
* Place holder for system-id node with default values. The
* value of platform-id and config-id will be set to the
* correct values during the BL2 stage of boot.
*/
system-id {
platform-id = <0x0>;
config-id = <0x0>;
multi-chip-mode = <0x0>;
};
};
plat/arm/board/rddaniel/fdts/rddaniel_tb_fw_config.dts 0 → 100644
View file @ d232ca5f
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
/* Platform Config */
compatible = "arm,tb_fw";
nt_fw_config_addr = <0x0 0xFEF00000>;
nt_fw_config_max_size = <0x0100000>;
/*
* The following two entries are placeholders for Mbed TLS
* heap information. The default values don't matter since
* they will be overwritten by BL1.
* In case of having shared Mbed TLS heap between BL1 and BL2,
* BL1 will populate these two properties with the respective
* info about the shared heap. This info will be available for
* BL2 in order to locate and re-use the heap.
*/
mbedtls_heap_addr = <0x0 0x0>;
mbedtls_heap_size = <0x0>;
};
plat/arm/board/rddaniel/include/platform_def.h 0 → 100644
View file @ d232ca5f
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
#include <sgi_base_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(16)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
#define CSS_SGI_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#endif
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x30140000)
#endif /* PLATFORM_DEF_H */
plat/arm/board/rddaniel/platform.mk 0 → 100644
View file @ d232ca5f
# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
include plat/arm/css/sgi/sgi-common.mk
RDDANIEL_BASE = plat/arm/board/rddaniel
PLAT_INCLUDES += -I${RDDANIEL_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_zeus.S
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDDANIEL_BASE}/rddaniel_err.c
BL2_SOURCES += ${RDDANIEL_BASE}/rddaniel_plat.c \
${RDDANIEL_BASE}/rddaniel_security.c \
${RDDANIEL_BASE}/rddaniel_err.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
BL31_SOURCES += ${SGI_CPU_SOURCES} \
${RDDANIEL_BASE}/rddaniel_plat.c \
${RDDANIEL_BASE}/rddaniel_topology.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
# Add the FDT_SOURCES and options for Dynamic Config
FDT_SOURCES += ${RDDANIEL_BASE}/fdts/${PLAT}_tb_fw_config.dts
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
FDT_SOURCES += ${RDDANIEL_BASE}/fdts/${PLAT}_nt_fw_config.dts
NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
override CTX_INCLUDE_AARCH32_REGS := 0
plat/arm/board/rddaniel/rddaniel_err.c 0 → 100644
View file @ d232ca5f
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
/*
* rddaniel error handler
*/
void __dead2 plat_arm_error_handler(int err)
{
while (1) {
wfi();
}
}
plat/arm/board/rddaniel/rddaniel_plat.c 0 → 100644
View file @ d232ca5f
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/common/platform.h>
#include <sgi_plat.h>
unsigned int plat_arm_sgi_get_platform_id(void)
{
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
& SID_SYSTEM_ID_PART_NUM_MASK;
}
unsigned int plat_arm_sgi_get_config_id(void)
{
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
}
unsigned int plat_arm_sgi_get_multi_chip_mode(void)
{
return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
}
void bl31_platform_setup(void)
{
sgi_bl31_common_platform_setup();
}
plat/arm/board/rddaniel/rddaniel_security.c 0 → 100644
View file @ d232ca5f
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
}
plat/arm/board/rddaniel/rddaniel_topology.c 0 → 100644
View file @ d232ca5f
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
#include <plat/arm/css/common/css_pm.h>
/******************************************************************************
* The power domain tree descriptor.
******************************************************************************/
const unsigned char rd_daniel_pd_tree_desc[] = {
PLAT_ARM_CLUSTER_COUNT,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER
};
/*******************************************************************************
* This function returns the topology tree information.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
return rd_daniel_pd_tree_desc;
}
/*******************************************************************************
* The array mapping platform core position (implemented by plat_my_core_pos())
* to the SCMI power domain ID implemented by SCP.
******************************************************************************/
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF))
};
plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, Arm Limited. All rights reserved. * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
system-id { system-id {
platform-id = <0x0>; platform-id = <0x0>;
config-id = <0x0>; config-id = <0x0>;
multi-chip-mode = <0x0>;
}; };
}; };
plat/arm/board/rde1edge/include/platform_def.h
View file @ d232ca5f
/* /*
* Copyright (c) 2018-2019, Arm Limited. All rights reserved. * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -16,7 +16,6 @@ ...@@ -16,7 +16,6 @@
#define CSS_SGI_MAX_PE_PER_CPU U(2) #define CSS_SGI_MAX_PE_PER_CPU U(2)
#define PLAT_CSS_MHU_BASE UL(0x45400000) #define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
/* Base address of DMC-620 instances */ /* Base address of DMC-620 instances */
#define RDE1EDGE_DMC620_BASE0 UL(0x4e000000) #define RDE1EDGE_DMC620_BASE0 UL(0x4e000000)
...@@ -37,4 +36,9 @@ ...@@ -37,4 +36,9 @@
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#endif #endif
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x300C0000)
#endif /* PLATFORM_DEF_H */ #endif /* PLATFORM_DEF_H */
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