From d27c880a369aa84f9b6fcf11d6024fc2f4ffc602 Mon Sep 17 00:00:00 2001
From: Hongbo Zhang <hongbo.zhang@linaro.org>
Date: Thu, 19 Apr 2018 14:42:23 +0800
Subject: [PATCH] plat/qemu: add gicv3 support for qemu
This patch adds gicv3 support for qemu, in order not to break any legacy
use case, gicv2 is still set by default, gicv3 can be selected by
compiling parameter QEMU_USE_GIC_DRIVER=QEMU_GICV3.
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: Ic63f38abf16ed3c36aa60e80d50103cf05cf797b
---
plat/qemu/include/platform_def.h | 4 +--
plat/qemu/platform.mk | 19 ++++++++++++-
plat/qemu/qemu_gicv3.c | 46 ++++++++++++++++++++++++++++++++
3 files changed, 66 insertions(+), 3 deletions(-)
create mode 100644 plat/qemu/qemu_gicv3.c
diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h
index 21492b40e..d7f77cc78 100644
--- a/plat/qemu/include/platform_def.h
+++ b/plat/qemu/include/platform_def.h
@@ -197,7 +197,7 @@
#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE
#define DEVICE0_BASE 0x08000000
-#define DEVICE0_SIZE 0x00021000
+#define DEVICE0_SIZE 0x01000000
#define DEVICE1_BASE 0x09000000
#define DEVICE1_SIZE 0x00041000
@@ -207,7 +207,7 @@
#define GICD_BASE 0x8000000
#define GICC_BASE 0x8010000
-#define GICR_BASE 0
+#define GICR_BASE 0x80A0000
#define QEMU_IRQ_SEC_SGI_0 8
diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index 2619587a3..6b9749c79 100644
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -4,6 +4,9 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+# Use the GICv2 driver on QEMU by default
+QEMU_USE_GIC_DRIVER := QEMU_GICV2
+
ifeq (${ARM_ARCH_MAJOR},7)
# ARMv7 Qemu support in trusted firmware expects the Cortex-A15 model.
# Qemu Cortex-A15 model does not implement the virtualization extension.
@@ -120,12 +123,26 @@ ifeq ($(add-lib-optee),yes)
BL2_SOURCES += lib/optee/optee_utils.c
endif
-QEMU_GIC_SOURCES := drivers/arm/gic/v2/gicv2_helpers.c \
+QEMU_GICV2_SOURCES := drivers/arm/gic/v2/gicv2_helpers.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/common/gic_common.c \
plat/common/plat_gicv2.c \
plat/qemu/qemu_gicv2.c
+QEMU_GICV3_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicv3_main.c \
+ drivers/arm/gic/common/gic_common.c \
+ plat/common/plat_gicv3.c \
+ plat/qemu/qemu_gicv3.c
+
+ifeq (${QEMU_USE_GIC_DRIVER}, QEMU_GICV2)
+QEMU_GIC_SOURCES := ${QEMU_GICV2_SOURCES}
+else ifeq (${QEMU_USE_GIC_DRIVER}, QEMU_GICV3)
+QEMU_GIC_SOURCES := ${QEMU_GICV3_SOURCES}
+else
+$(error "Incorrect GIC driver chosen for QEMU platform")
+endif
+
ifeq (${ARM_ARCH_MAJOR},8)
BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
diff --git a/plat/qemu/qemu_gicv3.c b/plat/qemu/qemu_gicv3.c
new file mode 100644
index 000000000..28572c5ef
--- /dev/null
+++ b/plat/qemu/qemu_gicv3.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gicv3.h>
+#include <drivers/arm/gic_common.h>
+#include <platform_def.h>
+#include <plat/common/platform.h>
+
+static const interrupt_prop_t qemu_interrupt_props[] = {
+ PLATFORM_G1S_PROPS(INTR_GROUP1S),
+ PLATFORM_G0_PROPS(INTR_GROUP0)
+};
+
+static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT];
+
+static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr)
+{
+ return (unsigned int)plat_core_pos_by_mpidr(mpidr);
+}
+
+static const gicv3_driver_data_t qemu_gicv3_driver_data = {
+ .gicd_base = GICD_BASE,
+ .gicr_base = GICR_BASE,
+ .interrupt_props = qemu_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props),
+ .rdistif_num = PLATFORM_CORE_COUNT,
+ .rdistif_base_addrs = qemu_rdistif_base_addrs,
+ .mpidr_to_core_pos = qemu_mpidr_to_core_pos
+};
+
+void plat_qemu_gic_init(void)
+{
+ gicv3_driver_init(&qemu_gicv3_driver_data);
+ gicv3_distif_init();
+ gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+void qemu_pwr_gic_on_finish(void)
+{
+ gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
--
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