Skip to content
GitLab
Menu
Projects
Groups
Snippets
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Sign in / Register
Toggle navigation
Menu
Open sidebar
adam.huang
Arm Trusted Firmware
Commits
d402f3dc
Commit
d402f3dc
authored
Sep 23, 2014
by
achingupta
Browse files
Merge pull request #213 from soby-mathew/sm/crash_reporting_fix
Remove BSS section access by 'plat_print_gic' during crash reporting
parents
bcdbf945
6ab03912
Changes
2
Show whitespace changes
Inline
Side-by-side
plat/fvp/include/plat_macros.S
View file @
d402f3dc
...
...
@@ -33,8 +33,8 @@
#include "../fvp_def.h"
.
section
.
rodata.
gic_reg_name
,
"aS"
gic_regs
:
.
asciz
"gic_hppir"
,
"gic_ahppir"
,
"gic_ctlr"
,
""
gic
c
_regs
:
.
asciz
"gic
c
_hppir"
,
"gic
c
_ahppir"
,
"gic
c
_ctlr"
,
""
gicd_pend_reg
:
.
asciz
"gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
newline
:
...
...
@@ -46,19 +46,33 @@ spacer:
*
The
below
macro
prints
out
relevant
GIC
*
registers
whenever
an
unhandled
exception
is
*
taken
in
BL3
-
1
.
*
Clobbers
:
x0
-
x10
,
x16
,
sp
*
Clobbers
:
x0
-
x10
,
x16
,
x17
,
sp
*
---------------------------------------------
*/
.
macro
plat_print_gic_regs
adr
x0
,
plat_config
ldr
w16
,
[
x0
,
#
CONFIG_GICC_BASE_OFFSET
]
cbz
x16
,
exit_print_gic_regs
/
*
gic
base
address
is
now
in
x16
*/
adr
x6
,
gic_regs
/*
Load
the
gic
reg
list
to
x6
*/
/
*
Load
the
gic
regs
to
gp
regs
used
by
str_in_crash_buf_print
*/
ldr
w8
,
[
x16
,
#
GICC_HPPIR
]
ldr
w9
,
[
x16
,
#
GICC_AHPPIR
]
ldr
w10
,
[
x16
,
#
GICC_CTLR
]
mov_imm
x0
,
(
VE_SYSREGS_BASE
+
V2M_SYS_ID
)
ldr
w16
,
[
x0
]
/
*
Extract
BLD
(
12
th
-
15
th
bits
)
from
the
SYS_ID
*/
ubfx
x16
,
x16
,
#
SYS_ID_BLD_SHIFT
,
#
4
/
*
Check
if
VE
mmap
*/
cmp
w16
,
#
BLD_GIC_VE_MMAP
b.eq
use_ve_mmap
/
*
Check
if
Cortex
-
A53
/
A57
mmap
*/
cmp
w16
,
#
BLD_GIC_A53A57_MMAP
b.ne
exit_print_gic_regs
mov_imm
x17
,
BASE_GICC_BASE
mov_imm
x16
,
BASE_GICD_BASE
b
print_gicc_regs
use_ve_mmap
:
mov_imm
x17
,
VE_GICC_BASE
mov_imm
x16
,
VE_GICD_BASE
print_gicc_regs
:
/
*
gicc
base
address
is
now
in
x17
*/
adr
x6
,
gicc_regs
/*
Load
the
gicc
reg
list
to
x6
*/
/
*
Load
the
gicc
regs
to
gp
regs
used
by
str_in_crash_buf_print
*/
ldr
w8
,
[
x17
,
#
GICC_HPPIR
]
ldr
w9
,
[
x17
,
#
GICC_AHPPIR
]
ldr
w10
,
[
x17
,
#
GICC_CTLR
]
/
*
Store
to
the
crash
buf
and
print
to
console
*/
bl
str_in_crash_buf_print
...
...
plat/juno/include/plat_macros.S
View file @
d402f3dc
...
...
@@ -34,8 +34,8 @@
#include "../juno_def.h"
.
section
.
rodata.
gic_reg_name
,
"aS"
gic_regs
:
.
asciz
"gic_hppir"
,
"gic_ahppir"
,
"gic_ctlr"
,
""
gic
c
_regs
:
.
asciz
"gic
c
_hppir"
,
"gic
c
_ahppir"
,
"gic
c
_ctlr"
,
""
gicd_pend_reg
:
.
asciz
"gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
newline
:
...
...
@@ -52,13 +52,14 @@ spacer:
*
---------------------------------------------
*/
.
macro
plat_print_gic_regs
ldr
x16
,
=
GICC_BASE
/
*
Load
the
gic
reg
list
to
x6
*/
adr
x6
,
gic_regs
/
*
Load
the
gic
regs
to
gp
regs
used
by
str_in_crash_buf_print
*/
ldr
w8
,
[
x16
,
#
GICC_HPPIR
]
ldr
w9
,
[
x16
,
#
GICC_AHPPIR
]
ldr
w10
,
[
x16
,
#
GICC_CTLR
]
mov_imm
x16
,
GICD_BASE
mov_imm
x17
,
GICC_BASE
/
*
Load
the
gicc
reg
list
to
x6
*/
adr
x6
,
gicc_regs
/
*
Load
the
gicc
regs
to
gp
regs
used
by
str_in_crash_buf_print
*/
ldr
w8
,
[
x17
,
#
GICC_HPPIR
]
ldr
w9
,
[
x17
,
#
GICC_AHPPIR
]
ldr
w10
,
[
x17
,
#
GICC_CTLR
]
/
*
Store
to
the
crash
buf
and
print
to
console
*/
bl
str_in_crash_buf_print
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment