diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst index 97e1fa86a616d1c6aad306a1bbdbcd9da8197a14..fd23b251acb1572bd0563f66f575364c3d8b7b54 100644 --- a/docs/about/maintainers.rst +++ b/docs/about/maintainers.rst @@ -399,6 +399,7 @@ Arm Rich IoT Platform ports :|G|: `vishnu-banavath`_ :|F|: plat/arm/board/corstone700 :|F|: plat/arm/board/a5ds +:|F|: plat/arm/board/diphda Arm Reference Design platform ports ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/plat/arm/diphda/index.rst b/docs/plat/arm/diphda/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..27afda43f50ab20fe4a7796cbaa733a94d6a80c0 --- /dev/null +++ b/docs/plat/arm/diphda/index.rst @@ -0,0 +1,61 @@ +Diphda Platform +========================== + +Some of the features of the Diphda platform referenced in TF-A include: + +- Cortex-A35 application processor (64-bit mode) +- Secure Enclave +- GIC-400 +- Trusted Board Boot + +Boot Sequence +------------- + +The board boot relies on CoT (chain of trust). The trusted-firmware-a +BL2 is extracted from the FIP and verified by the Secure Enclave +processor. BL2 verification relies on the signature area at the +beginning of the BL2 image. This area is needed by the SecureEnclave +bootloader. + +Then, the application processor is released from reset and starts by +executing BL2. + +BL2 performs the actions described in the trusted-firmware-a TBB design +document. + +Build Procedure (TF-A only) +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Obtain AArch64 ELF bare-metal target `toolchain `_. + Set the CROSS_COMPILE environment variable to point to the toolchain folder. + +- Build TF-A: + + .. code:: shell + + make LD=aarch64-none-elf-ld \ + CC=aarch64-none-elf-gcc \ + V=1 \ + BUILD_BASE= \ + PLAT=diphda \ + SPD=spmd \ + SPMD_SPM_AT_SEL2=0 \ + DEBUG=1 \ + MBEDTLS_DIR=mbedtls \ + OPENSSL_DIR= \ + RUNTIME_SYSROOT= \ + ARCH=aarch64 \ + TARGET_PLATFORM= \ + ENABLE_PIE=1 \ + BL2_AT_EL3=1 \ + CREATE_KEYS=1 \ + GENERATE_COT=1 \ + TRUSTED_BOARD_BOOT=1 \ + COT=tbbr \ + ARM_ROTPK_LOCATION=devel_rsa \ + ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ + BL32= \ + BL33= \ + bl2 + +*Copyright (c) 2021, Arm Limited. All rights reserved.* diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst index f72992b801a83e7e344b07df3796ebfca44655c1..f50dab52eb7032ffcb359138fe047c8a77b7bf5f 100644 --- a/docs/plat/arm/index.rst +++ b/docs/plat/arm/index.rst @@ -12,6 +12,7 @@ Arm Development Platforms arm_fpga/index arm-build-options morello/index + diphda/index This chapter holds documentation related to Arm's development platforms, including both software models (FVPs) and hardware development boards @@ -19,4 +20,4 @@ such as Juno. -------------- -*Copyright (c) 2019, Arm Limited. All rights reserved.* +*Copyright (c) 2021, Arm Limited. All rights reserved.* diff --git a/plat/arm/board/common/rotpk/arm_dev_rotpk.S b/plat/arm/board/common/rotpk/arm_dev_rotpk.S index 80f2192e4dc305cc070865ac2b7bfb8415d51af3..38f91fe5f841b07c6e1421fed81c30111d273233 100644 --- a/plat/arm/board/common/rotpk/arm_dev_rotpk.S +++ b/plat/arm/board/common/rotpk/arm_dev_rotpk.S @@ -1,10 +1,17 @@ /* - * Copyright (c) 2020, ARM Limited. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +/* diphda platform provides custom values for the macros defined in + * arm_def.h , so only platform_def.h needs to be included + */ +#if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA) #include "plat/arm/common/arm_def.h" +#else +#include +#endif .global arm_rotpk_header .global arm_rotpk_header_end diff --git a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c b/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c new file mode 100644 index 0000000000000000000000000000000000000000..916c868d2143669821797b36e5518b2148c1d535 --- /dev/null +++ b/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +/******************************************************************************* + * Following descriptor provides BL image/ep information that gets used + * by BL2 to load the images and also subset of this information is + * passed to next BL image. The image loading sequence is managed by + * populating the images in required loading order. The image execution + * sequence is managed by populating the `next_handoff_image_id` with + * the next executable image id. + ******************************************************************************/ +static bl_mem_params_node_t bl2_mem_params_descs[] = { + + /* Fill BL31 related information */ + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), + .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + + .next_handoff_image_id = BL32_IMAGE_ID, + }, + + /* Fill BL32 related information */ + { + .image_id = BL32_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, + .ep_info.args.arg0 = DIPHDA_TOS_FW_CONFIG_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + + .next_handoff_image_id = BL33_IMAGE_ID, + }, + + /* Fill TOS_FW_CONFIG related information */ + { + .image_id = TOS_FW_CONFIG_ID, + .image_info.image_base = DIPHDA_TOS_FW_CONFIG_BASE, + .image_info.image_max_size = DIPHDA_TOS_FW_CONFIG_LIMIT - \ + DIPHDA_TOS_FW_CONFIG_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + + /* Fill BL33 related information */ + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), + .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, + .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE + - PLAT_ARM_NS_IMAGE_BASE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +}; + +REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/arm/board/diphda/common/diphda_err.c b/plat/arm/board/diphda/common/diphda_err.c new file mode 100644 index 0000000000000000000000000000000000000000..89a3b8249c1a57ea63b56d16471a9eb5165a43c3 --- /dev/null +++ b/plat/arm/board/diphda/common/diphda_err.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/* + * diphda error handler + */ +void __dead2 plat_arm_error_handler(int err) +{ + while (1) { + wfi(); + } +} diff --git a/plat/arm/board/diphda/common/diphda_helpers.S b/plat/arm/board/diphda/common/diphda_helpers.S new file mode 100644 index 0000000000000000000000000000000000000000..c9d2a88de9cdaa644e31ad67b8eb69f3b19356e0 --- /dev/null +++ b/plat/arm/board/diphda/common/diphda_helpers.S @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + .globl plat_arm_calc_core_pos + + /* -------------------------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * For AArch32, cold-booting secondary CPUs is not yet + * implemented and they panic. + * -------------------------------------------------------------------- + */ +func plat_secondary_cold_boot_setup +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * unsigned long plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and warm + * boot. On diphda, this information can be queried from the power + * controller. The Power Control SYS Status Register (PSYSR) indicates + * the wake-up reason for the CPU. + * + * For a cold boot, return 0. + * For a warm boot, Not yet supported. + * + * TODO: PSYSR is a common register and should be + * accessed using locks. Since it is not possible + * to use locks immediately after a cold reset + * we are relying on the fact that after a cold + * reset all cpus will read the same WK field + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* TODO support warm boot */ + /* Cold reset */ + mov x0, #0 + ret +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current CPU is the primary + * CPU. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + mov_imm x1, MPIDR_AFFINITY_MASK + and x0, x0, x1 + cmp x0, #DIPHDA_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary diff --git a/plat/arm/board/diphda/common/diphda_plat.c b/plat/arm/board/diphda/common/diphda_plat.c new file mode 100644 index 0000000000000000000000000000000000000000..28d15a59e618dae7781100d818c0720b141788a5 --- /dev/null +++ b/plat/arm/board/diphda/common/diphda_plat.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include + +/* + * Table of regions to map using the MMU. + * Replace or extend the below regions as required + */ + +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + ARM_MAP_NS_SHARED_RAM, + ARM_MAP_NS_DRAM1, + DIPHDA_MAP_DEVICE, + DIPHDA_EXTERNAL_FLASH, + {0} +}; + +/* diphda only has one always-on power domain and there + * is no power control present + */ +void __init plat_arm_pwrc_setup(void) +{ +} + +unsigned int plat_get_syscnt_freq2(void) +{ + /* Returning the Generic Timer Frequency */ + return SYS_COUNTER_FREQ_IN_TICKS; +} + + +/* + * Helper function to initialize ARM interconnect driver. + */ +void plat_arm_interconnect_init(void) +{ +} + +/* + * Helper function to place current master into coherency + */ +void plat_arm_interconnect_enter_coherency(void) +{ +} + +/* + * Helper function to remove current master from coherency + */ +void plat_arm_interconnect_exit_coherency(void) +{ +} + +/* + * This function is invoked during Mbed TLS library initialisation to get a heap + * The function simply returns the default allocated heap. + */ + +#if TRUSTED_BOARD_BOOT +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + assert(heap_addr != NULL); + assert(heap_size != NULL); + + return arm_get_mbedtls_heap(heap_addr, heap_size); +} +#endif diff --git a/plat/arm/board/diphda/common/diphda_pm.c b/plat/arm/board/diphda/common/diphda_pm.c new file mode 100644 index 0000000000000000000000000000000000000000..12b322e27110a631c26d86a6cfda1c66f5e89b1b --- /dev/null +++ b/plat/arm/board/diphda/common/diphda_pm.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +/******************************************************************************* + * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard + * platform layer will take care of registering the handlers with PSCI. + ******************************************************************************/ +plat_psci_ops_t plat_arm_psci_pm_ops = { + /* dummy struct */ + .validate_ns_entrypoint = NULL +}; + +const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) +{ + return ops; +} diff --git a/plat/arm/board/diphda/common/diphda_security.c b/plat/arm/board/diphda/common/diphda_security.c new file mode 100644 index 0000000000000000000000000000000000000000..bf172afca0f2e5b9767d54bfca3e6f1004c3a129 --- /dev/null +++ b/plat/arm/board/diphda/common/diphda_security.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * We assume that all security programming is done by the primary core. + */ +void plat_arm_security_setup(void) +{ + /* + * If the platform had additional peripheral specific security + * configurations, those would be configured here. + */ +} diff --git a/plat/arm/board/diphda/common/diphda_stack_protector.c b/plat/arm/board/diphda/common/diphda_stack_protector.c new file mode 100644 index 0000000000000000000000000000000000000000..6228b63f2cb2cc59c7a33399e464e3e7252e10d3 --- /dev/null +++ b/plat/arm/board/diphda/common/diphda_stack_protector.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +static uint32_t plat_generate_random_number(void) +{ + uintptr_t return_addr = (uintptr_t)__builtin_return_address(0U); + uintptr_t frame_addr = (uintptr_t)__builtin_frame_address(0U); + uint64_t cntpct = read_cntpct_el0(); + + /* Generate 32-bit pattern: saving the 2 least significant bytes + * in random_lo and random_hi + */ + uint16_t random_lo = (uint16_t)( + (((uint64_t)return_addr) << 13) ^ frame_addr ^ cntpct + ); + + uint16_t random_hi = (uint16_t)( + (((uint64_t)frame_addr) << 15) ^ return_addr ^ cntpct + ); + + return (((uint32_t)random_hi) << 16) | random_lo; +} + +u_register_t plat_get_stack_protector_canary(void) +{ + return plat_generate_random_number(); /* a 32-bit pattern returned */ +} diff --git a/plat/arm/board/diphda/common/diphda_topology.c b/plat/arm/board/diphda/common/diphda_topology.c new file mode 100644 index 0000000000000000000000000000000000000000..9dfd05d0910abcafc5c474bafcbb977a93389281 --- /dev/null +++ b/plat/arm/board/diphda/common/diphda_topology.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +/* The diphda power domain tree descriptor */ +static unsigned char diphda_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT + + 2]; +/******************************************************************************* + * This function dynamically constructs the topology according to + * CLUSTER_COUNT and returns it. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + int i; + + /* + * The highest level is the system level. The next level is constituted + * by clusters and then cores in clusters. + */ + diphda_power_domain_tree_desc[0] = 1; + diphda_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT; + + for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++) + diphda_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT; + + return diphda_power_domain_tree_desc; +} + +/****************************************************************************** + * This function implements a part of the critical interface between the PSCI + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is + * returned in case the MPIDR is invalid. + *****************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + return plat_arm_calc_core_pos(mpidr); +} diff --git a/plat/arm/board/diphda/common/diphda_trusted_boot.c b/plat/arm/board/diphda/common/diphda_trusted_boot.c new file mode 100644 index 0000000000000000000000000000000000000000..ddb41faa6b9c61af0ebae665b447d946bb045707 --- /dev/null +++ b/plat/arm/board/diphda/common/diphda_trusted_boot.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/* + * Return the ROTPK hash in the following ASN.1 structure in DER format: + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + * + * The function returns 0 on success. Any other value is treated as error by the + * Trusted Board Boot. The function also reports extra information related + * to the ROTPK in the flags parameter: ROTPK_IS_HASH, ROTPK_NOT_DEPLOYED. + * + * Refer to the TF-A porting-guide document for more details. + */ +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + return arm_get_rotpk_info(cookie, key_ptr, key_len, flags); +} + +/* + * STUB overriding the non-volatile counter reading. + * NV counters are not implemented at this stage of development. + * Return: 0 = success + */ +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + *nv_ctr = DIPHDA_FW_NVCTR_VAL; + return 0; +} + +/* + * STUB overriding the non-volatile counter updating. + * NV counters are not implemented at this stage of development. + * Return: 0 = success + */ +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + return 0; +} diff --git a/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts b/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts new file mode 100644 index 0000000000000000000000000000000000000000..def04cde134490cd7c86d13e0edd59d6d87e5b31 --- /dev/null +++ b/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/dts-v1/; + +/ { + compatible = "arm,ffa-core-manifest-1.0"; + #address-cells = <2>; + #size-cells = <1>; + + /* + * BL32 image details needed by SPMC + * + * Note: + * binary_size: size of BL32 + TOS_FW_CONFIG + */ + + attribute { + spmc_id = <0x8000>; + maj_ver = <0x1>; + min_ver = <0x0>; + exec_state = <0x0>; + load_address = <0x0 0x2002000>; + entrypoint = <0x0 0x2002000>; + binary_size = <0xae000>; + }; + +}; diff --git a/plat/arm/board/diphda/common/include/platform_def.h b/plat/arm/board/diphda/common/include/platform_def.h new file mode 100644 index 0000000000000000000000000000000000000000..37fd71b6aa3b00632bf3c48ad85ab9aa077e101d --- /dev/null +++ b/plat/arm/board/diphda/common/include/platform_def.h @@ -0,0 +1,416 @@ +/* + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ARM_ROTPK_HEADER_LEN 19 +#define ARM_ROTPK_HASH_LEN 32 + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) + +/* PL011 UART related constants */ +#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ +#undef V2M_IOFPGA_UART0_CLK_IN_HZ +#endif + +#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ +#undef V2M_IOFPGA_UART1_CLK_IN_HZ +#endif + +#define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000 +#define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000 + +/* Core/Cluster/Thread counts for diphda */ +#define DIPHDA_CLUSTER_COUNT U(1) +#define DIPHDA_MAX_CPUS_PER_CLUSTER U(4) +#define DIPHDA_MAX_PE_PER_CPU U(1) +#define DIPHDA_PRIMARY_CPU U(0) + +#define PLAT_ARM_CLUSTER_COUNT DIPHDA_CLUSTER_COUNT + +#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ + DIPHDA_MAX_CPUS_PER_CLUSTER * \ + DIPHDA_MAX_PE_PER_CPU) + +/* UART related constants */ +#define PLAT_ARM_BOOT_UART_BASE 0x1a510000 +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ +#define PLAT_ARM_RUN_UART_BASE 0x1a520000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ +#define ARM_CONSOLE_BAUDRATE 115200 +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ + +/* Memory related constants */ + +/* SRAM (CVM) memory layout + * + * + * + * partition size: sizeof(meminfo_t) = 16 bytes + * + * content: memory info area used by the next BL + * + * + * + * partition size: 4080 bytes + * + * + * + * partition size: 4 KB + * + * content: + * + * Area where BL2 copies the images descriptors + * + * = + * + * partition size: 688 KB + * + * content: + * + * BL32 (optee-os) + * + * = 0x20ae000 + * + * partition size: 8 KB + * + * content: + * + * BL32 config (TOS_FW_CONFIG) + * + * + * + * partition size: 140 KB + * + * content: + * + * BL31 + * + * + * + * partition size: 4 KB + * + * content: + * + * MCUBOOT data needed to verify TF-A BL2 + * + * + * + * partition size: 176 KB + * + * content: + * + * BL2 + * + * = + 1 MB + * + * partition size: 3 MB + * + * content: + * + * BL33 (u-boot) + */ + +/* DDR memory */ +#define ARM_DRAM1_BASE UL(0x80000000) +#define ARM_DRAM1_SIZE UL(0x80000000) +#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - 1) + +/* DRAM1 and DRAM2 are the same for diphda */ +#define ARM_DRAM2_BASE ARM_DRAM1_BASE +#define ARM_DRAM2_SIZE ARM_DRAM1_SIZE +#define ARM_DRAM2_END ARM_DRAM1_END + +#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE +#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ + ARM_NS_DRAM1_SIZE - 1) + +/* The first 8 KB of Trusted SRAM are used as shared memory */ +#define ARM_TRUSTED_SRAM_BASE UL(0x02000000) +#define ARM_SHARED_RAM_SIZE UL(0x00002000) /* 8 KB */ +#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE + +/* The remaining Trusted SRAM is used to load the BL images */ + +#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00100000) /* 1 MB */ + +#define PLAT_ARM_MAX_BL2_SIZE UL(0x0002d000) /* 180 KB */ + +#define PLAT_ARM_MAX_BL31_SIZE UL(0x00023000) /* 140 KB */ + +#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ + ARM_SHARED_RAM_SIZE) +#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ + ARM_SHARED_RAM_SIZE) + +#define BL2_SIGNATURE_SIZE UL(0x00001000) /* 4 KB */ +#define BL2_SIGNATURE_BASE (BL2_LIMIT - \ + PLAT_ARM_MAX_BL2_SIZE) +#define BL2_BASE (BL2_LIMIT - \ + PLAT_ARM_MAX_BL2_SIZE + \ + BL2_SIGNATURE_SIZE) +#define BL2_LIMIT (ARM_BL_RAM_BASE + \ + ARM_BL_RAM_SIZE) + +#define BL31_BASE (BL2_SIGNATURE_BASE - \ + PLAT_ARM_MAX_BL31_SIZE) +#define BL31_LIMIT BL2_SIGNATURE_BASE + +#define DIPHDA_TOS_FW_CONFIG_BASE (BL31_BASE - \ + DIPHDA_TOS_FW_CONFIG_SIZE) +#define DIPHDA_TOS_FW_CONFIG_SIZE UL(0x00002000) /* 8 KB */ +#define DIPHDA_TOS_FW_CONFIG_LIMIT BL31_BASE + +#define BL32_BASE ARM_BL_RAM_BASE +#define PLAT_ARM_MAX_BL32_SIZE (DIPHDA_TOS_FW_CONFIG_BASE - \ + BL32_BASE) /* 688 KB */ +#define BL32_LIMIT (BL32_BASE + \ + PLAT_ARM_MAX_BL32_SIZE) + +/* SPD_spmd settings */ + +#define PLAT_ARM_SPMC_BASE BL32_BASE +#define PLAT_ARM_SPMC_SIZE PLAT_ARM_MAX_BL32_SIZE + +/* NS memory */ + +/* The last 3 MB of the SRAM is allocated to the non secure area */ +#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + \ + PLAT_ARM_TRUSTED_SRAM_SIZE) +#define ARM_NS_SHARED_RAM_SIZE UL(0x00300000) /* 3 MB */ + +/* end of the definition of SRAM memory layout */ + +/* NOR Flash */ + +#define PLAT_ARM_FIP_BASE UL(0x08131000) +#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ + +#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE +#define PLAT_ARM_NVM_SIZE UL(0x02000000) /* 32 MB */ + +#define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE +#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) +#define ARM_CACHE_WRITEBACK_SHIFT 6 + +/* + * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo. + * FW_CONFIG is intended to host the device tree. Currently, This area is not + * used because diphda platform doesn't use a device tree at TF-A level. + */ +#define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE \ + + sizeof(meminfo_t)) +#define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE \ + + (ARM_SHARED_RAM_SIZE >> 1)) + +/* + * Boot parameters passed from BL2 to BL31/BL32 are stored here + */ +#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT +#define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE + +/* + * The max number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#define ARM_BL_REGIONS 3 +#define PLAT_ARM_MMAP_ENTRIES 8 +#define MAX_XLAT_TABLES 5 +#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ + ARM_BL_REGIONS) +#define MAX_IO_DEVICES 2 +#define MAX_IO_HANDLES 3 +#define MAX_IO_BLOCK_DEVICES 1 + +/* GIC related constants */ +#define PLAT_ARM_GICD_BASE 0x1C010000 +#define PLAT_ARM_GICC_BASE 0x1C02F000 + +/* MHUv2 Secure Channel receiver and sender */ +#define PLAT_SDK700_MHU0_SEND 0x1B800000 +#define PLAT_SDK700_MHU0_RECV 0x1B810000 + +/* Timer/watchdog related constants */ +#define ARM_SYS_CNTCTL_BASE UL(0x1a200000) +#define ARM_SYS_CNTREAD_BASE UL(0x1a210000) +#define ARM_SYS_TIMCTL_BASE UL(0x1a220000) + +#define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ + +#define DIPHDA_IRQ_TZ_WDOG 32 +#define DIPHDA_IRQ_SEC_SYS_TIMER 34 + +#define PLAT_MAX_PWR_LVL 2 +/* + * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The + * power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +#define ARM_PWR_LVL0 MPIDR_AFFLVL0 +#define ARM_PWR_LVL1 MPIDR_AFFLVL1 +#define ARM_PWR_LVL2 MPIDR_AFFLVL2 + +/* + * Macros for local power states in ARM platforms encoded by State-ID field + * within the power-state parameter. + */ +/* Local power state for power domains in Run state. */ +#define ARM_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define ARM_LOCAL_STATE_RET U(1) +/* Local power state for OFF/power-down. Valid for CPU and cluster + * power domains + */ +#define ARM_LOCAL_STATE_OFF U(2) + +#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE +#define PLAT_ARM_NSTIMER_FRAME_ID U(1) + +#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE) + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +/* + * This macro defines the deepest retention state possible. A higher state + * ID will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE 1 + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE 2 + +#define PLATFORM_STACK_SIZE UL(0x440) + +#define DIPHDA_EXTERNAL_FLASH MAP_REGION_FLAT( \ + PLAT_ARM_NVM_BASE, \ + PLAT_ARM_NVM_SIZE, \ + MT_DEVICE | MT_RO | MT_SECURE) + +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, \ + ARM_SHARED_RAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \ + ARM_NS_SHARED_RAM_BASE, \ + ARM_NS_SHARED_RAM_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, \ + ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END \ + - BL_CODE_BASE, \ + MT_CODE | MT_SECURE), \ + MAP_REGION_FLAT( \ + BL_RO_DATA_BASE, \ + BL_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) +#if USE_COHERENT_MEM +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +/* + * Map the region for the optional device tree configuration with read and + * write permissions + */ +#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ + ARM_FW_CONFIG_BASE, \ + (ARM_FW_CONFIG_LIMIT- \ + ARM_FW_CONFIG_BASE), \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define DIPHDA_DEVICE_BASE (0x1A000000) +#define DIPHDA_DEVICE_SIZE (0x26000000) +#define DIPHDA_MAP_DEVICE MAP_REGION_FLAT( \ + DIPHDA_DEVICE_BASE, \ + DIPHDA_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_EDGE) + +#define ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE) + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(DIPHDA_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(DIPHDA_IRQ_SEC_SYS_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/diphda/include/plat_macros.S b/plat/arm/board/diphda/include/plat_macros.S new file mode 100644 index 0000000000000000000000000000000000000000..4de8f95027dd58a197ac54dea6d99b1298e4f516 --- /dev/null +++ b/plat/arm/board/diphda/include/plat_macros.S @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include + +/* --------------------------------------------- + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + * --------------------------------------------- + */ + .macro plat_crash_print_regs + css_print_gic_regs + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/arm/board/diphda/platform.mk b/plat/arm/board/diphda/platform.mk new file mode 100644 index 0000000000000000000000000000000000000000..5ff08620c091ee6208e5760c01f7c6f1d4923ef1 --- /dev/null +++ b/plat/arm/board/diphda/platform.mk @@ -0,0 +1,76 @@ +# +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Making sure the diphda platform type is specified +ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),) + $(error TARGET_PLATFORM must be fpga or fvp) +endif + +DIPHDA_CPU_LIBS +=lib/cpus/aarch64/cortex_a35.S + +PLAT_INCLUDES := -Iplat/arm/board/diphda/common/include \ + -Iplat/arm/board/diphda/include \ + -Iinclude/plat/arm/common \ + -Iinclude/plat/arm/css/common/aarch64 + + +DIPHDA_FW_NVCTR_VAL := 255 +TFW_NVCTR_VAL := ${DIPHDA_FW_NVCTR_VAL} +NTFW_NVCTR_VAL := ${DIPHDA_FW_NVCTR_VAL} + +override NEED_BL1 := no + +override NEED_BL2 := yes +FIP_BL2_ARGS := tb-fw + +override NEED_BL2U := no +override NEED_BL31 := yes +NEED_BL32 := yes +override NEED_BL33 := yes + +# Include GICv2 driver files +include drivers/arm/gic/v2/gicv2.mk + +DIPHDA_GIC_SOURCES := ${GICV2_SOURCES} \ + plat/common/plat_gicv2.c \ + plat/arm/common/arm_gicv2.c + + +BL2_SOURCES += plat/arm/board/diphda/common/diphda_security.c \ + plat/arm/board/diphda/common/diphda_err.c \ + plat/arm/board/diphda/common/diphda_trusted_boot.c \ + lib/utils/mem_region.c \ + plat/arm/board/diphda/common/diphda_helpers.S \ + plat/arm/board/diphda/common/diphda_plat.c \ + plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c \ + ${DIPHDA_CPU_LIBS} \ + + +BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ + lib/utils/mem_region.c \ + plat/arm/board/diphda/common/diphda_helpers.S \ + plat/arm/board/diphda/common/diphda_topology.c \ + plat/arm/board/diphda/common/diphda_security.c \ + plat/arm/board/diphda/common/diphda_plat.c \ + plat/arm/board/diphda/common/diphda_pm.c \ + ${DIPHDA_CPU_LIBS} \ + ${DIPHDA_GIC_SOURCES} + + +FDT_SOURCES += plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts +DIPHDA_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/diphda_spmc_manifest.dtb + +# Add the SPMC manifest to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${DIPHDA_TOS_FW_CONFIG},--tos-fw-config,${DIPHDA_TOS_FW_CONFIG})) + +# Adding TARGET_PLATFORM as a GCC define (-D option) +$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM}))) + +# Adding DIPHDA_FW_NVCTR_VAL as a GCC define (-D option) +$(eval $(call add_define,DIPHDA_FW_NVCTR_VAL)) + +include plat/arm/common/arm_common.mk +include plat/arm/board/common/board_common.mk diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index f1e4cf505662be186796fdd470eb86c630468dfc..de25a538d989bd94eec2e3b21f9e1e919eb6a314 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -256,8 +256,10 @@ endif ifeq (${JUNO_AARCH32_EL3_RUNTIME},1) BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c else +ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),) BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c endif +endif BL2_SOURCES += plat/arm/common/arm_image_load.c \ common/desc_image_load.c ifeq (${SPD},opteed)