Merge changes from topic "tegra-misra-21.1-fixes" into integration

* changes:
  Tegra194: drivers: fix violations of MISRA Rule 21.1
  Tegra: include: fix violations of MISRA Rule 21.1

plat/nvidia/tegra/include/drivers/bpmp_ipc.h

 /*
  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __BPMP_IPC_H__
-#define __BPMP_IPC_H__
+#ifndef BPMP_IPC_H
+#define BPMP_IPC_H
 
 #include <lib/utils_def.h>
 #include <stdbool.h>
@@ -44,4 +45,4 @@ int tegra_bpmp_ipc_enable_clock(uint32_t clk_id);
  */
 int tegra_bpmp_ipc_disable_clock(uint32_t clk_id);
 
-#endif /* __BPMP_IPC_H__ */
+#endif /* BPMP_IPC_H */

plat/nvidia/tegra/include/drivers/gpcdma.h

 /*
  * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __GPCDMA_H__
-#define __GPCDMA_H__
+#ifndef GPCDMA_H
+#define GPCDMA_H
 
 #include <stdint.h>
 
@@ -13,4 +14,4 @@ void tegra_gpcdma_memcpy(uint64_t dst_addr, uint64_t src_addr,
 			    uint32_t num_bytes);
 void tegra_gpcdma_zeromem(uint64_t dst_addr, uint32_t num_bytes);
 
-#endif /* __GPCDMA_H__ */
+#endif /* GPCDMA_H */

plat/nvidia/tegra/include/drivers/tegra_gic.h

 /*
  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __TEGRA_GIC_H__
-#define __TEGRA_GIC_H__
+#ifndef TEGRA_GIC_H
+#define TEGRA_GIC_H
 
 #include <common/interrupt_props.h>
 
@@ -26,4 +27,4 @@ void tegra_gic_pcpu_init(void);
 void tegra_gic_setup(const interrupt_prop_t *interrupt_props,
 		     unsigned int interrupt_props_num);
 
-#endif /* __TEGRA_GIC_H__ */
+#endif /* TEGRA_GIC_H */

plat/nvidia/tegra/include/lib/profiler.h

 /*
  * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PROFILER_H__
-#define __PROFILER_H__
+#ifndef PROFILER_H
+#define PROFILER_H
 
 /*******************************************************************************
  * Number of bytes of memory used by the profiler on Tegra
@@ -16,4 +17,4 @@ void boot_profiler_init(uint64_t shmem_base, uint32_t tmr_base);
 void boot_profiler_add_record(const char *str);
 void boot_profiler_deinit(void);
 
-#endif /* __PROFILER_H__ */
+#endif /* PROFILER_H */

plat/nvidia/tegra/include/t194/tegra194_private.h

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __TEGRA194_PRIVATE_H__
-#define __TEGRA194_PRIVATE_H__
+#ifndef TEGRA194_PRIVATE_H
+#define TEGRA194_PRIVATE_H
 
 void tegra194_cpu_reset_handler(void);
 uint64_t tegra194_get_cpu_reset_handler_base(void);
@@ -13,4 +13,4 @@ uint64_t tegra194_get_cpu_reset_handler_size(void);
 uint64_t tegra194_get_smmu_ctx_offset(void);
 void tegra194_set_system_suspend_entry(void);
 
-#endif /* __TEGRA194_PRIVATE_H__ */
+#endif /* TEGRA194_PRIVATE_H */

plat/nvidia/tegra/include/t194/tegra_def.h

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __TEGRA_DEF_H__
-#define __TEGRA_DEF_H__
+#ifndef TEGRA_DEF_H
+#define TEGRA_DEF_H
 
 #include <lib/utils_def.h>
 
@@ -237,4 +237,4 @@
 #define TEGRA_SID_XUSB_VF2			U(0x5f)
 #define TEGRA_SID_XUSB_VF3			U(0x60)
 
-#endif /* __TEGRA_DEF_H__ */
+#endif /* TEGRA_DEF_H */

plat/nvidia/tegra/include/t194/tegra_mc_def.h

 /*
- * Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __TEGRA_MC_DEF_H__
-#define __TEGRA_MC_DEF_H__
+#ifndef TEGRA_MC_DEF_H
+#define TEGRA_MC_DEF_H
 
 /*******************************************************************************
  * Memory Controller Order_id registers
@@ -647,4 +647,4 @@
 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK			(ULL(0x3) << 11)
 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU			(ULL(0) << 11)
 
-#endif /* __TEGRA_MC_DEF_H__ */
+#endif /* TEGRA_MC_DEF_H */

plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __MCE_PRIVATE_H__
-#define __MCE_PRIVATE_H__
+#ifndef MCE_PRIVATE_H
+#define MCE_PRIVATE_H
 
 #include <tegra_def.h>
 
@@ -71,4 +71,4 @@ void nvg_enable_strict_checking_mode(void);
 /* MCE helper functions */
 void mce_enable_strict_checking(void);
 
-#endif /* __MCE_PRIVATE_H__ */
+#endif /* MCE_PRIVATE_H */

plat/nvidia/tegra/soc/t194/drivers/include/se.h

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __SE_H__
-#define __SE_H__
+#ifndef SE_H
+#define SE_H
 
 int32_t tegra_se_suspend(void);
 void tegra_se_resume(void);
 
-#endif /* __SE_H__ */
+#endif /* SE_H */

plat/nvidia/tegra/soc/t194/drivers/se/se_private.h

 /*
  * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __SE_PRIVATE_H__
-#define __SE_PRIVATE_H__
+#ifndef SE_PRIVATE_H
+#define SE_PRIVATE_H
 
 #include <lib/utils_def.h>
 
@@ -82,4 +82,4 @@ static inline void tegra_se_write_32(uint32_t offset, uint32_t val)
 	mmio_write_32(TEGRA_SE0_BASE + offset, val);
 }
 
-#endif /* __SE_PRIVATE_H__ */
+#endif /* SE_PRIVATE_H */