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Commit d6845d3d authored by davidcunado-arm's avatar davidcunado-arm Committed by GitHub
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Merge pull request #835 from rockchip-linux/rk3399-atf-cleanup-20170210 

RK3399 ARM TF clean up 20170210
parents 86a3b266 ccdc044a
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plat/rockchip/rk3399/drivers/pmu/pmu.h
View file @ d6845d3d
......@@ -31,6 +31,7 @@
#ifndef __PMU_H__
#define __PMU_H__
#include <pmu_bits.h>
#include <pmu_regs.h>
#include <soc.h>
......@@ -67,693 +68,6 @@ enum pmu_core_pwrst_shift {
#define CKECK_WFI_MSK 0x10
#define CKECK_WFEI_MSK 0x11
enum pmu_powerdomain_id {
PD_CPUL0 = 0,
PD_CPUL1,
PD_CPUL2,
PD_CPUL3,
PD_CPUB0,
PD_CPUB1,
PD_SCUL,
PD_SCUB,
PD_TCPD0,
PD_TCPD1,
PD_CCI,
PD_PERILP,
PD_PERIHP,
PD_CENTER,
PD_VIO,
PD_GPU,
PD_VCODEC,
PD_VDU,
PD_RGA,
PD_IEP,
PD_VO,
PD_ISP0 = 22,
PD_ISP1,
PD_HDCP,
PD_GMAC,
PD_EMMC,
PD_USB3,
PD_EDP,
PD_GIC,
PD_SD,
PD_SDIOAUDIO,
PD_END
};
enum powerdomain_state {
PMU_POWER_ON = 0,
PMU_POWER_OFF,
};
enum pmu_bus_id {
BUS_ID_GPU = 0,
BUS_ID_PERILP,
BUS_ID_PERIHP,
BUS_ID_VCODEC,
BUS_ID_VDU,
BUS_ID_RGA,
BUS_ID_IEP,
BUS_ID_VOPB,
BUS_ID_VOPL,
BUS_ID_ISP0,
BUS_ID_ISP1,
BUS_ID_HDCP,
BUS_ID_USB3,
BUS_ID_PERILPM0,
BUS_ID_CENTER,
BUS_ID_CCIM0,
BUS_ID_CCIM1,
BUS_ID_VIO,
BUS_ID_MSCH0,
BUS_ID_MSCH1,
BUS_ID_ALIVE,
BUS_ID_PMU,
BUS_ID_EDP,
BUS_ID_GMAC,
BUS_ID_EMMC,
BUS_ID_CENTER1,
BUS_ID_PMUM0,
BUS_ID_GIC,
BUS_ID_SD,
BUS_ID_SDIOAUDIO,
};
enum pmu_bus_state {
BUS_ACTIVE,
BUS_IDLE,
};
/* pmu_cpuapm bit */
enum pmu_cores_pm_by_wfi {
core_pm_en = 0,
core_pm_int_wakeup_en,
core_pm_resv,
core_pm_sft_wakeup_en
};
enum pmu_wkup_cfg0 {
PMU_GPIO0A_POSE_WKUP_EN = 0,
PMU_GPIO0B_POSE_WKUP_EN = 8,
PMU_GPIO0C_POSE_WKUP_EN = 16,
PMU_GPIO0D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg1 {
PMU_GPIO0A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO0B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO0C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO0D_NEGEDGE_WKUP_EN = 24,
};
enum pmu_wkup_cfg2 {
PMU_GPIO1A_POSE_WKUP_EN = 0,
PMU_GPIO1B_POSE_WKUP_EN = 7,
PMU_GPIO1C_POSE_WKUP_EN = 16,
PMU_GPIO1D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg3 {
PMU_GPIO1A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO1B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO1C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO1D_NEGEDGE_WKUP_EN = 24,
};
/* pmu_wkup_cfg4 */
enum pmu_wkup_cfg4 {
PMU_CLUSTER_L_WKUP_EN = 0,
PMU_CLUSTER_B_WKUP_EN,
PMU_GPIO_WKUP_EN,
PMU_SDIO_WKUP_EN,
PMU_SDMMC_WKUP_EN,
PMU_TIMER_WKUP_EN = 6,
PMU_USBDEV_WKUP_EN,
PMU_SFT_WKUP_EN,
PMU_M0_WDT_WKUP_EN,
PMU_TIMEOUT_WKUP_EN,
PMU_PWM_WKUP_EN,
PMU_PCIE_WKUP_EN = 13,
};
enum pmu_pwrdn_con {
PMU_A53_L0_PWRDWN_EN = 0,
PMU_A53_L1_PWRDWN_EN,
PMU_A53_L2_PWRDWN_EN,
PMU_A53_L3_PWRDWN_EN,
PMU_A72_B0_PWRDWN_EN,
PMU_A72_B1_PWRDWN_EN,
PMU_SCU_L_PWRDWN_EN,
PMU_SCU_B_PWRDWN_EN,
PMU_TCPD0_PWRDWN_EN,
PMU_TCPD1_PWRDWN_EN,
PMU_CCI_PWRDWN_EN,
PMU_PERILP_PWRDWN_EN,
PMU_PERIHP_PWRDWN_EN,
PMU_CENTER_PWRDWN_EN,
PMU_VIO_PWRDWN_EN,
PMU_GPU_PWRDWN_EN,
PMU_VCODEC_PWRDWN_EN,
PMU_VDU_PWRDWN_EN,
PMU_RGA_PWRDWN_EN,
PMU_IEP_PWRDWN_EN,
PMU_VO_PWRDWN_EN,
PMU_ISP0_PWRDWN_EN = 22,
PMU_ISP1_PWRDWN_EN,
PMU_HDCP_PWRDWN_EN,
PMU_GMAC_PWRDWN_EN,
PMU_EMMC_PWRDWN_EN,
PMU_USB3_PWRDWN_EN,
PMU_EDP_PWRDWN_EN,
PMU_GIC_PWRDWN_EN,
PMU_SD_PWRDWN_EN,
PMU_SDIOAUDIO_PWRDWN_EN,
};
enum pmu_pwrdn_st {
PMU_A53_L0_PWRDWN_ST = 0,
PMU_A53_L1_PWRDWN_ST,
PMU_A53_L2_PWRDWN_ST,
PMU_A53_L3_PWRDWN_ST,
PMU_A72_B0_PWRDWN_ST,
PMU_A72_B1_PWRDWN_ST,
PMU_SCU_L_PWRDWN_ST,
PMU_SCU_B_PWRDWN_ST,
PMU_TCPD0_PWRDWN_ST,
PMU_TCPD1_PWRDWN_ST,
PMU_CCI_PWRDWN_ST,
PMU_PERILP_PWRDWN_ST,
PMU_PERIHP_PWRDWN_ST,
PMU_CENTER_PWRDWN_ST,
PMU_VIO_PWRDWN_ST,
PMU_GPU_PWRDWN_ST,
PMU_VCODEC_PWRDWN_ST,
PMU_VDU_PWRDWN_ST,
PMU_RGA_PWRDWN_ST,
PMU_IEP_PWRDWN_ST,
PMU_VO_PWRDWN_ST,
PMU_ISP0_PWRDWN_ST = 22,
PMU_ISP1_PWRDWN_ST,
PMU_HDCP_PWRDWN_ST,
PMU_GMAC_PWRDWN_ST,
PMU_EMMC_PWRDWN_ST,
PMU_USB3_PWRDWN_ST,
PMU_EDP_PWRDWN_ST,
PMU_GIC_PWRDWN_ST,
PMU_SD_PWRDWN_ST,
PMU_SDIOAUDIO_PWRDWN_ST,
};
enum pmu_pll_con {
PMU_PLL_PD_CFG = 0,
PMU_SFT_PLL_PD = 8,
};
enum pmu_pwermode_con {
PMU_PWR_MODE_EN = 0,
PMU_WKUP_RST_EN,
PMU_INPUT_CLAMP_EN,
PMU_OSC_DIS,
PMU_ALIVE_USE_LF,
PMU_PMU_USE_LF,
PMU_POWER_OFF_REQ_CFG,
PMU_CHIP_PD_EN,
PMU_PLL_PD_EN,
PMU_CPU0_PD_EN,
PMU_L2_FLUSH_EN,
PMU_L2_IDLE_EN,
PMU_SCU_PD_EN,
PMU_CCI_PD_EN,
PMU_PERILP_PD_EN,
PMU_CENTER_PD_EN,
PMU_SREF0_ENTER_EN,
PMU_DDRC0_GATING_EN,
PMU_DDRIO0_RET_EN,
PMU_DDRIO0_RET_DE_REQ,
PMU_SREF1_ENTER_EN,
PMU_DDRC1_GATING_EN,
PMU_DDRIO1_RET_EN,
PMU_DDRIO1_RET_DE_REQ,
PMU_CLK_CENTER_SRC_GATE_EN = 26,
PMU_CLK_PERILP_SRC_GATE_EN,
PMU_CLK_CORE_SRC_GATE_EN,
PMU_DDRIO_RET_HW_DE_REQ,
PMU_SLP_OUTPUT_CFG,
PMU_MAIN_CLUSTER,
};
enum pmu_sft_con {
PMU_WKUP_SFT = 0,
PMU_INPUT_CLAMP_CFG,
PMU_OSC_DIS_CFG,
PMU_PMU_LF_EN_CFG,
PMU_ALIVE_LF_EN_CFG,
PMU_24M_EN_CFG,
PMU_DBG_PWRUP_L0_CFG,
PMU_WKUP_SFT_M0,
PMU_DDRCTL0_C_SYSREQ_CFG,
PMU_DDR0_IO_RET_CFG,
PMU_DDRCTL1_C_SYSREQ_CFG = 12,
PMU_DDR1_IO_RET_CFG,
DBG_PWRUP_B0_CFG = 15,
DBG_NOPWERDWN_L0_EN,
DBG_NOPWERDWN_L1_EN,
DBG_NOPWERDWN_L2_EN,
DBG_NOPWERDWN_L3_EN,
DBG_PWRUP_REQ_L_EN = 20,
CLUSTER_L_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_L,
ACINACTM_CLUSTER_L_CFG,
DBG_NO_PWERDWN_B0_EN,
DBG_NO_PWERDWN_B1_EN,
DBG_PWRUP_REQ_B_EN = 28,
CLUSTER_B_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_B,
ACINACTM_CLUSTER_B_CFG,
};
enum pmu_int_con {
PMU_PMU_INT_EN = 0,
PMU_PWRMD_WKUP_INT_EN,
PMU_WKUP_GPIO0_NEG_INT_EN,
PMU_WKUP_GPIO0_POS_INT_EN,
PMU_WKUP_GPIO1_NEG_INT_EN,
PMU_WKUP_GPIO1_POS_INT_EN,
};
enum pmu_int_st {
PMU_PWRMD_WKUP_INT_ST = 1,
PMU_WKUP_GPIO0_NEG_INT_ST,
PMU_WKUP_GPIO0_POS_INT_ST,
PMU_WKUP_GPIO1_NEG_INT_ST,
PMU_WKUP_GPIO1_POS_INT_ST,
};
enum pmu_gpio0_pos_int_con {
PMU_GPIO0A_POS_INT_EN = 0,
PMU_GPIO0B_POS_INT_EN = 8,
PMU_GPIO0C_POS_INT_EN = 16,
PMU_GPIO0D_POS_INT_EN = 24,
};
enum pmu_gpio0_neg_int_con {
PMU_GPIO0A_NEG_INT_EN = 0,
PMU_GPIO0B_NEG_INT_EN = 8,
PMU_GPIO0C_NEG_INT_EN = 16,
PMU_GPIO0D_NEG_INT_EN = 24,
};
enum pmu_gpio1_pos_int_con {
PMU_GPIO1A_POS_INT_EN = 0,
PMU_GPIO1B_POS_INT_EN = 8,
PMU_GPIO1C_POS_INT_EN = 16,
PMU_GPIO1D_POS_INT_EN = 24,
};
enum pmu_gpio1_neg_int_con {
PMU_GPIO1A_NEG_INT_EN = 0,
PMU_GPIO1B_NEG_INT_EN = 8,
PMU_GPIO1C_NEG_INT_EN = 16,
PMU_GPIO1D_NEG_INT_EN = 24,
};
enum pmu_gpio0_pos_int_st {
PMU_GPIO0A_POS_INT_ST = 0,
PMU_GPIO0B_POS_INT_ST = 8,
PMU_GPIO0C_POS_INT_ST = 16,
PMU_GPIO0D_POS_INT_ST = 24,
};
enum pmu_gpio0_neg_int_st {
PMU_GPIO0A_NEG_INT_ST = 0,
PMU_GPIO0B_NEG_INT_ST = 8,
PMU_GPIO0C_NEG_INT_ST = 16,
PMU_GPIO0D_NEG_INT_ST = 24,
};
enum pmu_gpio1_pos_int_st {
PMU_GPIO1A_POS_INT_ST = 0,
PMU_GPIO1B_POS_INT_ST = 8,
PMU_GPIO1C_POS_INT_ST = 16,
PMU_GPIO1D_POS_INT_ST = 24,
};
enum pmu_gpio1_neg_int_st {
PMU_GPIO1A_NEG_INT_ST = 0,
PMU_GPIO1B_NEG_INT_ST = 8,
PMU_GPIO1C_NEG_INT_ST = 16,
PMU_GPIO1D_NEG_INT_ST = 24,
};
/* pmu power down configure register 0x0050 */
enum pmu_pwrdn_inten {
PMU_A53_L0_PWR_SWITCH_INT_EN = 0,
PMU_A53_L1_PWR_SWITCH_INT_EN,
PMU_A53_L2_PWR_SWITCH_INT_EN,
PMU_A53_L3_PWR_SWITCH_INT_EN,
PMU_A72_B0_PWR_SWITCH_INT_EN,
PMU_A72_B1_PWR_SWITCH_INT_EN,
PMU_SCU_L_PWR_SWITCH_INT_EN,
PMU_SCU_B_PWR_SWITCH_INT_EN,
PMU_TCPD0_PWR_SWITCH_INT_EN,
PMU_TCPD1_PWR_SWITCH_INT_EN,
PMU_CCI_PWR_SWITCH_INT_EN,
PMU_PERILP_PWR_SWITCH_INT_EN,
PMU_PERIHP_PWR_SWITCH_INT_EN,
PMU_CENTER_PWR_SWITCH_INT_EN,
PMU_VIO_PWR_SWITCH_INT_EN,
PMU_GPU_PWR_SWITCH_INT_EN,
PMU_VCODEC_PWR_SWITCH_INT_EN,
PMU_VDU_PWR_SWITCH_INT_EN,
PMU_RGA_PWR_SWITCH_INT_EN,
PMU_IEP_PWR_SWITCH_INT_EN,
PMU_VO_PWR_SWITCH_INT_EN,
PMU_ISP0_PWR_SWITCH_INT_EN = 22,
PMU_ISP1_PWR_SWITCH_INT_EN,
PMU_HDCP_PWR_SWITCH_INT_EN,
PMU_GMAC_PWR_SWITCH_INT_EN,
PMU_EMMC_PWR_SWITCH_INT_EN,
PMU_USB3_PWR_SWITCH_INT_EN,
PMU_EDP_PWR_SWITCH_INT_EN,
PMU_GIC_PWR_SWITCH_INT_EN,
PMU_SD_PWR_SWITCH_INT_EN,
PMU_SDIOAUDIO_PWR_SWITCH_INT_EN,
};
enum pmu_wkup_status {
PMU_WKUP_BY_CLSTER_L_INT = 0,
PMU_WKUP_BY_CLSTER_b_INT,
PMU_WKUP_BY_GPIO_INT,
PMU_WKUP_BY_SDIO_DET,
PMU_WKUP_BY_SDMMC_DET,
PMU_WKUP_BY_TIMER = 6,
PMU_WKUP_BY_USBDEV_DET,
PMU_WKUP_BY_M0_SFT,
PMU_WKUP_BY_M0_WDT_INT,
PMU_WKUP_BY_TIMEOUT,
PMU_WKUP_BY_PWM,
PMU_WKUP_BY_PCIE = 13,
};
enum pmu_bus_clr {
PMU_CLR_GPU = 0,
PMU_CLR_PERILP,
PMU_CLR_PERIHP,
PMU_CLR_VCODEC,
PMU_CLR_VDU,
PMU_CLR_RGA,
PMU_CLR_IEP,
PMU_CLR_VOPB,
PMU_CLR_VOPL,
PMU_CLR_ISP0,
PMU_CLR_ISP1,
PMU_CLR_HDCP,
PMU_CLR_USB3,
PMU_CLR_PERILPM0,
PMU_CLR_CENTER,
PMU_CLR_CCIM1,
PMU_CLR_CCIM0,
PMU_CLR_VIO,
PMU_CLR_MSCH0,
PMU_CLR_MSCH1,
PMU_CLR_ALIVE,
PMU_CLR_PMU,
PMU_CLR_EDP,
PMU_CLR_GMAC,
PMU_CLR_EMMC,
PMU_CLR_CENTER1,
PMU_CLR_PMUM0,
PMU_CLR_GIC,
PMU_CLR_SD,
PMU_CLR_SDIOAUDIO,
};
/* PMU bus idle request register */
enum pmu_bus_idle_req {
PMU_IDLE_REQ_GPU = 0,
PMU_IDLE_REQ_PERILP,
PMU_IDLE_REQ_PERIHP,
PMU_IDLE_REQ_VCODEC,
PMU_IDLE_REQ_VDU,
PMU_IDLE_REQ_RGA,
PMU_IDLE_REQ_IEP,
PMU_IDLE_REQ_VOPB,
PMU_IDLE_REQ_VOPL,
PMU_IDLE_REQ_ISP0,
PMU_IDLE_REQ_ISP1,
PMU_IDLE_REQ_HDCP,
PMU_IDLE_REQ_USB3,
PMU_IDLE_REQ_PERILPM0,
PMU_IDLE_REQ_CENTER,
PMU_IDLE_REQ_CCIM0,
PMU_IDLE_REQ_CCIM1,
PMU_IDLE_REQ_VIO,
PMU_IDLE_REQ_MSCH0,
PMU_IDLE_REQ_MSCH1,
PMU_IDLE_REQ_ALIVE,
PMU_IDLE_REQ_PMU,
PMU_IDLE_REQ_EDP,
PMU_IDLE_REQ_GMAC,
PMU_IDLE_REQ_EMMC,
PMU_IDLE_REQ_CENTER1,
PMU_IDLE_REQ_PMUM0,
PMU_IDLE_REQ_GIC,
PMU_IDLE_REQ_SD,
PMU_IDLE_REQ_SDIOAUDIO,
};
/* pmu bus idle status register */
enum pmu_bus_idle_st {
PMU_IDLE_ST_GPU = 0,
PMU_IDLE_ST_PERILP,
PMU_IDLE_ST_PERIHP,
PMU_IDLE_ST_VCODEC,
PMU_IDLE_ST_VDU,
PMU_IDLE_ST_RGA,
PMU_IDLE_ST_IEP,
PMU_IDLE_ST_VOPB,
PMU_IDLE_ST_VOPL,
PMU_IDLE_ST_ISP0,
PMU_IDLE_ST_ISP1,
PMU_IDLE_ST_HDCP,
PMU_IDLE_ST_USB3,
PMU_IDLE_ST_PERILPM0,
PMU_IDLE_ST_CENTER,
PMU_IDLE_ST_CCIM0,
PMU_IDLE_ST_CCIM1,
PMU_IDLE_ST_VIO,
PMU_IDLE_ST_MSCH0,
PMU_IDLE_ST_MSCH1,
PMU_IDLE_ST_ALIVE,
PMU_IDLE_ST_PMU,
PMU_IDLE_ST_EDP,
PMU_IDLE_ST_GMAC,
PMU_IDLE_ST_EMMC,
PMU_IDLE_ST_CENTER1,
PMU_IDLE_ST_PMUM0,
PMU_IDLE_ST_GIC,
PMU_IDLE_ST_SD,
PMU_IDLE_ST_SDIOAUDIO,
};
enum pmu_bus_idle_ack {
PMU_IDLE_ACK_GPU = 0,
PMU_IDLE_ACK_PERILP,
PMU_IDLE_ACK_PERIHP,
PMU_IDLE_ACK_VCODEC,
PMU_IDLE_ACK_VDU,
PMU_IDLE_ACK_RGA,
PMU_IDLE_ACK_IEP,
PMU_IDLE_ACK_VOPB,
PMU_IDLE_ACK_VOPL,
PMU_IDLE_ACK_ISP0,
PMU_IDLE_ACK_ISP1,
PMU_IDLE_ACK_HDCP,
PMU_IDLE_ACK_USB3,
PMU_IDLE_ACK_PERILPM0,
PMU_IDLE_ACK_CENTER,
PMU_IDLE_ACK_CCIM0,
PMU_IDLE_ACK_CCIM1,
PMU_IDLE_ACK_VIO,
PMU_IDLE_ACK_MSCH0,
PMU_IDLE_ACK_MSCH1,
PMU_IDLE_ACK_ALIVE,
PMU_IDLE_ACK_PMU,
PMU_IDLE_ACK_EDP,
PMU_IDLE_ACK_GMAC,
PMU_IDLE_ACK_EMMC,
PMU_IDLE_ACK_CENTER1,
PMU_IDLE_ACK_PMUM0,
PMU_IDLE_ACK_GIC,
PMU_IDLE_ACK_SD,
PMU_IDLE_ACK_SDIOAUDIO,
};
enum pmu_cci500_con {
PMU_PREQ_CCI500_CFG_SW = 0,
PMU_CLR_PREQ_CCI500_HW,
PMU_PSTATE_CCI500_0,
PMU_PSTATE_CCI500_1,
PMU_PSTATE_CCI500_2,
PMU_QREQ_CCI500_CFG_SW,
PMU_CLR_QREQ_CCI500_HW,
PMU_QGATING_CCI500_CFG,
PMU_PREQ_CCI500_CFG_SW_WMSK = 16,
PMU_CLR_PREQ_CCI500_HW_WMSK,
PMU_PSTATE_CCI500_0_WMSK,
PMU_PSTATE_CCI500_1_WMSK,
PMU_PSTATE_CCI500_2_WMSK,
PMU_QREQ_CCI500_CFG_SW_WMSK,
PMU_CLR_QREQ_CCI500_HW_WMSK,
PMU_QGATING_CCI500_CFG_WMSK,
};
enum pmu_adb400_con {
PMU_PWRDWN_REQ_CXCS_SW = 0,
PMU_PWRDWN_REQ_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_B_SW,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW,
PMU_CLR_CXCS_HW = 8,
PMU_CLR_CORE_L_HW,
PMU_CLR_CORE_L_2GIC_HW,
PMU_CLR_GIC2_CORE_L_HW,
PMU_CLR_CORE_B_HW,
PMU_CLR_CORE_B_2GIC_HW,
PMU_CLR_GIC2_CORE_B_HW,
PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16,
PMU_PWRDWN_REQ_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK,
PMU_CLR_CXCS_HW_WMSK = 24,
PMU_CLR_CORE_L_HW_WMSK,
PMU_CLR_CORE_L_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_L_HW_WMSK,
PMU_CLR_CORE_B_HW_WMSK,
PMU_CLR_CORE_B_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_B_HW_WMSK,
};
enum pmu_adb400_st {
PMU_PWRDWN_REQ_CXCS_SW_ST = 0,
PMU_PWRDWN_REQ_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_B_SW_ST,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST,
PMU_CLR_CXCS_HW_ST = 8,
PMU_CLR_CORE_L_HW_ST,
PMU_CLR_CORE_L_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_L_HW_ST,
PMU_CLR_CORE_B_HW_ST,
PMU_CLR_CORE_B_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_B_HW_ST,
};
enum pmu_pwrdn_con1 {
PMU_VD_SCU_L_PWRDN_EN = 0,
PMU_VD_SCU_B_PWRDN_EN,
PMU_VD_CENTER_PWRDN_EN,
};
enum pmu_core_pwr_st {
L2_FLUSHDONE_CLUSTER_L = 0,
STANDBY_BY_WFIL2_CLUSTER_L,
L2_FLUSHDONE_CLUSTER_B = 10,
STANDBY_BY_WFIL2_CLUSTER_B,
};
/* Specific features required */
#define AP_PWROFF 0x0a
......
plat/rockchip/rk3399/drivers/secure/secure.c 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <assert.h>
#include <debug.h>
#include <delay_timer.h>
#include <plat_private.h>
#include <secure.h>
#include <soc.h>
static void sgrf_ddr_rgn_global_bypass(uint32_t bypass)
{
if (bypass)
/* set bypass (non-secure regions) for whole ddr regions */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
SGRF_DDR_RGN_BYPS);
else
/* cancel bypass for whole ddr regions */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
SGRF_DDR_RGN_NO_BYPS);
}
/**
* There are 8 + 1 regions for DDR secure control:
* DDR_RGN_0 ~ DDR_RGN_7: Per DDR_RGNs grain size is 1MB
* DDR_RGN_X - the memories of exclude DDR_RGN_0 ~ DDR_RGN_7
*
* DDR_RGN_0 - start address of the RGN0
* DDR_RGN_8 - end address of the RGN0
* DDR_RGN_1 - start address of the RGN1
* DDR_RGN_9 - end address of the RGN1
* ...
* DDR_RGN_7 - start address of the RGN7
* DDR_RGN_15 - end address of the RGN7
* DDR_RGN_16 - bit 0 ~ 7 is bitmap for RGN0~7 secure,0: disable, 1: enable
* bit 8 is setting for RGNx, the rest of the memory and region
* which excludes RGN0~7, 0: disable, 1: enable
* bit 9, the global secure configuration via bypass, 0: disable
* bypass, 1: enable bypass
*
* @rgn - the DDR regions 0 ~ 7 which are can be configured.
* The @st_mb and @ed_mb indicate the start and end addresses for which to set
* the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
* address range 0x0 ~ 0xfffff is secure.
*
* For example, if we would like to set the range [0, 32MB) is security via
* DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
*/
static void sgrf_ddr_rgn_config(uint32_t rgn,
uintptr_t st, uintptr_t ed)
{
uintptr_t st_mb, ed_mb;
assert(rgn <= 7);
assert(st < ed);
/* check aligned 1MB */
assert(st % SIZE_M(1) == 0);
assert(ed % SIZE_M(1) == 0);
st_mb = st / SIZE_M(1);
ed_mb = ed / SIZE_M(1);
/* set ddr region addr start */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn),
BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_0_16_WMSK, 0));
/* set ddr region addr end */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8),
BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_0_16_WMSK, 0));
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
BIT_WITH_WMSK(rgn));
}
void secure_watchdog_disable(void)
{
/**
* Disable CA53 and CM0 wdt pclk
* BIT[8]: ca53 wdt pclk, 0: enable 1: disable
* BIT[10]: cm0 wdt pclk, 0: enable 1: disable
*/
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
BIT_WITH_WMSK(PCLK_WDT_CA53_GATE_SHIFT) |
BIT_WITH_WMSK(PCLK_WDT_CM0_GATE_SHIFT));
}
void secure_watchdog_enable(void)
{
/**
* Enable CA53 and CM0 wdt pclk
* BIT[8]: ca53 wdt pclk, 0: enable 1: disable
* BIT[10]: cm0 wdt pclk, 0: enable 1: disable
*/
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) |
WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT));
}
void secure_timer_init(void)
{
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
/* auto reload & enable the timer */
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
TIMER_EN | TIMER_FMODE);
}
void secure_sgrf_init(void)
{
/* security config for master */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5),
REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6),
REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7),
REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
/* security config for slave */
mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0),
SGRF_PMU_SLV_S_CFGED |
SGRF_PMU_SLV_CRYPTO1_NS);
mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1),
SGRF_SLV_S_WMSK | SGRF_PMUSRAM_S);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4),
SGRF_SLV_S_WMSK | SGRF_INTSRAM_S);
}
void secure_sgrf_ddr_rgn_init(void)
{
sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE);
sgrf_ddr_rgn_global_bypass(0);
}
plat/rockchip/rk3399/drivers/secure/secure.h 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__
#define __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__
/**************************************************
* sgrf reg, offset
**************************************************/
#define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4)
#define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4)
#define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4)
#define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\
(n < 8 ? SGRF_SOC_CON3_7(n) :\
SGRF_SOC_CON8_15(n)))
#define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4)
#define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4)
#define SGRF_DDRRGN_CON0_16(n) ((n) * 4)
#define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4)
/* All of master in ns */
#define SGRF_SOC_ALLMST_NS 0xffff
/* security config for slave */
#define SGRF_SLV_S_WMSK 0xffff0000
#define SGRF_SLV_S_ALL_NS 0x0
/* security config pmu slave ip */
/* All of slaves is ns */
#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0)
/* slaves secure attr is configed */
#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0)
#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1)
#define SGRF_PMUSRAM_S BIT(8)
#define SGRF_INTSRAM_S BIT(13)
/* ddr region */
#define SGRF_DDR_RGN_0_16_WMSK 0x0fff /* DDR RGN 0~16 size mask */
#define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */
#define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */
/* All security of the DDR RGNs are bypass */
#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9)
/* All security of the DDR RGNs are not bypass */
#define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(9)
/* The MST access the ddr rgn n with secure attribution */
#define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n))
/* bits[16:8]*/
#define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8)
#define SGRF_PMU_CON0 0x0c100
#define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4)
/**************************************************
* secure timer
**************************************************/
/* chanal0~5 */
#define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
/* chanal6~11 */
#define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n))
/* low 32 bits */
#define TIMER_END_COUNT0 0x00
/* high 32 bits */
#define TIMER_END_COUNT1 0x04
#define TIMER_CURRENT_VALUE0 0x08
#define TIMER_CURRENT_VALUE1 0x0C
/* low 32 bits */
#define TIMER_INIT_COUNT0 0x10
/* high 32 bits */
#define TIMER_INIT_COUNT1 0x14
#define TIMER_INTSTATUS 0x18
#define TIMER_CONTROL_REG 0x1c
#define TIMER_EN 0x1
#define TIMER_FMODE (0x0 << 1)
#define TIMER_RMODE (0x1 << 1)
/**************************************************
* secure WDT
**************************************************/
#define PCLK_WDT_CA53_GATE_SHIFT 8
#define PCLK_WDT_CM0_GATE_SHIFT 10
/* export secure operating APIs */
void secure_watchdog_disable(void);
void secure_watchdog_enable(void);
void secure_timer_init(void);
void secure_sgrf_init(void);
void secure_sgrf_ddr_rgn_init(void);
#endif /* __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ */
plat/rockchip/rk3399/drivers/soc/soc.c
View file @ d6845d3d
......@@ -29,19 +29,22 @@
*/
#include <arch_helpers.h>
#include <assert.h>
#include <debug.h>
#include <delay_timer.h>
#include <dfs.h>
#include <dram.h>
#include <mmio.h>
#include <m0_ctl.h>
#include <platform_def.h>
#include <plat_private.h>
#include <dram.h>
#include <rk3399_def.h>
#include <rk3399m0.h>
#include <secure.h>
#include <soc.h>
/* Table of regions to map using the MMU. */
const mmap_region_t plat_rk_mmap[] = {
MAP_REGION_FLAT(RK3399_DEV_RNG0_BASE, RK3399_DEV_RNG0_SIZE,
MAP_REGION_FLAT(DEV_RNG0_BASE, DEV_RNG0_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
MT_MEMORY | MT_RW | MT_SECURE),
......@@ -61,158 +64,8 @@ const unsigned char rockchip_power_domain_tree_desc[] = {
PLATFORM_CLUSTER1_CORE_COUNT
};
void secure_timer_init(void)
{
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
/* auto reload & enable the timer */
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
TIMER_EN | TIMER_FMODE);
}
void sgrf_init(void)
{
/* security config for master */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5),
SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6),
SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7),
SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS);
/* security config for slave */
mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0),
SGRF_PMU_SLV_S_CFGED |
SGRF_PMU_SLV_CRYPTO1_NS);
mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1),
SGRF_PMU_SLV_CON1_CFG);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
/* security config for ddr memery */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
SGRF_DDR_RGN_BYPS);
}
static void dma_secure_cfg(uint32_t secure)
{
if (secure) {
/* rgn0 secure for dmac0 and dmac1 */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22),
SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */
SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */
);
/* set dmac0 boot, under secure state */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10),
SGRF_DMAC_CFG_S);
/* dmac0 soft reset */
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC0_RST);
udelay(5);
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC0_RST_RLS);
/* set dmac1 boot, under secure state */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15),
SGRF_DMAC_CFG_S);
/* dmac1 soft reset */
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC1_RST);
udelay(5);
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC1_RST_RLS);
} else {
/* rgn non-secure for dmac0 and dmac1 */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22),
DMAC1_RGN_NS | DMAC0_RGN_NS);
/* set dmac0 boot, under non-secure state */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8),
DMAC0_BOOT_CFG_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9),
DMAC0_BOOT_PERIPH_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10),
DMAC0_BOOT_ADDR_NS);
/* dmac0 soft reset */
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC0_RST);
udelay(5);
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC0_RST_RLS);
/* set dmac1 boot, under non-secure state */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11),
DMAC1_BOOT_CFG_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12),
DMAC1_BOOT_PERIPH_L_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13),
DMAC1_BOOT_ADDR_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14),
DMAC1_BOOT_PERIPH_H_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15),
DMAC1_BOOT_IRQ_NS);
/* dmac1 soft reset */
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC1_RST);
udelay(5);
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC1_RST_RLS);
}
}
/* pll suspend */
struct deepsleep_data_s slp_data;
void secure_watchdog_disable(void)
{
slp_data.sgrf_con[3] = mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(3));
/* disable CA53 wdt pclk */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
BITS_WITH_WMASK(WDT_CA53_DIS, WDT_CA53_1BIT_MASK,
PCLK_WDT_CA53_GATE_SHIFT));
/* disable CM0 wdt pclk */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
BITS_WITH_WMASK(WDT_CM0_DIS, WDT_CM0_1BIT_MASK,
PCLK_WDT_CM0_GATE_SHIFT));
}
void secure_watchdog_restore(void)
{
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
slp_data.sgrf_con[3] |
WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) |
WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT));
}
/* sleep data for pll suspend */
static struct deepsleep_data_s slp_data;
static void set_pll_slow_mode(uint32_t pll_id)
{
......@@ -455,27 +308,14 @@ void __dead2 soc_global_soft_reset(void)
;
}
static void soc_m0_init(void)
{
/* secure config for pmu M0 */
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7));
/* set the execute address for M0 */
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff,
0xffff, 0));
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf,
0xf, 0));
}
void plat_rockchip_soc_init(void)
{
secure_timer_init();
dma_secure_cfg(0);
sgrf_init();
secure_sgrf_init();
secure_sgrf_ddr_rgn_init();
soc_global_soft_reset_init();
plat_rockchip_gpio_init();
soc_m0_init();
m0_init();
dram_init();
dram_dfs_init();
}
plat/rockchip/rk3399/drivers/soc/soc.h
View file @ d6845d3d
......@@ -75,7 +75,6 @@
#define REG_SOC_WMSK 0xffff0000
#define CLK_GATE_MASK 0x01
#define SGRF_SOC_COUNT 0x17
#define PMUCRU_GATE_COUNT 0x03
#define CRU_GATE_COUNT 0x23
#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4)
......@@ -108,13 +107,20 @@ enum glb_sft_reset {
PMU_RST_NOT_BY_SFT = BIT(3),
};
struct pll_div {
uint32_t mhz;
uint32_t refdiv;
uint32_t fbdiv;
uint32_t postdiv1;
uint32_t postdiv2;
uint32_t frac;
uint32_t freq;
};
struct deepsleep_data_s {
uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT];
uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT];
uint32_t cru_clksel_con[CRU_CLKSEL_COUNT];
uint32_t cru_gate_con[CRU_GATE_COUNT];
uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
uint32_t sgrf_con[SGRF_SOC_COUNT];
};
/**************************************************
......@@ -146,50 +152,6 @@ struct deepsleep_data_s {
#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000))
#define CYCL_32K_CNT_MS(ms) (ms * 32)
/**************************************************
* secure timer
**************************************************/
/* chanal0~5 */
#define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
/* chanal6~11 */
#define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n))
/* low 32 bits */
#define TIMER_END_COUNT0 0x00
/* high 32 bits */
#define TIMER_END_COUNT1 0x04
#define TIMER_CURRENT_VALUE0 0x08
#define TIMER_CURRENT_VALUE1 0x0C
/* low 32 bits */
#define TIMER_INIT_COUNT0 0x10
/* high 32 bits */
#define TIMER_INIT_COUNT1 0x14
#define TIMER_INTSTATUS 0x18
#define TIMER_CONTROL_REG 0x1c
#define TIMER_EN 0x1
#define TIMER_FMODE (0x0 << 1)
#define TIMER_RMODE (0x1 << 1)
/**************************************************
* secure WDT
**************************************************/
#define WDT_CM0_EN 0x0
#define WDT_CM0_DIS 0x1
#define WDT_CA53_EN 0x0
#define WDT_CA53_DIS 0x1
#define PCLK_WDT_CA53_GATE_SHIFT 8
#define PCLK_WDT_CM0_GATE_SHIFT 10
#define WDT_CA53_1BIT_MASK 0x1
#define WDT_CM0_1BIT_MASK 0x1
/**************************************************
* cru reg, offset
**************************************************/
......@@ -231,63 +193,6 @@ struct deepsleep_data_s {
#define PCLK_GPIO0_GATE_SHIFT 3
#define PCLK_GPIO1_GATE_SHIFT 4
/**************************************************
* sgrf reg, offset
**************************************************/
#define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4)
#define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4)
#define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4)
#define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4)
#define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4)
#define SGRF_DDRRGN_CON0_16(n) ((n) * 4)
#define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4)
/* security config for master */
#define SGRF_SOC_CON_WMSK 0xffff0000
/* All of master in ns */
#define SGRF_SOC_ALLMST_NS 0xffff
/* security config for slave */
#define SGRF_SLV_S_WMSK 0xffff0000
#define SGRF_SLV_S_ALL_NS 0x0
/* security config pmu slave ip */
/* All of slaves is ns */
#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0)
/* slaves secure attr is configed */
#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0)
#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1)
#define SGRF_PMUSRAM_S BIT(8)
#define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \
SGRF_PMUSRAM_S)
/* ddr region */
#define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */
#define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */
#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */
/* The MST access the ddr rgn n with secure attribution */
#define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n))
/* bits[16:8]*/
#define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8)
/* dmac to periph s or ns*/
#define SGRF_DMAC_CFG_S 0xffff0000
#define DMAC1_RGN_NS 0xff000000
#define DMAC0_RGN_NS 0x00ff0000
#define DMAC0_BOOT_CFG_NS 0xfffffff8
#define DMAC0_BOOT_PERIPH_NS 0xffff0fff
#define DMAC0_BOOT_ADDR_NS 0xffff0000
#define DMAC1_BOOT_CFG_NS 0xffff0008
#define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff
#define DMAC1_BOOT_ADDR_NS 0xffff0000
#define DMAC1_BOOT_PERIPH_H_NS 0xffffffff
#define DMAC1_BOOT_IRQ_NS 0xffffffff
#define CPU_BOOT_ADDR_WMASK 0xffff0000
#define CPU_BOOT_ADDR_ALIGN 16
......@@ -312,17 +217,13 @@ struct deepsleep_data_s {
#define GRF_DDRC0_CON1 0xe384
#define GRF_DDRC1_CON0 0xe388
#define GRF_DDRC1_CON1 0xe38c
#define GRF_SOC_CON_BASE 0xe200
#define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4)
#define PMUCRU_CLKSEL_CON0 0x0080
#define PMUCRU_CLKGATE_CON2 0x0108
#define PMUCRU_SOFTRST_CON0 0x0110
#define PMUCRU_GATEDIS_CON0 0x0130
#define SGRF_SOC_CON6 0x0e018
#define SGRF_PERILP_CON0 0x08100
#define SGRF_PERILP_CON(n) (SGRF_PERILP_CON0 + (n) * 4)
#define SGRF_PMU_CON0 0x0c100
#define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4)
#define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4)
/*
......@@ -346,10 +247,8 @@ static inline void pmu_sgrf_rst_hld(void)
CRU_PMU_SGRF_RST_HOLD);
}
/* funciton*/
/* export related and operating SoC APIs */
void __dead2 soc_global_soft_reset(void);
void secure_watchdog_disable();
void secure_watchdog_restore();
void disable_dvfs_plls(void);
void disable_nodvfs_plls(void);
void enable_dvfs_plls(void);
......@@ -360,5 +259,5 @@ void restore_dpll(void);
void clk_gate_con_save(void);
void clk_gate_con_disable(void);
void clk_gate_con_restore(void);
void sgrf_init(void);
#endif /* __SOC_H__ */
plat/rockchip/rk3399/include/addressmap.h 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__
#define __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__
#include <addressmap_shared.h>
/* Registers base address */
#define MMIO_BASE 0xF8000000
/* Aggregate of all devices in the first GB */
#define DEV_RNG0_BASE MMIO_BASE
#define DEV_RNG0_SIZE SIZE_M(125)
#endif /* __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__ */
plat/rockchip/rk3399/include/platform_def.h
View file @ d6845d3d
......@@ -32,6 +32,7 @@
#define __PLATFORM_DEF_H__
#include <arch.h>
#include <bl31_param.h>
#include <common_def.h>
#include <rk3399_def.h>
......@@ -88,22 +89,6 @@
*/
#define PLAT_MAX_OFF_STATE 2
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
/* TF txet, ro, rw, Size: 512KB */
#define TZRAM_BASE (0x0)
#define TZRAM_SIZE (0x80000)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
/*
* Put BL3-1 at the top of the Trusted RAM
*/
#define BL31_BASE (TZRAM_BASE + 0x10000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
......@@ -138,7 +123,7 @@
#define PLAT_RK_G1S_IRQS RK3399_G1S_IRQS
#define PLAT_RK_G0_IRQS RK3399_G0_IRQS
#define PLAT_RK_UART_BASE RK3399_UART2_BASE
#define PLAT_RK_UART_BASE UART2_BASE
#define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK
#define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE
......
plat/rockchip/rk3399/include/shared/addressmap_shared.h 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__
#define __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__
#define SIZE_K(n) ((n) * 1024)
#define SIZE_M(n) ((n) * 1024 * 1024)
/*
* The parts of the shared defined registers address with AP and M0,
* let's note and mark the previous defines like this:
*/
#define GIC500_BASE (MMIO_BASE + 0x06E00000)
#define UART0_BASE (MMIO_BASE + 0x07180000)
#define UART1_BASE (MMIO_BASE + 0x07190000)
#define UART2_BASE (MMIO_BASE + 0x071A0000)
#define UART3_BASE (MMIO_BASE + 0x071B0000)
#define PMU_BASE (MMIO_BASE + 0x07310000)
#define PMUGRF_BASE (MMIO_BASE + 0x07320000)
#define SGRF_BASE (MMIO_BASE + 0x07330000)
#define PMUSRAM_BASE (MMIO_BASE + 0x073B0000)
#define PWM_BASE (MMIO_BASE + 0x07420000)
#define CIC_BASE (MMIO_BASE + 0x07620000)
#define PD_BUS0_BASE (MMIO_BASE + 0x07650000)
#define DCF_BASE (MMIO_BASE + 0x076A0000)
#define GPIO0_BASE (MMIO_BASE + 0x07720000)
#define GPIO1_BASE (MMIO_BASE + 0x07730000)
#define PMUCRU_BASE (MMIO_BASE + 0x07750000)
#define CRU_BASE (MMIO_BASE + 0x07760000)
#define GRF_BASE (MMIO_BASE + 0x07770000)
#define GPIO2_BASE (MMIO_BASE + 0x07780000)
#define GPIO3_BASE (MMIO_BASE + 0x07788000)
#define GPIO4_BASE (MMIO_BASE + 0x07790000)
#define STIME_BASE (MMIO_BASE + 0x07860000)
#define SRAM_BASE (MMIO_BASE + 0x078C0000)
#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x07A50000)
#define DDRC0_BASE (MMIO_BASE + 0x07A80000)
#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x07A84000)
#define DDRC1_BASE (MMIO_BASE + 0x07A88000)
#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x07A8C000)
#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x07A90000)
#define CCI500_BASE (MMIO_BASE + 0x07B00000)
#define COLD_BOOT_BASE (MMIO_BASE + 0x07FF0000)
/* Registers size */
#define GIC500_SIZE SIZE_M(2)
#define UART0_SIZE SIZE_K(64)
#define UART1_SIZE SIZE_K(64)
#define UART2_SIZE SIZE_K(64)
#define UART3_SIZE SIZE_K(64)
#define PMU_SIZE SIZE_K(64)
#define PMUGRF_SIZE SIZE_K(64)
#define SGRF_SIZE SIZE_K(64)
#define PMUSRAM_SIZE SIZE_K(64)
#define PMUSRAM_RSIZE SIZE_K(8)
#define PWM_SIZE SIZE_K(64)
#define CIC_SIZE SIZE_K(4)
#define DCF_SIZE SIZE_K(4)
#define GPIO0_SIZE SIZE_K(64)
#define GPIO1_SIZE SIZE_K(64)
#define PMUCRU_SIZE SIZE_K(64)
#define CRU_SIZE SIZE_K(64)
#define GRF_SIZE SIZE_K(64)
#define GPIO2_SIZE SIZE_K(32)
#define GPIO3_SIZE SIZE_K(32)
#define GPIO4_SIZE SIZE_K(32)
#define STIME_SIZE SIZE_K(64)
#define SRAM_SIZE SIZE_K(192)
#define SERVICE_NOC_0_SIZE SIZE_K(192)
#define DDRC0_SIZE SIZE_K(32)
#define SERVICE_NOC_1_SIZE SIZE_K(16)
#define DDRC1_SIZE SIZE_K(32)
#define SERVICE_NOC_2_SIZE SIZE_K(16)
#define SERVICE_NOC_3_SIZE SIZE_K(448)
#define CCI500_SIZE SIZE_M(1)
#define PD_BUS0_SIZE SIZE_K(448)
/* DDR Registers address */
#define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000)
#define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4)
#define PI_OFFSET 0x800
#define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET)
#define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4)
#define PHY_OFFSET 0x2000
#define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET)
#define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4)
#define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000)
#endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ */
plat/rockchip/rk3399/include/shared/bl31_param.h 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLAT_ROCKCHIP_RK3399_INCLUDE_SHARED_BL31_PARAM_H__
#define __PLAT_ROCKCHIP_RK3399_INCLUDE_SHARED_BL31_PARAM_H__
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
/* TF text, ro, rw, Size: 1MB */
#define TZRAM_BASE (0x0)
#define TZRAM_SIZE (0x100000)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
/*
* Put BL3-1 at the top of the Trusted RAM
*/
#define BL31_BASE (TZRAM_BASE + 0x1000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
#endif /*__PLAT_ROCKCHIP_RK3399_INCLUDE_SHARED_BL31_PARAM_H__*/
plat/rockchip/rk3399/include/shared/dram_regs.h 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DRAM_REGS_H__
#define __DRAM_REGS_H__
#define CTL_REG_NUM 332
#define PHY_REG_NUM 959
#define PI_REG_NUM 200
#define MSCH_ID_COREID 0x0
#define MSCH_ID_REVISIONID 0x4
#define MSCH_DEVICECONF 0x8
#define MSCH_DEVICESIZE 0xc
#define MSCH_DDRTIMINGA0 0x10
#define MSCH_DDRTIMINGB0 0x14
#define MSCH_DDRTIMINGC0 0x18
#define MSCH_DEVTODEV0 0x1c
#define MSCH_DDRMODE 0x110
#define MSCH_AGINGX0 0x1000
#define CIC_CTRL0 0x0
#define CIC_CTRL1 0x4
#define CIC_IDLE_TH 0x8
#define CIC_CG_WAIT_TH 0xc
#define CIC_STATUS0 0x10
#define CIC_STATUS1 0x14
#define CIC_CTRL2 0x18
#define CIC_CTRL3 0x1c
#define CIC_CTRL4 0x20
/* DENALI_CTL_00 */
#define START 1
/* DENALI_CTL_68 */
#define PWRUP_SREFRESH_EXIT (1 << 16)
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
#define PHY_DRV_ODT_Hi_Z 0x0
#define PHY_DRV_ODT_240 0x1
#define PHY_DRV_ODT_120 0x8
#define PHY_DRV_ODT_80 0x9
#define PHY_DRV_ODT_60 0xc
#define PHY_DRV_ODT_48 0xd
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
/*
* sys_reg bitfield struct
* [31] row_3_4_ch1
* [30] row_3_4_ch0
* [29:28] chinfo
* [27] rank_ch1
* [26:25] col_ch1
* [24] bk_ch1
* [23:22] cs0_row_ch1
* [21:20] cs1_row_ch1
* [19:18] bw_ch1
* [17:16] dbw_ch1;
* [15:13] ddrtype
* [12] channelnum
* [11] rank_ch0
* [10:9] col_ch0
* [8] bk_ch0
* [7:6] cs0_row_ch0
* [5:4] cs1_row_ch0
* [3:2] bw_ch0
* [1:0] dbw_ch0
*/
#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1)
#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
#define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1)
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7)
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1))
#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16))
#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16))
#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16))
#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16))
#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16))
#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16))
#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16))
#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3))
#define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \
(0x1f<<(10+16))|((n)<<10))
#endif /* __DRAM_REGS_H__ */
plat/rockchip/rk3399/include/shared/m0_param.h 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __M0_PARAM_H__
#define __M0_PARAM_H__
#ifndef __LINKER__
enum {
M0_FUNC_SUSPEND = 0,
M0_FUNC_DRAM = 1,
};
#endif /* __LINKER__ */
#define PARAM_ADDR 0xc0
#define PARAM_M0_FUNC 0x00
#define PARAM_DRAM_FREQ 0x04
#define PARAM_DPLL_CON0 0x08
#define PARAM_DPLL_CON1 0x0c
#define PARAM_DPLL_CON2 0x10
#define PARAM_DPLL_CON3 0x14
#define PARAM_DPLL_CON4 0x18
#define PARAM_DPLL_CON5 0x1c
#define PARAM_FREQ_SELECT 0x20
#define PARAM_M0_DONE 0x24
#define PARAM_M0_SIZE 0x28
#define M0_DONE_FLAG 0xf59ec39a
#endif /*__M0_PARAM_H__*/
plat/rockchip/rk3399/include/shared/misc_regs.h 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__
#define __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__
/* CRU */
#define CRU_DPLL_CON0 0x40
#define CRU_DPLL_CON1 0x44
#define CRU_DPLL_CON2 0x48
#define CRU_DPLL_CON3 0x4c
#define CRU_DPLL_CON4 0x50
#define CRU_DPLL_CON5 0x54
/* CRU_PLL_CON3 */
#define PLL_SLOW_MODE 0
#define PLL_NORMAL_MODE 1
#define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8))
#define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0))
/* PMU CRU */
#define PMU_CRU_GATEDIS_CON0 0x130
#endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ */
plat/rockchip/rk3399/include/shared/pmu_bits.h 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PMU_BITS_H__
#define __PMU_BITS_H__
enum pmu_powerdomain_id {
PD_CPUL0 = 0,
PD_CPUL1,
PD_CPUL2,
PD_CPUL3,
PD_CPUB0,
PD_CPUB1,
PD_SCUL,
PD_SCUB,
PD_TCPD0,
PD_TCPD1,
PD_CCI,
PD_PERILP,
PD_PERIHP,
PD_CENTER,
PD_VIO,
PD_GPU,
PD_VCODEC,
PD_VDU,
PD_RGA,
PD_IEP,
PD_VO,
PD_ISP0 = 22,
PD_ISP1,
PD_HDCP,
PD_GMAC,
PD_EMMC,
PD_USB3,
PD_EDP,
PD_GIC,
PD_SD,
PD_SDIOAUDIO,
PD_END
};
enum powerdomain_state {
PMU_POWER_ON = 0,
PMU_POWER_OFF,
};
enum pmu_bus_id {
BUS_ID_GPU = 0,
BUS_ID_PERILP,
BUS_ID_PERIHP,
BUS_ID_VCODEC,
BUS_ID_VDU,
BUS_ID_RGA,
BUS_ID_IEP,
BUS_ID_VOPB,
BUS_ID_VOPL,
BUS_ID_ISP0,
BUS_ID_ISP1,
BUS_ID_HDCP,
BUS_ID_USB3,
BUS_ID_PERILPM0,
BUS_ID_CENTER,
BUS_ID_CCIM0,
BUS_ID_CCIM1,
BUS_ID_VIO,
BUS_ID_MSCH0,
BUS_ID_MSCH1,
BUS_ID_ALIVE,
BUS_ID_PMU,
BUS_ID_EDP,
BUS_ID_GMAC,
BUS_ID_EMMC,
BUS_ID_CENTER1,
BUS_ID_PMUM0,
BUS_ID_GIC,
BUS_ID_SD,
BUS_ID_SDIOAUDIO,
};
enum pmu_bus_state {
BUS_ACTIVE,
BUS_IDLE,
};
/* pmu_cpuapm bit */
enum pmu_cores_pm_by_wfi {
core_pm_en = 0,
core_pm_int_wakeup_en,
core_pm_resv,
core_pm_sft_wakeup_en
};
enum pmu_wkup_cfg0 {
PMU_GPIO0A_POSE_WKUP_EN = 0,
PMU_GPIO0B_POSE_WKUP_EN = 8,
PMU_GPIO0C_POSE_WKUP_EN = 16,
PMU_GPIO0D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg1 {
PMU_GPIO0A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO0B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO0C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO0D_NEGEDGE_WKUP_EN = 24,
};
enum pmu_wkup_cfg2 {
PMU_GPIO1A_POSE_WKUP_EN = 0,
PMU_GPIO1B_POSE_WKUP_EN = 7,
PMU_GPIO1C_POSE_WKUP_EN = 16,
PMU_GPIO1D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg3 {
PMU_GPIO1A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO1B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO1C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO1D_NEGEDGE_WKUP_EN = 24,
};
/* pmu_wkup_cfg4 */
enum pmu_wkup_cfg4 {
PMU_CLUSTER_L_WKUP_EN = 0,
PMU_CLUSTER_B_WKUP_EN,
PMU_GPIO_WKUP_EN,
PMU_SDIO_WKUP_EN,
PMU_SDMMC_WKUP_EN,
PMU_TIMER_WKUP_EN = 6,
PMU_USBDEV_WKUP_EN,
PMU_SFT_WKUP_EN,
PMU_M0_WDT_WKUP_EN,
PMU_TIMEOUT_WKUP_EN,
PMU_PWM_WKUP_EN,
PMU_PCIE_WKUP_EN = 13,
};
enum pmu_pwrdn_con {
PMU_A53_L0_PWRDWN_EN = 0,
PMU_A53_L1_PWRDWN_EN,
PMU_A53_L2_PWRDWN_EN,
PMU_A53_L3_PWRDWN_EN,
PMU_A72_B0_PWRDWN_EN,
PMU_A72_B1_PWRDWN_EN,
PMU_SCU_L_PWRDWN_EN,
PMU_SCU_B_PWRDWN_EN,
PMU_TCPD0_PWRDWN_EN,
PMU_TCPD1_PWRDWN_EN,
PMU_CCI_PWRDWN_EN,
PMU_PERILP_PWRDWN_EN,
PMU_PERIHP_PWRDWN_EN,
PMU_CENTER_PWRDWN_EN,
PMU_VIO_PWRDWN_EN,
PMU_GPU_PWRDWN_EN,
PMU_VCODEC_PWRDWN_EN,
PMU_VDU_PWRDWN_EN,
PMU_RGA_PWRDWN_EN,
PMU_IEP_PWRDWN_EN,
PMU_VO_PWRDWN_EN,
PMU_ISP0_PWRDWN_EN = 22,
PMU_ISP1_PWRDWN_EN,
PMU_HDCP_PWRDWN_EN,
PMU_GMAC_PWRDWN_EN,
PMU_EMMC_PWRDWN_EN,
PMU_USB3_PWRDWN_EN,
PMU_EDP_PWRDWN_EN,
PMU_GIC_PWRDWN_EN,
PMU_SD_PWRDWN_EN,
PMU_SDIOAUDIO_PWRDWN_EN,
};
enum pmu_pwrdn_st {
PMU_A53_L0_PWRDWN_ST = 0,
PMU_A53_L1_PWRDWN_ST,
PMU_A53_L2_PWRDWN_ST,
PMU_A53_L3_PWRDWN_ST,
PMU_A72_B0_PWRDWN_ST,
PMU_A72_B1_PWRDWN_ST,
PMU_SCU_L_PWRDWN_ST,
PMU_SCU_B_PWRDWN_ST,
PMU_TCPD0_PWRDWN_ST,
PMU_TCPD1_PWRDWN_ST,
PMU_CCI_PWRDWN_ST,
PMU_PERILP_PWRDWN_ST,
PMU_PERIHP_PWRDWN_ST,
PMU_CENTER_PWRDWN_ST,
PMU_VIO_PWRDWN_ST,
PMU_GPU_PWRDWN_ST,
PMU_VCODEC_PWRDWN_ST,
PMU_VDU_PWRDWN_ST,
PMU_RGA_PWRDWN_ST,
PMU_IEP_PWRDWN_ST,
PMU_VO_PWRDWN_ST,
PMU_ISP0_PWRDWN_ST = 22,
PMU_ISP1_PWRDWN_ST,
PMU_HDCP_PWRDWN_ST,
PMU_GMAC_PWRDWN_ST,
PMU_EMMC_PWRDWN_ST,
PMU_USB3_PWRDWN_ST,
PMU_EDP_PWRDWN_ST,
PMU_GIC_PWRDWN_ST,
PMU_SD_PWRDWN_ST,
PMU_SDIOAUDIO_PWRDWN_ST,
};
enum pmu_pll_con {
PMU_PLL_PD_CFG = 0,
PMU_SFT_PLL_PD = 8,
};
enum pmu_pwermode_con {
PMU_PWR_MODE_EN = 0,
PMU_WKUP_RST_EN,
PMU_INPUT_CLAMP_EN,
PMU_OSC_DIS,
PMU_ALIVE_USE_LF,
PMU_PMU_USE_LF,
PMU_POWER_OFF_REQ_CFG,
PMU_CHIP_PD_EN,
PMU_PLL_PD_EN,
PMU_CPU0_PD_EN,
PMU_L2_FLUSH_EN,
PMU_L2_IDLE_EN,
PMU_SCU_PD_EN,
PMU_CCI_PD_EN,
PMU_PERILP_PD_EN,
PMU_CENTER_PD_EN,
PMU_SREF0_ENTER_EN,
PMU_DDRC0_GATING_EN,
PMU_DDRIO0_RET_EN,
PMU_DDRIO0_RET_DE_REQ,
PMU_SREF1_ENTER_EN,
PMU_DDRC1_GATING_EN,
PMU_DDRIO1_RET_EN,
PMU_DDRIO1_RET_DE_REQ,
PMU_CLK_CENTER_SRC_GATE_EN = 26,
PMU_CLK_PERILP_SRC_GATE_EN,
PMU_CLK_CORE_SRC_GATE_EN,
PMU_DDRIO_RET_HW_DE_REQ,
PMU_SLP_OUTPUT_CFG,
PMU_MAIN_CLUSTER,
};
enum pmu_sft_con {
PMU_WKUP_SFT = 0,
PMU_INPUT_CLAMP_CFG,
PMU_OSC_DIS_CFG,
PMU_PMU_LF_EN_CFG,
PMU_ALIVE_LF_EN_CFG,
PMU_24M_EN_CFG,
PMU_DBG_PWRUP_L0_CFG,
PMU_WKUP_SFT_M0,
PMU_DDRCTL0_C_SYSREQ_CFG,
PMU_DDR0_IO_RET_CFG,
PMU_DDRCTL1_C_SYSREQ_CFG = 12,
PMU_DDR1_IO_RET_CFG,
DBG_PWRUP_B0_CFG = 15,
DBG_NOPWERDWN_L0_EN,
DBG_NOPWERDWN_L1_EN,
DBG_NOPWERDWN_L2_EN,
DBG_NOPWERDWN_L3_EN,
DBG_PWRUP_REQ_L_EN = 20,
CLUSTER_L_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_L,
ACINACTM_CLUSTER_L_CFG,
DBG_NO_PWERDWN_B0_EN,
DBG_NO_PWERDWN_B1_EN,
DBG_PWRUP_REQ_B_EN = 28,
CLUSTER_B_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_B,
ACINACTM_CLUSTER_B_CFG,
};
enum pmu_int_con {
PMU_PMU_INT_EN = 0,
PMU_PWRMD_WKUP_INT_EN,
PMU_WKUP_GPIO0_NEG_INT_EN,
PMU_WKUP_GPIO0_POS_INT_EN,
PMU_WKUP_GPIO1_NEG_INT_EN,
PMU_WKUP_GPIO1_POS_INT_EN,
};
enum pmu_int_st {
PMU_PWRMD_WKUP_INT_ST = 1,
PMU_WKUP_GPIO0_NEG_INT_ST,
PMU_WKUP_GPIO0_POS_INT_ST,
PMU_WKUP_GPIO1_NEG_INT_ST,
PMU_WKUP_GPIO1_POS_INT_ST,
};
enum pmu_gpio0_pos_int_con {
PMU_GPIO0A_POS_INT_EN = 0,
PMU_GPIO0B_POS_INT_EN = 8,
PMU_GPIO0C_POS_INT_EN = 16,
PMU_GPIO0D_POS_INT_EN = 24,
};
enum pmu_gpio0_neg_int_con {
PMU_GPIO0A_NEG_INT_EN = 0,
PMU_GPIO0B_NEG_INT_EN = 8,
PMU_GPIO0C_NEG_INT_EN = 16,
PMU_GPIO0D_NEG_INT_EN = 24,
};
enum pmu_gpio1_pos_int_con {
PMU_GPIO1A_POS_INT_EN = 0,
PMU_GPIO1B_POS_INT_EN = 8,
PMU_GPIO1C_POS_INT_EN = 16,
PMU_GPIO1D_POS_INT_EN = 24,
};
enum pmu_gpio1_neg_int_con {
PMU_GPIO1A_NEG_INT_EN = 0,
PMU_GPIO1B_NEG_INT_EN = 8,
PMU_GPIO1C_NEG_INT_EN = 16,
PMU_GPIO1D_NEG_INT_EN = 24,
};
enum pmu_gpio0_pos_int_st {
PMU_GPIO0A_POS_INT_ST = 0,
PMU_GPIO0B_POS_INT_ST = 8,
PMU_GPIO0C_POS_INT_ST = 16,
PMU_GPIO0D_POS_INT_ST = 24,
};
enum pmu_gpio0_neg_int_st {
PMU_GPIO0A_NEG_INT_ST = 0,
PMU_GPIO0B_NEG_INT_ST = 8,
PMU_GPIO0C_NEG_INT_ST = 16,
PMU_GPIO0D_NEG_INT_ST = 24,
};
enum pmu_gpio1_pos_int_st {
PMU_GPIO1A_POS_INT_ST = 0,
PMU_GPIO1B_POS_INT_ST = 8,
PMU_GPIO1C_POS_INT_ST = 16,
PMU_GPIO1D_POS_INT_ST = 24,
};
enum pmu_gpio1_neg_int_st {
PMU_GPIO1A_NEG_INT_ST = 0,
PMU_GPIO1B_NEG_INT_ST = 8,
PMU_GPIO1C_NEG_INT_ST = 16,
PMU_GPIO1D_NEG_INT_ST = 24,
};
/* pmu power down configure register 0x0050 */
enum pmu_pwrdn_inten {
PMU_A53_L0_PWR_SWITCH_INT_EN = 0,
PMU_A53_L1_PWR_SWITCH_INT_EN,
PMU_A53_L2_PWR_SWITCH_INT_EN,
PMU_A53_L3_PWR_SWITCH_INT_EN,
PMU_A72_B0_PWR_SWITCH_INT_EN,
PMU_A72_B1_PWR_SWITCH_INT_EN,
PMU_SCU_L_PWR_SWITCH_INT_EN,
PMU_SCU_B_PWR_SWITCH_INT_EN,
PMU_TCPD0_PWR_SWITCH_INT_EN,
PMU_TCPD1_PWR_SWITCH_INT_EN,
PMU_CCI_PWR_SWITCH_INT_EN,
PMU_PERILP_PWR_SWITCH_INT_EN,
PMU_PERIHP_PWR_SWITCH_INT_EN,
PMU_CENTER_PWR_SWITCH_INT_EN,
PMU_VIO_PWR_SWITCH_INT_EN,
PMU_GPU_PWR_SWITCH_INT_EN,
PMU_VCODEC_PWR_SWITCH_INT_EN,
PMU_VDU_PWR_SWITCH_INT_EN,
PMU_RGA_PWR_SWITCH_INT_EN,
PMU_IEP_PWR_SWITCH_INT_EN,
PMU_VO_PWR_SWITCH_INT_EN,
PMU_ISP0_PWR_SWITCH_INT_EN = 22,
PMU_ISP1_PWR_SWITCH_INT_EN,
PMU_HDCP_PWR_SWITCH_INT_EN,
PMU_GMAC_PWR_SWITCH_INT_EN,
PMU_EMMC_PWR_SWITCH_INT_EN,
PMU_USB3_PWR_SWITCH_INT_EN,
PMU_EDP_PWR_SWITCH_INT_EN,
PMU_GIC_PWR_SWITCH_INT_EN,
PMU_SD_PWR_SWITCH_INT_EN,
PMU_SDIOAUDIO_PWR_SWITCH_INT_EN,
};
enum pmu_wkup_status {
PMU_WKUP_BY_CLSTER_L_INT = 0,
PMU_WKUP_BY_CLSTER_b_INT,
PMU_WKUP_BY_GPIO_INT,
PMU_WKUP_BY_SDIO_DET,
PMU_WKUP_BY_SDMMC_DET,
PMU_WKUP_BY_TIMER = 6,
PMU_WKUP_BY_USBDEV_DET,
PMU_WKUP_BY_M0_SFT,
PMU_WKUP_BY_M0_WDT_INT,
PMU_WKUP_BY_TIMEOUT,
PMU_WKUP_BY_PWM,
PMU_WKUP_BY_PCIE = 13,
};
enum pmu_bus_clr {
PMU_CLR_GPU = 0,
PMU_CLR_PERILP,
PMU_CLR_PERIHP,
PMU_CLR_VCODEC,
PMU_CLR_VDU,
PMU_CLR_RGA,
PMU_CLR_IEP,
PMU_CLR_VOPB,
PMU_CLR_VOPL,
PMU_CLR_ISP0,
PMU_CLR_ISP1,
PMU_CLR_HDCP,
PMU_CLR_USB3,
PMU_CLR_PERILPM0,
PMU_CLR_CENTER,
PMU_CLR_CCIM1,
PMU_CLR_CCIM0,
PMU_CLR_VIO,
PMU_CLR_MSCH0,
PMU_CLR_MSCH1,
PMU_CLR_ALIVE,
PMU_CLR_PMU,
PMU_CLR_EDP,
PMU_CLR_GMAC,
PMU_CLR_EMMC,
PMU_CLR_CENTER1,
PMU_CLR_PMUM0,
PMU_CLR_GIC,
PMU_CLR_SD,
PMU_CLR_SDIOAUDIO,
};
/* PMU bus idle request register */
enum pmu_bus_idle_req {
PMU_IDLE_REQ_GPU = 0,
PMU_IDLE_REQ_PERILP,
PMU_IDLE_REQ_PERIHP,
PMU_IDLE_REQ_VCODEC,
PMU_IDLE_REQ_VDU,
PMU_IDLE_REQ_RGA,
PMU_IDLE_REQ_IEP,
PMU_IDLE_REQ_VOPB,
PMU_IDLE_REQ_VOPL,
PMU_IDLE_REQ_ISP0,
PMU_IDLE_REQ_ISP1,
PMU_IDLE_REQ_HDCP,
PMU_IDLE_REQ_USB3,
PMU_IDLE_REQ_PERILPM0,
PMU_IDLE_REQ_CENTER,
PMU_IDLE_REQ_CCIM0,
PMU_IDLE_REQ_CCIM1,
PMU_IDLE_REQ_VIO,
PMU_IDLE_REQ_MSCH0,
PMU_IDLE_REQ_MSCH1,
PMU_IDLE_REQ_ALIVE,
PMU_IDLE_REQ_PMU,
PMU_IDLE_REQ_EDP,
PMU_IDLE_REQ_GMAC,
PMU_IDLE_REQ_EMMC,
PMU_IDLE_REQ_CENTER1,
PMU_IDLE_REQ_PMUM0,
PMU_IDLE_REQ_GIC,
PMU_IDLE_REQ_SD,
PMU_IDLE_REQ_SDIOAUDIO,
};
/* pmu bus idle status register */
enum pmu_bus_idle_st {
PMU_IDLE_ST_GPU = 0,
PMU_IDLE_ST_PERILP,
PMU_IDLE_ST_PERIHP,
PMU_IDLE_ST_VCODEC,
PMU_IDLE_ST_VDU,
PMU_IDLE_ST_RGA,
PMU_IDLE_ST_IEP,
PMU_IDLE_ST_VOPB,
PMU_IDLE_ST_VOPL,
PMU_IDLE_ST_ISP0,
PMU_IDLE_ST_ISP1,
PMU_IDLE_ST_HDCP,
PMU_IDLE_ST_USB3,
PMU_IDLE_ST_PERILPM0,
PMU_IDLE_ST_CENTER,
PMU_IDLE_ST_CCIM0,
PMU_IDLE_ST_CCIM1,
PMU_IDLE_ST_VIO,
PMU_IDLE_ST_MSCH0,
PMU_IDLE_ST_MSCH1,
PMU_IDLE_ST_ALIVE,
PMU_IDLE_ST_PMU,
PMU_IDLE_ST_EDP,
PMU_IDLE_ST_GMAC,
PMU_IDLE_ST_EMMC,
PMU_IDLE_ST_CENTER1,
PMU_IDLE_ST_PMUM0,
PMU_IDLE_ST_GIC,
PMU_IDLE_ST_SD,
PMU_IDLE_ST_SDIOAUDIO,
};
enum pmu_bus_idle_ack {
PMU_IDLE_ACK_GPU = 0,
PMU_IDLE_ACK_PERILP,
PMU_IDLE_ACK_PERIHP,
PMU_IDLE_ACK_VCODEC,
PMU_IDLE_ACK_VDU,
PMU_IDLE_ACK_RGA,
PMU_IDLE_ACK_IEP,
PMU_IDLE_ACK_VOPB,
PMU_IDLE_ACK_VOPL,
PMU_IDLE_ACK_ISP0,
PMU_IDLE_ACK_ISP1,
PMU_IDLE_ACK_HDCP,
PMU_IDLE_ACK_USB3,
PMU_IDLE_ACK_PERILPM0,
PMU_IDLE_ACK_CENTER,
PMU_IDLE_ACK_CCIM0,
PMU_IDLE_ACK_CCIM1,
PMU_IDLE_ACK_VIO,
PMU_IDLE_ACK_MSCH0,
PMU_IDLE_ACK_MSCH1,
PMU_IDLE_ACK_ALIVE,
PMU_IDLE_ACK_PMU,
PMU_IDLE_ACK_EDP,
PMU_IDLE_ACK_GMAC,
PMU_IDLE_ACK_EMMC,
PMU_IDLE_ACK_CENTER1,
PMU_IDLE_ACK_PMUM0,
PMU_IDLE_ACK_GIC,
PMU_IDLE_ACK_SD,
PMU_IDLE_ACK_SDIOAUDIO,
};
enum pmu_cci500_con {
PMU_PREQ_CCI500_CFG_SW = 0,
PMU_CLR_PREQ_CCI500_HW,
PMU_PSTATE_CCI500_0,
PMU_PSTATE_CCI500_1,
PMU_PSTATE_CCI500_2,
PMU_QREQ_CCI500_CFG_SW,
PMU_CLR_QREQ_CCI500_HW,
PMU_QGATING_CCI500_CFG,
PMU_PREQ_CCI500_CFG_SW_WMSK = 16,
PMU_CLR_PREQ_CCI500_HW_WMSK,
PMU_PSTATE_CCI500_0_WMSK,
PMU_PSTATE_CCI500_1_WMSK,
PMU_PSTATE_CCI500_2_WMSK,
PMU_QREQ_CCI500_CFG_SW_WMSK,
PMU_CLR_QREQ_CCI500_HW_WMSK,
PMU_QGATING_CCI500_CFG_WMSK,
};
enum pmu_adb400_con {
PMU_PWRDWN_REQ_CXCS_SW = 0,
PMU_PWRDWN_REQ_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_B_SW,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW,
PMU_CLR_CXCS_HW = 8,
PMU_CLR_CORE_L_HW,
PMU_CLR_CORE_L_2GIC_HW,
PMU_CLR_GIC2_CORE_L_HW,
PMU_CLR_CORE_B_HW,
PMU_CLR_CORE_B_2GIC_HW,
PMU_CLR_GIC2_CORE_B_HW,
PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16,
PMU_PWRDWN_REQ_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK,
PMU_CLR_CXCS_HW_WMSK = 24,
PMU_CLR_CORE_L_HW_WMSK,
PMU_CLR_CORE_L_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_L_HW_WMSK,
PMU_CLR_CORE_B_HW_WMSK,
PMU_CLR_CORE_B_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_B_HW_WMSK,
};
enum pmu_adb400_st {
PMU_PWRDWN_REQ_CXCS_SW_ST = 0,
PMU_PWRDWN_REQ_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_B_SW_ST,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST,
PMU_CLR_CXCS_HW_ST = 8,
PMU_CLR_CORE_L_HW_ST,
PMU_CLR_CORE_L_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_L_HW_ST,
PMU_CLR_CORE_B_HW_ST,
PMU_CLR_CORE_B_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_B_HW_ST,
};
enum pmu_pwrdn_con1 {
PMU_VD_SCU_L_PWRDN_EN = 0,
PMU_VD_SCU_B_PWRDN_EN,
PMU_VD_CENTER_PWRDN_EN,
};
enum pmu_core_pwr_st {
L2_FLUSHDONE_CLUSTER_L = 0,
STANDBY_BY_WFIL2_CLUSTER_L,
L2_FLUSHDONE_CLUSTER_B = 10,
STANDBY_BY_WFIL2_CLUSTER_B,
};
#endif /* __PMU_BITS_H__ */
plat/rockchip/rk3399/plat_sip_calls.c
View file @ d6845d3d
......@@ -44,24 +44,20 @@
#define DRAM_GET_RATE 0x05
#define DRAM_CLR_IRQ 0x06
#define DRAM_SET_PARAM 0x07
#define DRAM_SET_ODT_PD 0x08
uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id)
uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1,
uint64_t id, uint64_t arg2)
{
switch (id) {
case DRAM_INIT:
ddr_dfs_init();
break;
case DRAM_SET_RATE:
return ddr_set_rate((uint32_t)arg0);
case DRAM_ROUND_RATE:
return ddr_round_rate((uint32_t)arg0);
case DRAM_GET_RATE:
return ddr_get_rate();
case DRAM_CLR_IRQ:
clr_dcf_irq();
break;
case DRAM_SET_PARAM:
dts_timing_receive((uint32_t)arg0, (uint32_t)arg1);
case DRAM_SET_ODT_PD:
dram_set_odt_pd(arg0, arg1, arg2);
break;
default:
break;
......@@ -81,7 +77,7 @@ uint64_t rockchip_plat_sip_handler(uint32_t smc_fid,
{
switch (smc_fid) {
case RK_SIP_DDR_CFG:
SMC_RET1(handle, ddr_smc_handler(x1, x2, x3));
SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4));
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
SMC_RET1(handle, SMC_UNK);
......
plat/rockchip/rk3399/platform.mk
View file @ d6845d3d
......@@ -39,9 +39,11 @@ PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \
-I${RK_PLAT_SOC}/ \
-I${RK_PLAT_SOC}/drivers/pmu/ \
-I${RK_PLAT_SOC}/drivers/pwm/ \
-I${RK_PLAT_SOC}/drivers/secure/ \
-I${RK_PLAT_SOC}/drivers/soc/ \
-I${RK_PLAT_SOC}/drivers/dram/ \
-I${RK_PLAT_SOC}/include/ \
-I${RK_PLAT_SOC}/include/shared/ \
RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_main.c \
......@@ -77,12 +79,14 @@ BL31_SOURCES += ${RK_GIC_SOURCES}
${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c \
${RK_PLAT_SOC}/drivers/pmu/m0_ctl.c \
${RK_PLAT_SOC}/drivers/pwm/pwm.c \
${RK_PLAT_SOC}/drivers/secure/secure.c \
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/drivers/dram/dfs.c \
${RK_PLAT_SOC}/drivers/dram/suspend.c \
${RK_PLAT_SOC}/drivers/dram/dram.c \
${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c
${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c \
${RK_PLAT_SOC}/drivers/dram/suspend.c
ENABLE_PLAT_COMPAT := 0
......
plat/rockchip/rk3399/rk3399_def.h
View file @ d6845d3d
......@@ -31,122 +31,18 @@
#ifndef __PLAT_DEF_H__
#define __PLAT_DEF_H__
#include <addressmap.h>
#define RK3399_PRIMARY_CPU 0x0
/* Special value used to verify platform parameters from BL2 to BL3-1 */
#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
#define SIZE_K(n) ((n) * 1024)
#define SIZE_M(n) ((n) * 1024 * 1024)
/* Register base address and size */
#define MMIO_BASE 0xfe000000
#define GIC500_BASE (MMIO_BASE + 0xe00000)
#define GIC500_SIZE SIZE_M(2)
#define PMU_BASE (MMIO_BASE + 0x1310000)
#define PMU_SIZE SIZE_K(64)
#define PMUGRF_BASE (MMIO_BASE + 0x1320000)
#define PMUGRF_SIZE SIZE_K(64)
#define SGRF_BASE (MMIO_BASE + 0x1330000)
#define SGRF_SIZE SIZE_K(64)
#define PMUSRAM_BASE (MMIO_BASE + 0x13b0000)
#define PMUSRAM_SIZE SIZE_K(64)
#define PMUSRAM_RSIZE SIZE_K(8)
#define PWM_BASE (MMIO_BASE + 0x1420000)
#define PWM_SIZE SIZE_K(64)
#define CIC_BASE (MMIO_BASE + 0x1620000)
#define CIC_SIZE SIZE_K(4)
#define DCF_BASE (MMIO_BASE + 0x16a0000)
#define DCF_SIZE SIZE_K(4)
#define GPIO0_BASE (MMIO_BASE + 0x1720000)
#define GPIO0_SIZE SIZE_K(64)
#define GPIO1_BASE (MMIO_BASE + 0x1730000)
#define GPIO1_SIZE SIZE_K(64)
#define CRUS_BASE (MMIO_BASE + 0x1750000)
#define CRUS_SIZE SIZE_K(128)
#define GRF_BASE (MMIO_BASE + 0x1770000)
#define GRF_SIZE SIZE_K(64)
#define GPIO2_BASE (MMIO_BASE + 0x1780000)
#define GPIO2_SIZE SIZE_K(32)
#define GPIO3_BASE (MMIO_BASE + 0x1788000)
#define GPIO3_SIZE SIZE_K(32)
#define GPIO4_BASE (MMIO_BASE + 0x1790000)
#define GPIO4_SIZE SIZE_K(32)
#define STIME_BASE (MMIO_BASE + 0x1860000)
#define STIME_SIZE SIZE_K(64)
#define SRAM_BASE (MMIO_BASE + 0x18c0000)
#define SRAM_SIZE SIZE_K(192)
#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x1a50000)
#define NOC_0_SIZE SIZE_K(192)
#define DDRC0_BASE (MMIO_BASE + 0x1a80000)
#define DDRC0_SIZE SIZE_K(32)
#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x1a84000)
#define NOC_1_SIZE SIZE_K(16)
#define DDRC1_BASE (MMIO_BASE + 0x1a88000)
#define DDRC1_SIZE SIZE_K(32)
#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x1a8c000)
#define NOC_2_SIZE SIZE_K(16)
#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x1a90000)
#define NOC_3_SIZE SIZE_K(448)
#define CCI500_BASE (MMIO_BASE + 0x1b00000)
#define CCI500_SIZE SIZE_M(1)
#define DDR_PI_OFFSET 0x800
#define DDR_PHY_OFFSET 0x2000
#define DDRC0_PI_BASE (DDRC0_BASE + DDR_PI_OFFSET)
#define DDRC0_PHY_BASE (DDRC0_BASE + DDR_PHY_OFFSET)
#define DDRC1_PI_BASE (DDRC1_BASE + DDR_PI_OFFSET)
#define DDRC1_PHY_BASE (DDRC1_BASE + DDR_PHY_OFFSET)
/* Aggregate of all devices in the first GB */
#define RK3399_DEV_RNG0_BASE MMIO_BASE
#define RK3399_DEV_RNG0_SIZE 0x1d00000
/*
* include i2c pmu/audio, pwm0-3 rkpwm0-3 uart_dbg,mailbox scr
* 0xff650000 -0xff6c0000
*/
#define PD_BUS0_BASE (MMIO_BASE + 0x1650000)
#define PD_BUS0_SIZE SIZE_K(448)
#define PMUCRU_BASE (MMIO_BASE + 0x1750000)
#define CRU_BASE (MMIO_BASE + 0x1760000)
#define COLD_BOOT_BASE (MMIO_BASE + 0x1ff0000)
/**************************************************************************
* UART related constants
**************************************************************************/
#define RK3399_UART2_BASE (0xff1a0000)
#define RK3399_UART2_SIZE SIZE_K(64)
#define RK3399_BAUDRATE (115200)
#define RK3399_UART_CLOCK (24000000)
#define RK3399_BAUDRATE 115200
#define RK3399_UART_CLOCK 24000000
/******************************************************************************
* System counter frequency related constants
......@@ -176,6 +72,7 @@
#define ARM_IRQ_SEC_SGI_5 13
#define ARM_IRQ_SEC_SGI_6 14
#define ARM_IRQ_SEC_SGI_7 15
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
......
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