xilinx: versal: Wire silicon default setup

Add new option for serial and default clock setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I0ca7ad51637cdaa6bb891f22c53595d20da7236a

plat/xilinx/versal/include/versal_def.h

@@ -19,6 +19,7 @@
 
 /* List all supported platforms */
 #define VERSAL_PLATFORM_ID_versal_virt	1
+#define VERSAL_PLATFORM_ID_silicon	4
 
 #define VERSAL_PLATFORM_IS(con)	(VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM)
 
@@ -85,6 +86,11 @@
 # define VERSAL_UART_CLOCK	25000000
 # define VERSAL_UART_BAUDRATE	115200
 # define VERSAL_CPU_CLOCK	2720000
+#elif VERSAL_PLATFORM_IS(silicon)
+# define PLATFORM_NAME		"Versal Silicon"
+# define VERSAL_UART_CLOCK	100000000
+# define VERSAL_UART_BAUDRATE	115200
+# define VERSAL_CPU_CLOCK	100000000
 #endif
 
 /* Access control register defines */