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Unverified Commit d87d524e authored by danh-arm's avatar danh-arm Committed by GitHub
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Merge pull request #1466 from Yann-lms/stm32mp1 

Add STMicroelectronics STM32MP1 platform support
parents e16d459d efb3728d
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fdts/stm32mp157caa-pinctrl.dtsi 0 → 100644
View file @ d87d524e
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>
*/
#include "stm32mp157-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller {
compatible = "st,stm32mp157caa-pinctrl";
gpioa: gpio@50002000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@50003000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@50004000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@50005000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@50006000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@50007000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@50008000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@50009000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@5000a000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioj: gpio@5000b000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 144 16>;
};
gpiok: gpio@5000c000 {
status = "okay";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 160 8>;
};
};
pinctrl_z: pin-controller-z {
compatible = "st,stm32mp157caa-z-pinctrl";
gpioz: gpio@54004000 {
status = "okay";
ngpios = <8>;
gpio-ranges = <&pinctrl_z 0 400 8>;
};
};
};
};
include/drivers/st/stm32_gpio.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __PLAT_GPIO_H__
#define __PLAT_GPIO_H__
#include <utils_def.h>
#define STM32_GPIOA_BANK U(0x50002000)
#define STM32_GPIOZ_BANK U(0x54004000)
#define STM32_GPIO_BANK_OFFSET U(0x1000)
#define GPIO_MODE_OFFSET U(0x00)
#define GPIO_TYPE_OFFSET U(0x04)
#define GPIO_SPEED_OFFSET U(0x08)
#define GPIO_PUPD_OFFSET U(0x0C)
#define GPIO_BSRR_OFFSET U(0x18)
#define GPIO_AFRL_OFFSET U(0x20)
#define GPIO_AFRH_OFFSET U(0x24)
#define GPIO_ALT_LOWER_LIMIT U(0x08)
#define GPIO_BANK_A U(0x00)
#define GPIO_BANK_B U(0x01)
#define GPIO_BANK_C U(0x02)
#define GPIO_BANK_D U(0x03)
#define GPIO_BANK_E U(0x04)
#define GPIO_BANK_F U(0x05)
#define GPIO_BANK_G U(0x06)
#define GPIO_BANK_H U(0x07)
#define GPIO_BANK_I U(0x08)
#define GPIO_BANK_J U(0x09)
#define GPIO_BANK_K U(0x0A)
#define GPIO_BANK_Z U(0x19)
#define GPIO_PIN_0 U(0x00)
#define GPIO_PIN_1 U(0x01)
#define GPIO_PIN_2 U(0x02)
#define GPIO_PIN_3 U(0x03)
#define GPIO_PIN_4 U(0x04)
#define GPIO_PIN_5 U(0x05)
#define GPIO_PIN_6 U(0x06)
#define GPIO_PIN_7 U(0x07)
#define GPIO_PIN_8 U(0x08)
#define GPIO_PIN_9 U(0x09)
#define GPIO_PIN_10 U(0x0A)
#define GPIO_PIN_11 U(0x0B)
#define GPIO_PIN_12 U(0x0C)
#define GPIO_PIN_13 U(0x0D)
#define GPIO_PIN_14 U(0x0E)
#define GPIO_PIN_15 U(0x0F)
#define GPIO_PIN_MAX GPIO_PIN_15
#define GPIO_ALTERNATE_0 0x00
#define GPIO_ALTERNATE_1 0x01
#define GPIO_ALTERNATE_2 0x02
#define GPIO_ALTERNATE_3 0x03
#define GPIO_ALTERNATE_4 0x04
#define GPIO_ALTERNATE_5 0x05
#define GPIO_ALTERNATE_6 0x06
#define GPIO_ALTERNATE_7 0x07
#define GPIO_ALTERNATE_8 0x08
#define GPIO_ALTERNATE_9 0x09
#define GPIO_ALTERNATE_10 0x0A
#define GPIO_ALTERNATE_11 0x0B
#define GPIO_ALTERNATE_12 0x0C
#define GPIO_ALTERNATE_13 0x0D
#define GPIO_ALTERNATE_14 0x0E
#define GPIO_ALTERNATE_15 0x0F
#define GPIO_ALTERNATE_MASK U(0x0F)
#define GPIO_MODE_INPUT 0x00
#define GPIO_MODE_OUTPUT 0x01
#define GPIO_MODE_ALTERNATE 0x02
#define GPIO_MODE_ANALOG 0x03
#define GPIO_MODE_MASK U(0x03)
#define GPIO_OPEN_DRAIN U(0x10)
#define GPIO_SPEED_LOW 0x00
#define GPIO_SPEED_MEDIUM 0x01
#define GPIO_SPEED_FAST 0x02
#define GPIO_SPEED_HIGH 0x03
#define GPIO_SPEED_MASK U(0x03)
#define GPIO_NO_PULL 0x00
#define GPIO_PULL_UP 0x01
#define GPIO_PULL_DOWN 0x02
#define GPIO_PULL_MASK U(0x03)
#ifndef __ASSEMBLY__
#include <stdint.h>
void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
uint32_t pull, uint32_t alternate);
#endif /*__ASSEMBLY__*/
#endif /*__PLAT_GPIO_H__*/
include/drivers/st/stm32_i2c.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __STM32MP1_I2C_H
#define __STM32MP1_I2C_H
#include <stdint.h>
#include <utils_def.h>
/* Bit definition for I2C_CR1 register */
#define I2C_CR1_PE BIT(0)
#define I2C_CR1_TXIE BIT(1)
#define I2C_CR1_RXIE BIT(2)
#define I2C_CR1_ADDRIE BIT(3)
#define I2C_CR1_NACKIE BIT(4)
#define I2C_CR1_STOPIE BIT(5)
#define I2C_CR1_TCIE BIT(6)
#define I2C_CR1_ERRIE BIT(7)
#define I2C_CR1_DNF GENMASK(11, 8)
#define I2C_CR1_ANFOFF BIT(12)
#define I2C_CR1_SWRST BIT(13)
#define I2C_CR1_TXDMAEN BIT(14)
#define I2C_CR1_RXDMAEN BIT(15)
#define I2C_CR1_SBC BIT(16)
#define I2C_CR1_NOSTRETCH BIT(17)
#define I2C_CR1_WUPEN BIT(18)
#define I2C_CR1_GCEN BIT(19)
#define I2C_CR1_SMBHEN BIT(22)
#define I2C_CR1_SMBDEN BIT(21)
#define I2C_CR1_ALERTEN BIT(22)
#define I2C_CR1_PECEN BIT(23)
/* Bit definition for I2C_CR2 register */
#define I2C_CR2_SADD GENMASK(9, 0)
#define I2C_CR2_RD_WRN BIT(10)
#define I2C_CR2_RD_WRN_OFFSET 10U
#define I2C_CR2_ADD10 BIT(11)
#define I2C_CR2_HEAD10R BIT(12)
#define I2C_CR2_START BIT(13)
#define I2C_CR2_STOP BIT(14)
#define I2C_CR2_NACK BIT(15)
#define I2C_CR2_NBYTES GENMASK(23, 16)
#define I2C_CR2_NBYTES_OFFSET 16U
#define I2C_CR2_RELOAD BIT(24)
#define I2C_CR2_AUTOEND BIT(25)
#define I2C_CR2_PECBYTE BIT(26)
/* Bit definition for I2C_OAR1 register */
#define I2C_OAR1_OA1 GENMASK(9, 0)
#define I2C_OAR1_OA1MODE BIT(10)
#define I2C_OAR1_OA1EN BIT(15)
/* Bit definition for I2C_OAR2 register */
#define I2C_OAR2_OA2 GENMASK(7, 1)
#define I2C_OAR2_OA2MSK GENMASK(10, 8)
#define I2C_OAR2_OA2NOMASK 0
#define I2C_OAR2_OA2MASK01 BIT(8)
#define I2C_OAR2_OA2MASK02 BIT(9)
#define I2C_OAR2_OA2MASK03 GENMASK(9, 8)
#define I2C_OAR2_OA2MASK04 BIT(10)
#define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10))
#define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10))
#define I2C_OAR2_OA2MASK07 GENMASK(10, 8)
#define I2C_OAR2_OA2EN BIT(15)
/* Bit definition for I2C_TIMINGR register */
#define I2C_TIMINGR_SCLL GENMASK(7, 0)
#define I2C_TIMINGR_SCLH GENMASK(15, 8)
#define I2C_TIMINGR_SDADEL GENMASK(19, 16)
#define I2C_TIMINGR_SCLDEL GENMASK(23, 20)
#define I2C_TIMINGR_PRESC GENMASK(31, 28)
/* Bit definition for I2C_TIMEOUTR register */
#define I2C_TIMEOUTR_TIMEOUTA GENMASK(11, 0)
#define I2C_TIMEOUTR_TIDLE BIT(12)
#define I2C_TIMEOUTR_TIMOUTEN BIT(15)
#define I2C_TIMEOUTR_TIMEOUTB GENMASK(27, 16)
#define I2C_TIMEOUTR_TEXTEN BIT(31)
/* Bit definition for I2C_ISR register */
#define I2C_ISR_TXE BIT(0)
#define I2C_ISR_TXIS BIT(1)
#define I2C_ISR_RXNE BIT(2)
#define I2C_ISR_ADDR BIT(3)
#define I2C_ISR_NACKF BIT(4)
#define I2C_ISR_STOPF BIT(5)
#define I2C_ISR_TC BIT(6)
#define I2C_ISR_TCR BIT(7)
#define I2C_ISR_BERR BIT(8)
#define I2C_ISR_ARLO BIT(9)
#define I2C_ISR_OVR BIT(10)
#define I2C_ISR_PECERR BIT(11)
#define I2C_ISR_TIMEOUT BIT(12)
#define I2C_ISR_ALERT BIT(13)
#define I2C_ISR_BUSY BIT(15)
#define I2C_ISR_DIR BIT(16)
#define I2C_ISR_ADDCODE GENMASK(23, 17)
/* Bit definition for I2C_ICR register */
#define I2C_ICR_ADDRCF BIT(3)
#define I2C_ICR_NACKCF BIT(4)
#define I2C_ICR_STOPCF BIT(5)
#define I2C_ICR_BERRCF BIT(8)
#define I2C_ICR_ARLOCF BIT(9)
#define I2C_ICR_OVRCF BIT(10)
#define I2C_ICR_PECCF BIT(11)
#define I2C_ICR_TIMOUTCF BIT(12)
#define I2C_ICR_ALERTCF BIT(13)
struct stm32_i2c_init_s {
uint32_t timing; /* Specifies the I2C_TIMINGR_register value
* This parameter is calculated by referring
* to I2C initialization section in Reference
* manual.
*/
uint32_t own_address1; /* Specifies the first device own address.
* This parameter can be a 7-bit or 10-bit
* address.
*/
uint32_t addressing_mode; /* Specifies if 7-bit or 10-bit addressing
* mode is selected.
* This parameter can be a value of @ref
* I2C_ADDRESSING_MODE.
*/
uint32_t dual_address_mode; /* Specifies if dual addressing mode is
* selected.
* This parameter can be a value of @ref
* I2C_DUAL_ADDRESSING_MODE.
*/
uint32_t own_address2; /* Specifies the second device own address
* if dual addressing mode is selected.
* This parameter can be a 7-bit address.
*/
uint32_t own_address2_masks; /* Specifies the acknowledge mask address
* second device own address if dual
* addressing mode is selected.
* This parameter can be a value of @ref
* I2C_OWN_ADDRESS2_MASKS.
*/
uint32_t general_call_mode; /* Specifies if general call mode is
* selected.
* This parameter can be a value of @ref
* I2C_GENERAL_CALL_ADDRESSING_MODE.
*/
uint32_t no_stretch_mode; /* Specifies if nostretch mode is
* selected.
* This parameter can be a value of @ref
* I2C_NOSTRETCH_MODE.
*/
};
enum i2c_state_e {
I2C_STATE_RESET = 0x00U, /* Peripheral is not yet
* initialized.
*/
I2C_STATE_READY = 0x20U, /* Peripheral Initialized
* and ready for use.
*/
I2C_STATE_BUSY = 0x24U, /* An internal process is
* ongoing.
*/
I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission process
* is ongoing.
*/
I2C_STATE_BUSY_RX = 0x22U, /* Data Reception process
* is ongoing.
*/
I2C_STATE_LISTEN = 0x28U, /* Address Listen Mode is
* ongoing.
*/
I2C_STATE_BUSY_TX_LISTEN = 0x29U, /* Address Listen Mode
* and Data Transmission
* process is ongoing.
*/
I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /* Address Listen Mode
* and Data Reception
* process is ongoing.
*/
I2C_STATE_ABORT = 0x60U, /* Abort user request ongoing. */
I2C_STATE_TIMEOUT = 0xA0U, /* Timeout state. */
I2C_STATE_ERROR = 0xE0U /* Error. */
};
enum i2c_mode_e {
I2C_MODE_NONE = 0x00U, /* No I2C communication on going. */
I2C_MODE_MASTER = 0x10U, /* I2C communication is in Master Mode. */
I2C_MODE_SLAVE = 0x20U, /* I2C communication is in Slave Mode. */
I2C_MODE_MEM = 0x40U /* I2C communication is in Memory Mode. */
};
#define I2C_ERROR_NONE 0x00000000U /* No error */
#define I2C_ERROR_BERR 0x00000001U /* BERR error */
#define I2C_ERROR_ARLO 0x00000002U /* ARLO error */
#define I2C_ERROR_AF 0x00000004U /* ACKF error */
#define I2C_ERROR_OVR 0x00000008U /* OVR error */
#define I2C_ERROR_DMA 0x00000010U /* DMA transfer error */
#define I2C_ERROR_TIMEOUT 0x00000020U /* Timeout error */
#define I2C_ERROR_SIZE 0x00000040U /* Size Management error */
struct i2c_handle_s {
uint32_t i2c_base_addr; /* Registers base address */
struct stm32_i2c_init_s i2c_init; /* Communication parameters */
uint8_t *p_buff; /* Pointer to transfer buffer */
uint16_t xfer_size; /* Transfer size */
uint16_t xfer_count; /* Transfer counter */
uint32_t prev_state; /* Communication previous
* state
*/
uint8_t lock; /* Locking object */
enum i2c_state_e i2c_state; /* Communication state */
enum i2c_mode_e i2c_mode; /* Communication mode */
uint32_t i2c_err; /* Error code */
};
#define I2C_ADDRESSINGMODE_7BIT 0x00000001U
#define I2C_ADDRESSINGMODE_10BIT 0x00000002U
#define I2C_DUALADDRESS_DISABLE 0x00000000U
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define I2C_GENERALCALL_DISABLE 0x00000000U
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
#define I2C_NOSTRETCH_DISABLE 0x00000000U
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define I2C_MEMADD_SIZE_8BIT 0x00000001U
#define I2C_MEMADD_SIZE_16BIT 0x00000002U
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE 0x00000000U
#define I2C_NO_STARTSTOP 0x00000000U
#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \
I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START)
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
#define I2C_RESET_CR2 (I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
int stm32_i2c_init(struct i2c_handle_s *hi2c);
int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout);
int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout);
int stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint32_t trials, uint32_t timeout);
int stm32_i2c_config_analog_filter(struct i2c_handle_s *hi2c,
uint32_t analog_filter);
#endif /* __STM32MP1_I2C_H */
include/drivers/st/stm32mp1_clk.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __STM32MP1_CLK_H__
#define __STM32MP1_CLK_H__
#include <arch_helpers.h>
#include <stdbool.h>
int stm32mp1_clk_probe(void);
int stm32mp1_clk_init(void);
bool stm32mp1_clk_is_enabled(unsigned long id);
int stm32mp1_clk_enable(unsigned long id);
int stm32mp1_clk_disable(unsigned long id);
unsigned long stm32mp1_clk_get_rate(unsigned long id);
void stm32mp1_stgen_increment(unsigned long long offset_in_ms);
static inline uint32_t get_timer(uint32_t base)
{
if (base == 0U) {
return (uint32_t)(~read_cntpct_el0());
}
return base - (uint32_t)(~read_cntpct_el0());
}
#endif /* __STM32MP1_CLK_H__ */
include/drivers/st/stm32mp1_clkfunc.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __STM32MP1_CLKFUNC_H__
#define __STM32MP1_CLKFUNC_H__
#include <stdbool.h>
enum stm32mp_osc_id {
_HSI,
_HSE,
_CSI,
_LSI,
_LSE,
_I2S_CKIN,
_USB_PHY_48,
NB_OSC,
_UNKNOWN_OSC_ID = 0xFF
};
extern const char *stm32mp_osc_node_label[NB_OSC];
int fdt_osc_read_freq(const char *name, uint32_t *freq);
bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name);
uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
const char *prop_name,
uint32_t dflt_value);
uint32_t fdt_rcc_read_addr(void);
int fdt_rcc_read_uint32_array(const char *prop_name,
uint32_t *array, uint32_t count);
int fdt_rcc_subnode_offset(const char *name);
const uint32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
bool fdt_get_rcc_secure_status(void);
uintptr_t fdt_get_stgen_base(void);
int fdt_get_clock_id(int node);
#endif /* __STM32MP1_CLKFUNC_H__ */
include/drivers/st/stm32mp1_ddr.h 0 → 100644
View file @ d87d524e
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
#ifndef _STM32MP1_DDR_H
#define _STM32MP1_DDR_H
#include <stdbool.h>
#define DT_DDR_COMPAT "st,stm32mp1-ddr"
struct stm32mp1_ddr_size {
uint64_t base;
uint64_t size;
};
/**
* struct ddr_info
*
* @dev: pointer for the device
* @info: UCLASS RAM information
* @ctl: DDR controleur base address
* @phy: DDR PHY base address
* @syscfg: syscfg base address
*/
struct ddr_info {
struct stm32mp1_ddr_size info;
struct stm32mp1_ddrctl *ctl;
struct stm32mp1_ddrphy *phy;
uintptr_t pwr;
uintptr_t rcc;
};
struct stm32mp1_ddrctrl_reg {
uint32_t mstr;
uint32_t mrctrl0;
uint32_t mrctrl1;
uint32_t derateen;
uint32_t derateint;
uint32_t pwrctl;
uint32_t pwrtmg;
uint32_t hwlpctl;
uint32_t rfshctl0;
uint32_t rfshctl3;
uint32_t crcparctl0;
uint32_t zqctl0;
uint32_t dfitmg0;
uint32_t dfitmg1;
uint32_t dfilpcfg0;
uint32_t dfiupd0;
uint32_t dfiupd1;
uint32_t dfiupd2;
uint32_t dfiphymstr;
uint32_t odtmap;
uint32_t dbg0;
uint32_t dbg1;
uint32_t dbgcmd;
uint32_t poisoncfg;
uint32_t pccfg;
};
struct stm32mp1_ddrctrl_timing {
uint32_t rfshtmg;
uint32_t dramtmg0;
uint32_t dramtmg1;
uint32_t dramtmg2;
uint32_t dramtmg3;
uint32_t dramtmg4;
uint32_t dramtmg5;
uint32_t dramtmg6;
uint32_t dramtmg7;
uint32_t dramtmg8;
uint32_t dramtmg14;
uint32_t odtcfg;
};
struct stm32mp1_ddrctrl_map {
uint32_t addrmap1;
uint32_t addrmap2;
uint32_t addrmap3;
uint32_t addrmap4;
uint32_t addrmap5;
uint32_t addrmap6;
uint32_t addrmap9;
uint32_t addrmap10;
uint32_t addrmap11;
};
struct stm32mp1_ddrctrl_perf {
uint32_t sched;
uint32_t sched1;
uint32_t perfhpr1;
uint32_t perflpr1;
uint32_t perfwr1;
uint32_t pcfgr_0;
uint32_t pcfgw_0;
uint32_t pcfgqos0_0;
uint32_t pcfgqos1_0;
uint32_t pcfgwqos0_0;
uint32_t pcfgwqos1_0;
uint32_t pcfgr_1;
uint32_t pcfgw_1;
uint32_t pcfgqos0_1;
uint32_t pcfgqos1_1;
uint32_t pcfgwqos0_1;
uint32_t pcfgwqos1_1;
};
struct stm32mp1_ddrphy_reg {
uint32_t pgcr;
uint32_t aciocr;
uint32_t dxccr;
uint32_t dsgcr;
uint32_t dcr;
uint32_t odtcr;
uint32_t zq0cr1;
uint32_t dx0gcr;
uint32_t dx1gcr;
uint32_t dx2gcr;
uint32_t dx3gcr;
};
struct stm32mp1_ddrphy_timing {
uint32_t ptr0;
uint32_t ptr1;
uint32_t ptr2;
uint32_t dtpr0;
uint32_t dtpr1;
uint32_t dtpr2;
uint32_t mr0;
uint32_t mr1;
uint32_t mr2;
uint32_t mr3;
};
struct stm32mp1_ddrphy_cal {
uint32_t dx0dllcr;
uint32_t dx0dqtr;
uint32_t dx0dqstr;
uint32_t dx1dllcr;
uint32_t dx1dqtr;
uint32_t dx1dqstr;
uint32_t dx2dllcr;
uint32_t dx2dqtr;
uint32_t dx2dqstr;
uint32_t dx3dllcr;
uint32_t dx3dqtr;
uint32_t dx3dqstr;
};
struct stm32mp1_ddr_info {
const char *name;
uint16_t speed; /* in MHZ */
uint32_t size; /* Memory size in byte = col * row * width */
};
struct stm32mp1_ddr_config {
struct stm32mp1_ddr_info info;
struct stm32mp1_ddrctrl_reg c_reg;
struct stm32mp1_ddrctrl_timing c_timing;
struct stm32mp1_ddrctrl_map c_map;
struct stm32mp1_ddrctrl_perf c_perf;
struct stm32mp1_ddrphy_reg p_reg;
struct stm32mp1_ddrphy_timing p_timing;
struct stm32mp1_ddrphy_cal p_cal;
};
int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed);
void stm32mp1_ddr_init(struct ddr_info *priv,
struct stm32mp1_ddr_config *config);
#endif /* _STM32MP1_DDR_H */
include/drivers/st/stm32mp1_ddr_helpers.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __STM32MP1_DDR_HELPERS_H__
#define __STM32MP1_DDR_HELPERS_H__
void ddr_enable_clock(void);
#endif /* __STM32MP1_DDR_HELPERS_H__ */
include/drivers/st/stm32mp1_ddr_regs.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
#ifndef _RAM_STM32MP1_DDR_REGS_H
#define _RAM_STM32MP1_DDR_REGS_H
#include <utils_def.h>
/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
struct stm32mp1_ddrctl {
uint32_t mstr ; /* 0x0 Master */
uint32_t stat; /* 0x4 Operating Mode Status */
uint8_t reserved008[0x10 - 0x8];
uint32_t mrctrl0; /* 0x10 Control 0 */
uint32_t mrctrl1; /* 0x14 Control 1 */
uint32_t mrstat; /* 0x18 Status */
uint32_t reserved01c; /* 0x1c */
uint32_t derateen; /* 0x20 Temperature Derate Enable */
uint32_t derateint; /* 0x24 Temperature Derate Interval */
uint8_t reserved028[0x30 - 0x28];
uint32_t pwrctl; /* 0x30 Low Power Control */
uint32_t pwrtmg; /* 0x34 Low Power Timing */
uint32_t hwlpctl; /* 0x38 Hardware Low Power Control */
uint8_t reserved03c[0x50 - 0x3C];
uint32_t rfshctl0; /* 0x50 Refresh Control 0 */
uint32_t reserved054; /* 0x54 Refresh Control 1 */
uint32_t reserved058; /* 0x58 Refresh Control 2 */
uint32_t reserved05C;
uint32_t rfshctl3; /* 0x60 Refresh Control 0 */
uint32_t rfshtmg; /* 0x64 Refresh Timing */
uint8_t reserved068[0xc0 - 0x68];
uint32_t crcparctl0; /* 0xc0 CRC Parity Control0 */
uint32_t reserved0c4; /* 0xc4 CRC Parity Control1 */
uint32_t reserved0c8; /* 0xc8 CRC Parity Control2 */
uint32_t crcparstat; /* 0xcc CRC Parity Status */
uint32_t init0; /* 0xd0 SDRAM Initialization 0 */
uint32_t init1; /* 0xd4 SDRAM Initialization 1 */
uint32_t init2; /* 0xd8 SDRAM Initialization 2 */
uint32_t init3; /* 0xdc SDRAM Initialization 3 */
uint32_t init4; /* 0xe0 SDRAM Initialization 4 */
uint32_t init5; /* 0xe4 SDRAM Initialization 5 */
uint32_t reserved0e8;
uint32_t reserved0ec;
uint32_t dimmctl; /* 0xf0 DIMM Control */
uint8_t reserved0f4[0x100 - 0xf4];
uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */
uint32_t dramtmg1; /* 0x104 SDRAM Timing 1 */
uint32_t dramtmg2; /* 0x108 SDRAM Timing 2 */
uint32_t dramtmg3; /* 0x10c SDRAM Timing 3 */
uint32_t dramtmg4; /* 0x110 SDRAM Timing 4 */
uint32_t dramtmg5; /* 0x114 SDRAM Timing 5 */
uint32_t dramtmg6; /* 0x118 SDRAM Timing 6 */
uint32_t dramtmg7; /* 0x11c SDRAM Timing 7 */
uint32_t dramtmg8; /* 0x120 SDRAM Timing 8 */
uint8_t reserved124[0x138 - 0x124];
uint32_t dramtmg14; /* 0x138 SDRAM Timing 14 */
uint32_t dramtmg15; /* 0x13C SDRAM Timing 15 */
uint8_t reserved140[0x180 - 0x140];
uint32_t zqctl0; /* 0x180 ZQ Control 0 */
uint32_t zqctl1; /* 0x184 ZQ Control 1 */
uint32_t zqctl2; /* 0x188 ZQ Control 2 */
uint32_t zqstat; /* 0x18c ZQ Status */
uint32_t dfitmg0; /* 0x190 DFI Timing 0 */
uint32_t dfitmg1; /* 0x194 DFI Timing 1 */
uint32_t dfilpcfg0; /* 0x198 DFI Low Power Configuration 0 */
uint32_t reserved19c;
uint32_t dfiupd0; /* 0x1a0 DFI Update 0 */
uint32_t dfiupd1; /* 0x1a4 DFI Update 1 */
uint32_t dfiupd2; /* 0x1a8 DFI Update 2 */
uint32_t reserved1ac;
uint32_t dfimisc; /* 0x1b0 DFI Miscellaneous Control */
uint8_t reserved1b4[0x1bc - 0x1b4];
uint32_t dfistat; /* 0x1bc DFI Miscellaneous Control */
uint8_t reserved1c0[0x1c4 - 0x1c0];
uint32_t dfiphymstr; /* 0x1c4 DFI PHY Master interface */
uint8_t reserved1c8[0x204 - 0x1c8];
uint32_t addrmap1; /* 0x204 Address Map 1 */
uint32_t addrmap2; /* 0x208 Address Map 2 */
uint32_t addrmap3; /* 0x20c Address Map 3 */
uint32_t addrmap4; /* 0x210 Address Map 4 */
uint32_t addrmap5; /* 0x214 Address Map 5 */
uint32_t addrmap6; /* 0x218 Address Map 6 */
uint8_t reserved21c[0x224 - 0x21c];
uint32_t addrmap9; /* 0x224 Address Map 9 */
uint32_t addrmap10; /* 0x228 Address Map 10 */
uint32_t addrmap11; /* 0x22C Address Map 11 */
uint8_t reserved230[0x240 - 0x230];
uint32_t odtcfg; /* 0x240 ODT Configuration */
uint32_t odtmap; /* 0x244 ODT/Rank Map */
uint8_t reserved248[0x250 - 0x248];
uint32_t sched; /* 0x250 Scheduler Control */
uint32_t sched1; /* 0x254 Scheduler Control 1 */
uint32_t reserved258;
uint32_t perfhpr1; /* 0x25c High Priority Read CAM 1 */
uint32_t reserved260;
uint32_t perflpr1; /* 0x264 Low Priority Read CAM 1 */
uint32_t reserved268;
uint32_t perfwr1; /* 0x26c Write CAM 1 */
uint8_t reserved27c[0x300 - 0x270];
uint32_t dbg0; /* 0x300 Debug 0 */
uint32_t dbg1; /* 0x304 Debug 1 */
uint32_t dbgcam; /* 0x308 CAM Debug */
uint32_t dbgcmd; /* 0x30c Command Debug */
uint32_t dbgstat; /* 0x310 Status Debug */
uint8_t reserved314[0x320 - 0x314];
uint32_t swctl; /* 0x320 Software Programming Control Enable */
uint32_t swstat; /* 0x324 Software Programming Control Status */
uint8_t reserved328[0x36c - 0x328];
uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */
uint32_t poisonstat; /* 0x370 AXI Poison Status Register */
uint8_t reserved374[0x3fc - 0x374];
/* Multi Port registers */
uint32_t pstat; /* 0x3fc Port Status */
uint32_t pccfg; /* 0x400 Port Common Configuration */
/* PORT 0 */
uint32_t pcfgr_0; /* 0x404 Configuration Read */
uint32_t pcfgw_0; /* 0x408 Configuration Write */
uint8_t reserved40c[0x490 - 0x40c];
uint32_t pctrl_0; /* 0x490 Port Control Register */
uint32_t pcfgqos0_0; /* 0x494 Read QoS Configuration 0 */
uint32_t pcfgqos1_0; /* 0x498 Read QoS Configuration 1 */
uint32_t pcfgwqos0_0; /* 0x49c Write QoS Configuration 0 */
uint32_t pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1 */
uint8_t reserved4a4[0x4b4 - 0x4a4];
/* PORT 1 */
uint32_t pcfgr_1; /* 0x4b4 Configuration Read */
uint32_t pcfgw_1; /* 0x4b8 Configuration Write */
uint8_t reserved4bc[0x540 - 0x4bc];
uint32_t pctrl_1; /* 0x540 Port 2 Control Register */
uint32_t pcfgqos0_1; /* 0x544 Read QoS Configuration 0 */
uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */
uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */
uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */
} __packed;
/* DDR Physical Interface Control (DDRPHYC) registers*/
struct stm32mp1_ddrphy {
uint32_t ridr; /* 0x00 R Revision Identification */
uint32_t pir; /* 0x04 R/W PHY Initialization */
uint32_t pgcr; /* 0x08 R/W PHY General Configuration */
uint32_t pgsr; /* 0x0C PHY General Status */
uint32_t dllgcr; /* 0x10 R/W DLL General Control */
uint32_t acdllcr; /* 0x14 R/W AC DLL Control */
uint32_t ptr0; /* 0x18 R/W PHY Timing 0 */
uint32_t ptr1; /* 0x1C R/W PHY Timing 1 */
uint32_t ptr2; /* 0x20 R/W PHY Timing 2 */
uint32_t aciocr; /* 0x24 AC I/O Configuration */
uint32_t dxccr; /* 0x28 DATX8 Common Configuration */
uint32_t dsgcr; /* 0x2C DDR System General Configuration */
uint32_t dcr; /* 0x30 DRAM Configuration */
uint32_t dtpr0; /* 0x34 DRAM Timing Parameters0 */
uint32_t dtpr1; /* 0x38 DRAM Timing Parameters1 */
uint32_t dtpr2; /* 0x3C DRAM Timing Parameters2 */
uint32_t mr0; /* 0x40 Mode 0 */
uint32_t mr1; /* 0x44 Mode 1 */
uint32_t mr2; /* 0x48 Mode 2 */
uint32_t mr3; /* 0x4C Mode 3 */
uint32_t odtcr; /* 0x50 ODT Configuration */
uint32_t dtar; /* 0x54 data training address */
uint32_t dtdr0; /* 0x58 */
uint32_t dtdr1; /* 0x5c */
uint8_t res1[0x0c0 - 0x060]; /* 0x60 */
uint32_t dcuar; /* 0xc0 Address */
uint32_t dcudr; /* 0xc4 DCU Data */
uint32_t dcurr; /* 0xc8 DCU Run */
uint32_t dculr; /* 0xcc DCU Loop */
uint32_t dcugcr; /* 0xd0 DCU General Configuration */
uint32_t dcutpr; /* 0xd4 DCU Timing Parameters */
uint32_t dcusr0; /* 0xd8 DCU Status 0 */
uint32_t dcusr1; /* 0xdc DCU Status 1 */
uint8_t res2[0x100 - 0xe0]; /* 0xe0 */
uint32_t bistrr; /* 0x100 BIST Run */
uint32_t bistmskr0; /* 0x104 BIST Mask 0 */
uint32_t bistmskr1; /* 0x108 BIST Mask 0 */
uint32_t bistwcr; /* 0x10c BIST Word Count */
uint32_t bistlsr; /* 0x110 BIST LFSR Seed */
uint32_t bistar0; /* 0x114 BIST Address 0 */
uint32_t bistar1; /* 0x118 BIST Address 1 */
uint32_t bistar2; /* 0x11c BIST Address 2 */
uint32_t bistupdr; /* 0x120 BIST User Data Pattern */
uint32_t bistgsr; /* 0x124 BIST General Status */
uint32_t bistwer; /* 0x128 BIST Word Error */
uint32_t bistber0; /* 0x12c BIST Bit Error 0 */
uint32_t bistber1; /* 0x130 BIST Bit Error 1 */
uint32_t bistber2; /* 0x134 BIST Bit Error 2 */
uint32_t bistwcsr; /* 0x138 BIST Word Count Status */
uint32_t bistfwr0; /* 0x13c BIST Fail Word 0 */
uint32_t bistfwr1; /* 0x140 BIST Fail Word 1 */
uint8_t res3[0x178 - 0x144]; /* 0x144 */
uint32_t gpr0; /* 0x178 General Purpose 0 (GPR0) */
uint32_t gpr1; /* 0x17C General Purpose 1 (GPR1) */
uint32_t zq0cr0; /* 0x180 zq 0 control 0 */
uint32_t zq0cr1; /* 0x184 zq 0 control 1 */
uint32_t zq0sr0; /* 0x188 zq 0 status 0 */
uint32_t zq0sr1; /* 0x18C zq 0 status 1 */
uint8_t res4[0x1C0 - 0x190]; /* 0x190 */
uint32_t dx0gcr; /* 0x1c0 Byte lane 0 General Configuration */
uint32_t dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0 */
uint32_t dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1 */
uint32_t dx0dllcr; /* 0x1cc Byte lane 0 DLL Control */
uint32_t dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing */
uint32_t dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing */
uint8_t res5[0x200 - 0x1d8]; /* 0x1d8 */
uint32_t dx1gcr; /* 0x200 Byte lane 1 General Configuration */
uint32_t dx1gsr0; /* 0x204 Byte lane 1 General Status 0 */
uint32_t dx1gsr1; /* 0x208 Byte lane 1 General Status 1 */
uint32_t dx1dllcr; /* 0x20c Byte lane 1 DLL Control */
uint32_t dx1dqtr; /* 0x210 Byte lane 1 DQ Timing */
uint32_t dx1dqstr; /* 0x214 Byte lane 1 QS Timing */
uint8_t res6[0x240 - 0x218]; /* 0x218 */
uint32_t dx2gcr; /* 0x240 Byte lane 2 General Configuration */
uint32_t dx2gsr0; /* 0x244 Byte lane 2 General Status 0 */
uint32_t dx2gsr1; /* 0x248 Byte lane 2 General Status 1 */
uint32_t dx2dllcr; /* 0x24c Byte lane 2 DLL Control */
uint32_t dx2dqtr; /* 0x250 Byte lane 2 DQ Timing */
uint32_t dx2dqstr; /* 0x254 Byte lane 2 QS Timing */
uint8_t res7[0x280 - 0x258]; /* 0x258 */
uint32_t dx3gcr; /* 0x280 Byte lane 3 General Configuration */
uint32_t dx3gsr0; /* 0x284 Byte lane 3 General Status 0 */
uint32_t dx3gsr1; /* 0x288 Byte lane 3 General Status 1 */
uint32_t dx3dllcr; /* 0x28c Byte lane 3 DLL Control */
uint32_t dx3dqtr; /* 0x290 Byte lane 3 DQ Timing */
uint32_t dx3dqstr; /* 0x294 Byte lane 3 QS Timing */
} __packed;
/* DDR Controller registers offsets */
#define DDRCTRL_MSTR 0x000
#define DDRCTRL_STAT 0x004
#define DDRCTRL_MRCTRL0 0x010
#define DDRCTRL_MRSTAT 0x018
#define DDRCTRL_PWRCTL 0x030
#define DDRCTRL_PWRTMG 0x034
#define DDRCTRL_HWLPCTL 0x038
#define DDRCTRL_RFSHCTL3 0x060
#define DDRCTRL_RFSHTMG 0x064
#define DDRCTRL_INIT0 0x0D0
#define DDRCTRL_DFIMISC 0x1B0
#define DDRCTRL_DBG1 0x304
#define DDRCTRL_DBGCAM 0x308
#define DDRCTRL_DBGCMD 0x30C
#define DDRCTRL_DBGSTAT 0x310
#define DDRCTRL_SWCTL 0x320
#define DDRCTRL_SWSTAT 0x324
#define DDRCTRL_PCTRL_0 0x490
#define DDRCTRL_PCTRL_1 0x540
/* DDR Controller Register fields */
#define DDRCTRL_MSTR_DDR3 BIT(0)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL 0
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF BIT(12)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER BIT(13)
#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15)
#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
#define DDRCTRL_STAT_OPERATING_MODE_NORMAL BIT(0)
#define DDRCTRL_STAT_OPERATING_MODE_SR (BIT(0) | BIT(1))
#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
#define DDRCTRL_STAT_SELFREF_TYPE_ASR (BIT(4) | BIT(5))
#define DDRCTRL_STAT_SELFREF_TYPE_SR BIT(5)
#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE U(0)
/* Only one rank supported */
#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4
#define DDRCTRL_MRCTRL0_MR_RANK_ALL \
(0x1U << DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12
#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
#define DDRCTRL_MRCTRL0_MR_WR BIT(31)
#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0)
#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0)
#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1)
#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3)
#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(19, 12)
#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16)
#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0)
#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0)
#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16
#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30)
#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL BIT(30)
#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
#define DDRCTRL_DBG1_DIS_HIF BIT(1)
#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29)
#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28)
#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26)
#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \
(DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \
DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY)
#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \
(DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \
DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH)
#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0)
#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0)
#define DDRCTRL_SWCTL_SW_DONE BIT(0)
#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0)
#define DDRCTRL_PCTRL_N_PORT_EN BIT(0)
/* DDR PHY registers offsets */
#define DDRPHYC_PIR 0x004
#define DDRPHYC_PGCR 0x008
#define DDRPHYC_PGSR 0x00C
#define DDRPHYC_DLLGCR 0x010
#define DDRPHYC_ACDLLCR 0x014
#define DDRPHYC_PTR0 0x018
#define DDRPHYC_ACIOCR 0x024
#define DDRPHYC_DXCCR 0x028
#define DDRPHYC_DSGCR 0x02C
#define DDRPHYC_ZQ0CR0 0x180
#define DDRPHYC_DX0GCR 0x1C0
#define DDRPHYC_DX0DLLCR 0x1CC
#define DDRPHYC_DX1GCR 0x200
#define DDRPHYC_DX1DLLCR 0x20C
#define DDRPHYC_DX2GCR 0x240
#define DDRPHYC_DX2DLLCR 0x24C
#define DDRPHYC_DX3GCR 0x280
#define DDRPHYC_DX3DLLCR 0x28C
/* DDR PHY Register fields */
#define DDRPHYC_PIR_INIT BIT(0)
#define DDRPHYC_PIR_DLLSRST BIT(1)
#define DDRPHYC_PIR_DLLLOCK BIT(2)
#define DDRPHYC_PIR_ZCAL BIT(3)
#define DDRPHYC_PIR_ITMSRST BIT(4)
#define DDRPHYC_PIR_DRAMRST BIT(5)
#define DDRPHYC_PIR_DRAMINIT BIT(6)
#define DDRPHYC_PIR_QSTRN BIT(7)
#define DDRPHYC_PIR_ICPC BIT(16)
#define DDRPHYC_PIR_ZCALBYP BIT(30)
#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
#define DDRPHYC_PGCR_DFTCMP BIT(2)
#define DDRPHYC_PGCR_PDDISDX BIT(24)
#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
#define DDRPHYC_PGSR_IDONE BIT(0)
#define DDRPHYC_PGSR_DTERR BIT(5)
#define DDRPHYC_PGSR_DTIERR BIT(6)
#define DDRPHYC_PGSR_DFTERR BIT(7)
#define DDRPHYC_PGSR_RVERR BIT(8)
#define DDRPHYC_PGSR_RVEIRR BIT(9)
#define DDRPHYC_DLLGCR_BPS200 BIT(23)
#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
#define DDRPHYC_PTR0_TDLLSRST_OFFSET 0
#define DDRPHYC_PTR0_TDLLSRST_MASK GENMASK(5, 0)
#define DDRPHYC_PTR0_TDLLLOCK_OFFSET 6
#define DDRPHYC_PTR0_TDLLLOCK_MASK GENMASK(17, 6)
#define DDRPHYC_PTR0_TITMSRST_OFFSET 18
#define DDRPHYC_PTR0_TITMSRST_MASK GENMASK(21, 18)
#define DDRPHYC_ACIOCR_ACPDD BIT(3)
#define DDRPHYC_ACIOCR_ACPDR BIT(4)
#define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8)
#define DDRPHYC_ACIOCR_CKPDD_0 BIT(8)
#define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11)
#define DDRPHYC_ACIOCR_CKPDR_0 BIT(11)
#define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(21, 18)
#define DDRPHYC_ACIOCR_CSPDD_0 BIT(18)
#define DDRPHYC_ACIOCR_RSTPDD BIT(27)
#define DDRPHYC_ACIOCR_RSTPDR BIT(28)
#define DDRPHYC_DXCCR_DXPDD BIT(2)
#define DDRPHYC_DXCCR_DXPDR BIT(3)
#define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16)
#define DDRPHYC_DSGCR_CKEPDD_0 BIT(16)
#define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20)
#define DDRPHYC_DSGCR_ODTPDD_0 BIT(20)
#define DDRPHYC_DSGCR_NL2PD BIT(24)
#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0
#define DDRPHYC_ZQ0CRN_ZDEN BIT(28)
#define DDRPHYC_ZQ0CRN_ZQPD BIT(31)
#define DDRPHYC_DXNGCR_DXEN BIT(0)
#define DDRPHYC_DXNDLLCR_DLLSRST BIT(30)
#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14)
#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14
void ddr_enable_clock(void);
#endif /* _RAM_STM32MP1_DDR_REGS_H */
include/drivers/st/stm32mp1_pmic.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __STM32MP1_PMIC_H__
#define __STM32MP1_PMIC_H__
#include <stdbool.h>
bool dt_check_pmic(void);
int dt_pmic_enable_boot_on_regulators(void);
void initialize_pmic_i2c(void);
void initialize_pmic(void);
int pmic_ddr_power_init(enum ddr_type ddr_type);
#endif /* __STM32MP1_PMIC_H__ */
include/drivers/st/stm32mp1_pwr.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __STM32MP1_PWR_H__
#define __STM32MP1_PWR_H__
#include <utils_def.h>
#define PWR_CR1 U(0x00)
#define PWR_CR2 U(0x08)
#define PWR_CR3 U(0x0C)
#define PWR_MPUCR U(0x10)
#define PWR_WKUPCR U(0x20)
#define PWR_MPUWKUPENR U(0x28)
#define PWR_CR1_LPDS BIT(0)
#define PWR_CR1_LPCFG BIT(1)
#define PWR_CR1_LVDS BIT(2)
#define PWR_CR1_DBP BIT(8)
#define PWR_CR3_DDRSREN BIT(10)
#define PWR_CR3_DDRSRDIS BIT(11)
#define PWR_CR3_DDRRETEN BIT(12)
#define PWR_MPUCR_PDDS BIT(0)
#define PWR_MPUCR_CSTDBYDIS BIT(3)
#define PWR_MPUCR_CSSF BIT(9)
#endif /* __STM32MP1_PWR_H__ */
include/drivers/st/stm32mp1_ram.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _STM32MP1_RAM_H
#define _STM32MP1_RAM_H
int stm32mp1_ddr_probe(void);
#endif /* _STM32MP1_RAM_H */
include/drivers/st/stm32mp1_rcc.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __STM32MP1_RCC_H__
#define __STM32MP1_RCC_H__
#include <utils_def.h>
#define RCC_TZCR U(0x00)
#define RCC_OCENSETR U(0x0C)
#define RCC_OCENCLRR U(0x10)
#define RCC_HSICFGR U(0x18)
#define RCC_CSICFGR U(0x1C)
#define RCC_MPCKSELR U(0x20)
#define RCC_ASSCKSELR U(0x24)
#define RCC_RCK12SELR U(0x28)
#define RCC_MPCKDIVR U(0x2C)
#define RCC_AXIDIVR U(0x30)
#define RCC_APB4DIVR U(0x3C)
#define RCC_APB5DIVR U(0x40)
#define RCC_RTCDIVR U(0x44)
#define RCC_MSSCKSELR U(0x48)
#define RCC_PLL1CR U(0x80)
#define RCC_PLL1CFGR1 U(0x84)
#define RCC_PLL1CFGR2 U(0x88)
#define RCC_PLL1FRACR U(0x8C)
#define RCC_PLL1CSGR U(0x90)
#define RCC_PLL2CR U(0x94)
#define RCC_PLL2CFGR1 U(0x98)
#define RCC_PLL2CFGR2 U(0x9C)
#define RCC_PLL2FRACR U(0xA0)
#define RCC_PLL2CSGR U(0xA4)
#define RCC_I2C46CKSELR U(0xC0)
#define RCC_SPI6CKSELR U(0xC4)
#define RCC_UART1CKSELR U(0xC8)
#define RCC_RNG1CKSELR U(0xCC)
#define RCC_CPERCKSELR U(0xD0)
#define RCC_STGENCKSELR U(0xD4)
#define RCC_DDRITFCR U(0xD8)
#define RCC_MP_BOOTCR U(0x100)
#define RCC_MP_SREQSETR U(0x104)
#define RCC_MP_SREQCLRR U(0x108)
#define RCC_MP_GCR U(0x10C)
#define RCC_MP_APRSTCR U(0x110)
#define RCC_MP_APRSTSR U(0x114)
#define RCC_BDCR U(0x140)
#define RCC_RDLSICR U(0x144)
#define RCC_APB4RSTSETR U(0x180)
#define RCC_APB4RSTCLRR U(0x184)
#define RCC_APB5RSTSETR U(0x188)
#define RCC_APB5RSTCLRR U(0x18C)
#define RCC_AHB5RSTSETR U(0x190)
#define RCC_AHB5RSTCLRR U(0x194)
#define RCC_AHB6RSTSETR U(0x198)
#define RCC_AHB6RSTCLRR U(0x19C)
#define RCC_TZAHB6RSTSETR U(0x1A0)
#define RCC_TZAHB6RSTCLRR U(0x1A4)
#define RCC_MP_APB4ENSETR U(0x200)
#define RCC_MP_APB4ENCLRR U(0x204)
#define RCC_MP_APB5ENSETR U(0x208)
#define RCC_MP_APB5ENCLRR U(0x20C)
#define RCC_MP_AHB5ENSETR U(0x210)
#define RCC_MP_AHB5ENCLRR U(0x214)
#define RCC_MP_AHB6ENSETR U(0x218)
#define RCC_MP_AHB6ENCLRR U(0x21C)
#define RCC_MP_TZAHB6ENSETR U(0x220)
#define RCC_MP_TZAHB6ENCLRR U(0x224)
#define RCC_MP_APB4LPENSETR U(0x300)
#define RCC_MP_APB4LPENCLRR U(0x304)
#define RCC_MP_APB5LPENSETR U(0x308)
#define RCC_MP_APB5LPENCLRR U(0x30C)
#define RCC_MP_AHB5LPENSETR U(0x310)
#define RCC_MP_AHB5LPENCLRR U(0x314)
#define RCC_MP_AHB6LPENSETR U(0x318)
#define RCC_MP_AHB6LPENCLRR U(0x31C)
#define RCC_MP_TZAHB6LPENSETR U(0x320)
#define RCC_MP_TZAHB6LPENCLRR U(0x324)
#define RCC_BR_RSTSCLRR U(0x400)
#define RCC_MP_GRSTCSETR U(0x404)
#define RCC_MP_RSTSCLRR U(0x408)
#define RCC_MP_IWDGFZSETR U(0x40C)
#define RCC_MP_IWDGFZCLRR U(0x410)
#define RCC_MP_CIER U(0x414)
#define RCC_MP_CIFR U(0x418)
#define RCC_PWRLPDLYCR U(0x41C)
#define RCC_MP_RSTSSETR U(0x420)
#define RCC_MCO1CFGR U(0x800)
#define RCC_MCO2CFGR U(0x804)
#define RCC_OCRDYR U(0x808)
#define RCC_DBGCFGR U(0x80C)
#define RCC_RCK3SELR U(0x820)
#define RCC_RCK4SELR U(0x824)
#define RCC_TIMG1PRER U(0x828)
#define RCC_TIMG2PRER U(0x82C)
#define RCC_APB1DIVR U(0x834)
#define RCC_APB2DIVR U(0x838)
#define RCC_APB3DIVR U(0x83C)
#define RCC_PLL3CR U(0x880)
#define RCC_PLL3CFGR1 U(0x884)
#define RCC_PLL3CFGR2 U(0x888)
#define RCC_PLL3FRACR U(0x88C)
#define RCC_PLL3CSGR U(0x890)
#define RCC_PLL4CR U(0x894)
#define RCC_PLL4CFGR1 U(0x898)
#define RCC_PLL4CFGR2 U(0x89C)
#define RCC_PLL4FRACR U(0x8A0)
#define RCC_PLL4CSGR U(0x8A4)
#define RCC_I2C12CKSELR U(0x8C0)
#define RCC_I2C35CKSELR U(0x8C4)
#define RCC_SAI1CKSELR U(0x8C8)
#define RCC_SAI2CKSELR U(0x8CC)
#define RCC_SAI3CKSELR U(0x8D0)
#define RCC_SAI4CKSELR U(0x8D4)
#define RCC_SPI2S1CKSELR U(0x8D8)
#define RCC_SPI2S23CKSELR U(0x8DC)
#define RCC_SPI45CKSELR U(0x8E0)
#define RCC_UART6CKSELR U(0x8E4)
#define RCC_UART24CKSELR U(0x8E8)
#define RCC_UART35CKSELR U(0x8EC)
#define RCC_UART78CKSELR U(0x8F0)
#define RCC_SDMMC12CKSELR U(0x8F4)
#define RCC_SDMMC3CKSELR U(0x8F8)
#define RCC_ETHCKSELR U(0x8FC)
#define RCC_QSPICKSELR U(0x900)
#define RCC_FMCCKSELR U(0x904)
#define RCC_FDCANCKSELR U(0x90C)
#define RCC_SPDIFCKSELR U(0x914)
#define RCC_CECCKSELR U(0x918)
#define RCC_USBCKSELR U(0x91C)
#define RCC_RNG2CKSELR U(0x920)
#define RCC_DSICKSELR U(0x924)
#define RCC_ADCCKSELR U(0x928)
#define RCC_LPTIM45CKSELR U(0x92C)
#define RCC_LPTIM23CKSELR U(0x930)
#define RCC_LPTIM1CKSELR U(0x934)
#define RCC_APB1RSTSETR U(0x980)
#define RCC_APB1RSTCLRR U(0x984)
#define RCC_APB2RSTSETR U(0x988)
#define RCC_APB2RSTCLRR U(0x98C)
#define RCC_APB3RSTSETR U(0x990)
#define RCC_APB3RSTCLRR U(0x994)
#define RCC_AHB2RSTSETR U(0x998)
#define RCC_AHB2RSTCLRR U(0x99C)
#define RCC_AHB3RSTSETR U(0x9A0)
#define RCC_AHB3RSTCLRR U(0x9A4)
#define RCC_AHB4RSTSETR U(0x9A8)
#define RCC_AHB4RSTCLRR U(0x9AC)
#define RCC_MP_APB1ENSETR U(0xA00)
#define RCC_MP_APB1ENCLRR U(0xA04)
#define RCC_MP_APB2ENSETR U(0xA08)
#define RCC_MP_APB2ENCLRR U(0xA0C)
#define RCC_MP_APB3ENSETR U(0xA10)
#define RCC_MP_APB3ENCLRR U(0xA14)
#define RCC_MP_AHB2ENSETR U(0xA18)
#define RCC_MP_AHB2ENCLRR U(0xA1C)
#define RCC_MP_AHB3ENSETR U(0xA20)
#define RCC_MP_AHB3ENCLRR U(0xA24)
#define RCC_MP_AHB4ENSETR U(0xA28)
#define RCC_MP_AHB4ENCLRR U(0xA2C)
#define RCC_MP_MLAHBENSETR U(0xA38)
#define RCC_MP_MLAHBENCLRR U(0xA3C)
#define RCC_MP_APB1LPENSETR U(0xB00)
#define RCC_MP_APB1LPENCLRR U(0xB04)
#define RCC_MP_APB2LPENSETR U(0xB08)
#define RCC_MP_APB2LPENCLRR U(0xB0C)
#define RCC_MP_APB3LPENSETR U(0xB10)
#define RCC_MP_APB3LPENCLRR U(0xB14)
#define RCC_MP_AHB2LPENSETR U(0xB18)
#define RCC_MP_AHB2LPENCLRR U(0xB1C)
#define RCC_MP_AHB3LPENSETR U(0xB20)
#define RCC_MP_AHB3LPENCLRR U(0xB24)
#define RCC_MP_AHB4LPENSETR U(0xB28)
#define RCC_MP_AHB4LPENCLRR U(0xB2C)
#define RCC_MP_AXIMLPENSETR U(0xB30)
#define RCC_MP_AXIMLPENCLRR U(0xB34)
#define RCC_MP_MLAHBLPENSETR U(0xB38)
#define RCC_MP_MLAHBLPENCLRR U(0xB3C)
#define RCC_VERR U(0xFF4)
#define RCC_IDR U(0xFF8)
#define RCC_SIDR U(0xFFC)
/* Values for RCC_TZCR register */
#define RCC_TZCR_TZEN BIT(0)
/* Used for most of RCC_<x>SELR registers */
#define RCC_SELR_SRC_MASK GENMASK(2, 0)
#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0)
#define RCC_SELR_SRCRDY BIT(31)
/* Values of RCC_MPCKSELR register */
#define RCC_MPCKSELR_HSI 0x00000000
#define RCC_MPCKSELR_HSE 0x00000001
#define RCC_MPCKSELR_PLL 0x00000002
#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003
/* Values of RCC_ASSCKSELR register */
#define RCC_ASSCKSELR_HSI 0x00000000
#define RCC_ASSCKSELR_HSE 0x00000001
#define RCC_ASSCKSELR_PLL 0x00000002
/* Values of RCC_MSSCKSELR register */
#define RCC_MSSCKSELR_HSI 0x00000000
#define RCC_MSSCKSELR_HSE 0x00000001
#define RCC_MSSCKSELR_CSI 0x00000002
#define RCC_MSSCKSELR_PLL 0x00000003
/* Values of RCC_CPERCKSELR register */
#define RCC_CPERCKSELR_HSI 0x00000000
#define RCC_CPERCKSELR_CSI 0x00000001
#define RCC_CPERCKSELR_HSE 0x00000002
/* Used for most of DIVR register: max div for RTC */
#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
#define RCC_DIVR_DIVRDY BIT(31)
/* Masks for specific DIVR registers */
#define RCC_APBXDIV_MASK GENMASK(2, 0)
#define RCC_MPUDIV_MASK GENMASK(2, 0)
#define RCC_AXIDIV_MASK GENMASK(2, 0)
/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
#define RCC_MP_ENCLRR_OFFSET U(4)
/* Fields of RCC_BDCR register */
#define RCC_BDCR_LSEON BIT(0)
#define RCC_BDCR_LSEBYP BIT(1)
#define RCC_BDCR_LSERDY BIT(2)
#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
#define RCC_BDCR_LSEDRV_SHIFT 4
#define RCC_BDCR_LSECSSON BIT(8)
#define RCC_BDCR_RTCCKEN BIT(20)
#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
#define RCC_BDCR_RTCSRC_SHIFT 16
#define RCC_BDCR_VSWRST BIT(31)
/* Fields of RCC_RDLSICR register */
#define RCC_RDLSICR_LSION BIT(0)
#define RCC_RDLSICR_LSIRDY BIT(1)
/* Used for all RCC_PLL<n>CR registers */
#define RCC_PLLNCR_PLLON BIT(0)
#define RCC_PLLNCR_PLLRDY BIT(1)
#define RCC_PLLNCR_DIVPEN BIT(4)
#define RCC_PLLNCR_DIVQEN BIT(5)
#define RCC_PLLNCR_DIVREN BIT(6)
#define RCC_PLLNCR_DIVEN_SHIFT 4
/* Used for all RCC_PLL<n>CFGR1 registers */
#define RCC_PLLNCFGR1_DIVM_SHIFT 16
#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
#define RCC_PLLNCFGR1_DIVN_SHIFT 0
#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
/* Only for PLL3 and PLL4 */
#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
/* Used for all RCC_PLL<n>CFGR2 registers */
#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
#define RCC_PLLNCFGR2_DIVP_SHIFT 0
#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
#define RCC_PLLNCFGR2_DIVQ_SHIFT 8
#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
#define RCC_PLLNCFGR2_DIVR_SHIFT 16
#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
/* Used for all RCC_PLL<n>FRACR registers */
#define RCC_PLLNFRACR_FRACV_SHIFT 3
#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
#define RCC_PLLNFRACR_FRACLE BIT(16)
/* Used for all RCC_PLL<n>CSGR registers */
#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
/* Used for RCC_OCENSETR and RCC_OCENCLRR registers */
#define RCC_OCENR_HSION BIT(0)
#define RCC_OCENR_CSION BIT(4)
#define RCC_OCENR_HSEON BIT(8)
#define RCC_OCENR_HSEBYP BIT(10)
#define RCC_OCENR_HSECSSON BIT(11)
/* Fields of RCC_OCRDYR register */
#define RCC_OCRDYR_HSIRDY BIT(0)
#define RCC_OCRDYR_HSIDIVRDY BIT(2)
#define RCC_OCRDYR_CSIRDY BIT(4)
#define RCC_OCRDYR_HSERDY BIT(8)
/* Fields of RCC_DDRITFCR register */
#define RCC_DDRITFCR_DDRC1EN BIT(0)
#define RCC_DDRITFCR_DDRC1LPEN BIT(1)
#define RCC_DDRITFCR_DDRC2EN BIT(2)
#define RCC_DDRITFCR_DDRC2LPEN BIT(3)
#define RCC_DDRITFCR_DDRPHYCEN BIT(4)
#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5)
#define RCC_DDRITFCR_DDRCAPBEN BIT(6)
#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7)
#define RCC_DDRITFCR_AXIDCGEN BIT(8)
#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9)
#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10)
#define RCC_DDRITFCR_DDRCAPBRST BIT(14)
#define RCC_DDRITFCR_DDRCAXIRST BIT(15)
#define RCC_DDRITFCR_DDRCORERST BIT(16)
#define RCC_DDRITFCR_DPHYAPBRST BIT(17)
#define RCC_DDRITFCR_DPHYRST BIT(18)
#define RCC_DDRITFCR_DPHYCTLRST BIT(19)
#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
#define RCC_DDRITFCR_DDRCKMOD_SSR 0
#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20)
#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21)
#define RCC_DDRITFCR_GSKPCTRL BIT(24)
/* Fields of RCC_HSICFGR register */
#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
/* Used for RCC_MCO related operations */
#define RCC_MCOCFG_MCOON BIT(12)
#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
#define RCC_MCOCFG_MCODIV_SHIFT 4
#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
/* Fields of RCC_DBGCFGR register */
#define RCC_DBGCFGR_DBGCKEN BIT(8)
/* RCC register fields for reset reasons */
#define RCC_MP_RSTSCLRR_PORRSTF BIT(0)
#define RCC_MP_RSTSCLRR_BORRSTF BIT(1)
#define RCC_MP_RSTSCLRR_PADRSTF BIT(2)
#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3)
#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4)
#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6)
#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8)
#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9)
#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11)
#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12)
/* Global Reset Register */
#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
/* Clock Source Interrupt Flag Register */
#define RCC_MP_CIFR_MASK U(0x110F1F)
#define RCC_MP_CIFR_WKUPF BIT(20)
/* Stop Request Set Register */
#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
#define RCC_MP_SREQSETR_STPREQ_P1 BIT(1)
/* Stop Request Clear Register */
#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
#define RCC_MP_SREQCLRR_STPREQ_P1 BIT(1)
/* Values of RCC_UART24CKSELR register */
#define RCC_UART24CKSELR_HSI 0x00000002
/* Values of RCC_MP_APB1ENSETR register */
#define RCC_MP_APB1ENSETR_UART4EN BIT(16)
/* Values of RCC_MP_AHB4ENSETR register */
#define RCC_MP_AHB4ENSETR_GPIOGEN BIT(6)
#endif /* __STM32MP1_RCC_H__ */
include/drivers/st/stm32mp1_reset.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __STM32MP1_RESET_H__
#define __STM32MP1_RESET_H__
#include <stdint.h>
void stm32mp1_reset_assert(uint32_t reset_id);
void stm32mp1_reset_deassert(uint32_t reset_id);
#endif /* __STM32MP1_RESET_H__ */
include/drivers/st/stpmu1.h 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __STPMU1_H__
#define __STPMU1_H__
#include <stm32_i2c.h>
#include <utils_def.h>
#define TURN_ON_REG 0x1U
#define TURN_OFF_REG 0x2U
#define ICC_LDO_TURN_OFF_REG 0x3U
#define ICC_BUCK_TURN_OFF_REG 0x4U
#define RESET_STATUS_REG 0x5U
#define VERSION_STATUS_REG 0x6U
#define MAIN_CONTROL_REG 0x10U
#define PADS_PULL_REG 0x11U
#define BUCK_PULL_DOWN_REG 0x12U
#define LDO14_PULL_DOWN_REG 0x13U
#define LDO56_PULL_DOWN_REG 0x14U
#define VIN_CONTROL_REG 0x15U
#define PONKEY_TIMER_REG 0x16U
#define MASK_RANK_BUCK_REG 0x17U
#define MASK_RESET_BUCK_REG 0x18U
#define MASK_RANK_LDO_REG 0x19U
#define MASK_RESET_LDO_REG 0x1AU
#define WATCHDOG_CONTROL_REG 0x1BU
#define WATCHDOG_TIMER_REG 0x1CU
#define BUCK_ICC_TURNOFF_REG 0x1DU
#define LDO_ICC_TURNOFF_REG 0x1EU
#define BUCK_APM_CONTROL_REG 0x1FU
#define BUCK1_CONTROL_REG 0x20U
#define BUCK2_CONTROL_REG 0x21U
#define BUCK3_CONTROL_REG 0x22U
#define BUCK4_CONTROL_REG 0x23U
#define VREF_DDR_CONTROL_REG 0x24U
#define LDO1_CONTROL_REG 0x25U
#define LDO2_CONTROL_REG 0x26U
#define LDO3_CONTROL_REG 0x27U
#define LDO4_CONTROL_REG 0x28U
#define LDO5_CONTROL_REG 0x29U
#define LDO6_CONTROL_REG 0x2AU
#define BUCK1_PWRCTRL_REG 0x30U
#define BUCK2_PWRCTRL_REG 0x31U
#define BUCK3_PWRCTRL_REG 0x32U
#define BUCK4_PWRCTRL_REG 0x33U
#define VREF_DDR_PWRCTRL_REG 0x34U
#define LDO1_PWRCTRL_REG 0x35U
#define LDO2_PWRCTRL_REG 0x36U
#define LDO3_PWRCTRL_REG 0x37U
#define LDO4_PWRCTRL_REG 0x38U
#define LDO5_PWRCTRL_REG 0x39U
#define LDO6_PWRCTRL_REG 0x3AU
#define FREQUENCY_SPREADING_REG 0x3BU
#define USB_CONTROL_REG 0x40U
#define ITLATCH1_REG 0x50U
#define ITLATCH2_REG 0x51U
#define ITLATCH3_REG 0x52U
#define ITLATCH4_REG 0x53U
#define ITSETLATCH1_REG 0x60U
#define ITSETLATCH2_REG 0x61U
#define ITSETLATCH3_REG 0x62U
#define ITSETLATCH4_REG 0x63U
#define ITCLEARLATCH1_REG 0x70U
#define ITCLEARLATCH2_REG 0x71U
#define ITCLEARLATCH3_REG 0x72U
#define ITCLEARLATCH4_REG 0x73U
#define ITMASK1_REG 0x80U
#define ITMASK2_REG 0x81U
#define ITMASK3_REG 0x82U
#define ITMASK4_REG 0x83U
#define ITSETMASK1_REG 0x90U
#define ITSETMASK2_REG 0x91U
#define ITSETMASK3_REG 0x92U
#define ITSETMASK4_REG 0x93U
#define ITCLEARMASK1_REG 0xA0U
#define ITCLEARMASK2_REG 0xA1U
#define ITCLEARMASK3_REG 0xA2U
#define ITCLEARMASK4_REG 0xA3U
#define ITSOURCE1_REG 0xB0U
#define ITSOURCE2_REG 0xB1U
#define ITSOURCE3_REG 0xB2U
#define ITSOURCE4_REG 0xB3U
#define LDO_VOLTAGE_MASK 0x7CU
#define BUCK_VOLTAGE_MASK 0xFCU
#define LDO_BUCK_VOLTAGE_SHIFT 2
#define LDO_ENABLE_MASK 0x01U
#define BUCK_ENABLE_MASK 0x01U
#define BUCK_HPLP_ENABLE_MASK 0x02U
#define LDO_HPLP_ENABLE_MASK 0x02U
#define LDO_BUCK_HPLP_SHIFT 1
#define LDO_BUCK_RANK_MASK 0x01U
#define LDO_BUCK_RESET_MASK 0x01U
#define LDO_BUCK_PULL_DOWN_MASK 0x03U
/* Main PMIC Control Register (MAIN_CONTROL_REG) */
#define ICC_EVENT_ENABLED BIT(4)
#define PWRCTRL_POLARITY_HIGH BIT(3)
#define PWRCTRL_PIN_VALID BIT(2)
#define RESTART_REQUEST_ENABLED BIT(1)
#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
/* Main PMIC PADS Control Register (PADS_PULL_REG) */
#define WAKEUP_DETECTOR_DISABLED BIT(4)
#define PWRCTRL_PD_ACTIVE BIT(3)
#define PWRCTRL_PU_ACTIVE BIT(2)
#define WAKEUP_PD_ACTIVE BIT(1)
#define PONKEY_PU_ACTIVE BIT(0)
/* Main PMIC VINLOW Control Register (VIN_CONTROL_REGC DMSC) */
#define SWIN_DETECTOR_ENABLED BIT(7)
#define SWOUT_DETECTOR_ENABLED BIT(6)
#define VINLOW_HYST_MASK 0x3
#define VINLOW_HYST_SHIFT 4
#define VINLOW_THRESHOLD_MASK 0x7
#define VINLOW_THRESHOLD_SHIFT 1
#define VINLOW_ENABLED 0x01
#define VINLOW_CTRL_REG_MASK 0xFF
/* USB Control Register */
#define BOOST_OVP_DISABLED BIT(7)
#define VBUS_OTG_DETECTION_DISABLED BIT(6)
#define OCP_LIMIT_HIGH BIT(3)
#define SWIN_SWOUT_ENABLED BIT(2)
#define USBSW_OTG_SWITCH_ENABLED BIT(1)
int stpmu1_switch_off(void);
int stpmu1_register_read(uint8_t register_id, uint8_t *value);
int stpmu1_register_write(uint8_t register_id, uint8_t value);
int stpmu1_register_update(uint8_t register_id, uint8_t value, uint8_t mask);
int stpmu1_regulator_enable(const char *name);
int stpmu1_regulator_disable(const char *name);
uint8_t stpmu1_is_regulator_enabled(const char *name);
int stpmu1_regulator_voltage_set(const char *name, uint16_t millivolts);
void stpmu1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr);
#endif /* __STPMU1_H__ */
include/dt-bindings/clock/stm32mp1-clks.h 0 → 100644
View file @ d87d524e
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
#define _DT_BINDINGS_STM32MP1_CLKS_H_
/* OSCILLATOR clocks */
#define CK_HSE 0
#define CK_CSI 1
#define CK_LSI 2
#define CK_LSE 3
#define CK_HSI 4
#define CK_HSE_DIV2 5
/* Bus clocks */
#define TIM2 6
#define TIM3 7
#define TIM4 8
#define TIM5 9
#define TIM6 10
#define TIM7 11
#define TIM12 12
#define TIM13 13
#define TIM14 14
#define LPTIM1 15
#define SPI2 16
#define SPI3 17
#define USART2 18
#define USART3 19
#define UART4 20
#define UART5 21
#define UART7 22
#define UART8 23
#define I2C1 24
#define I2C2 25
#define I2C3 26
#define I2C5 27
#define SPDIF 28
#define CEC 29
#define DAC12 30
#define MDIO 31
#define TIM1 32
#define TIM8 33
#define TIM15 34
#define TIM16 35
#define TIM17 36
#define SPI1 37
#define SPI4 38
#define SPI5 39
#define USART6 40
#define SAI1 41
#define SAI2 42
#define SAI3 43
#define DFSDM 44
#define FDCAN 45
#define LPTIM2 46
#define LPTIM3 47
#define LPTIM4 48
#define LPTIM5 49
#define SAI4 50
#define SYSCFG 51
#define VREF 52
#define TMPSENS 53
#define PMBCTRL 54
#define HDP 55
#define LTDC 56
#define DSI 57
#define IWDG2 58
#define USBPHY 59
#define STGENRO 60
#define SPI6 61
#define I2C4 62
#define I2C6 63
#define USART1 64
#define RTCAPB 65
#define TZC1 66
#define TZPC 67
#define IWDG1 68
#define BSEC 69
#define STGEN 70
#define DMA1 71
#define DMA2 72
#define DMAMUX 73
#define ADC12 74
#define USBO 75
#define SDMMC3 76
#define DCMI 77
#define CRYP2 78
#define HASH2 79
#define RNG2 80
#define CRC2 81
#define HSEM 82
#define IPCC 83
#define GPIOA 84
#define GPIOB 85
#define GPIOC 86
#define GPIOD 87
#define GPIOE 88
#define GPIOF 89
#define GPIOG 90
#define GPIOH 91
#define GPIOI 92
#define GPIOJ 93
#define GPIOK 94
#define GPIOZ 95
#define CRYP1 96
#define HASH1 97
#define RNG1 98
#define BKPSRAM 99
#define MDMA 100
#define GPU 101
#define ETHCK 102
#define ETHTX 103
#define ETHRX 104
#define ETHMAC 105
#define FMC 106
#define QSPI 107
#define SDMMC1 108
#define SDMMC2 109
#define CRC1 110
#define USBH 111
#define ETHSTP 112
#define TZC2 113
/* Kernel clocks */
#define SDMMC1_K 118
#define SDMMC2_K 119
#define SDMMC3_K 120
#define FMC_K 121
#define QSPI_K 122
#define ETHCK_K 123
#define RNG1_K 124
#define RNG2_K 125
#define GPU_K 126
#define USBPHY_K 127
#define STGEN_K 128
#define SPDIF_K 129
#define SPI1_K 130
#define SPI2_K 131
#define SPI3_K 132
#define SPI4_K 133
#define SPI5_K 134
#define SPI6_K 135
#define CEC_K 136
#define I2C1_K 137
#define I2C2_K 138
#define I2C3_K 139
#define I2C4_K 140
#define I2C5_K 141
#define I2C6_K 142
#define LPTIM1_K 143
#define LPTIM2_K 144
#define LPTIM3_K 145
#define LPTIM4_K 146
#define LPTIM5_K 147
#define USART1_K 148
#define USART2_K 149
#define USART3_K 150
#define UART4_K 151
#define UART5_K 152
#define USART6_K 153
#define UART7_K 154
#define UART8_K 155
#define DFSDM_K 156
#define FDCAN_K 157
#define SAI1_K 158
#define SAI2_K 159
#define SAI3_K 160
#define SAI4_K 161
#define ADC12_K 162
#define DSI_K 163
#define DSI_PX 164
#define ADFSDM_K 165
#define USBO_K 166
#define LTDC_PX 167
#define DAC12_K 168
#define ETHPTP_K 169
/* PLL */
#define PLL1 176
#define PLL2 177
#define PLL3 178
#define PLL4 179
/* ODF */
#define PLL1_P 180
#define PLL1_Q 181
#define PLL1_R 182
#define PLL2_P 183
#define PLL2_Q 184
#define PLL2_R 185
#define PLL3_P 186
#define PLL3_Q 187
#define PLL3_R 188
#define PLL4_P 189
#define PLL4_Q 190
#define PLL4_R 191
/* AUX */
#define RTC 192
/* MCLK */
#define CK_PER 193
#define CK_MPU 194
#define CK_AXI 195
#define CK_MCU 196
/* Time base */
#define TIM2_K 197
#define TIM3_K 198
#define TIM4_K 199
#define TIM5_K 200
#define TIM6_K 201
#define TIM7_K 202
#define TIM12_K 203
#define TIM13_K 204
#define TIM14_K 205
#define TIM1_K 206
#define TIM8_K 207
#define TIM15_K 208
#define TIM16_K 209
#define TIM17_K 210
/* MCO clocks */
#define CK_MCO1 211
#define CK_MCO2 212
/* TRACE & DEBUG clocks */
#define CK_DBG 214
#define CK_TRACE 215
/* DDR */
#define DDRC1 220
#define DDRC1LP 221
#define DDRC2 222
#define DDRC2LP 223
#define DDRPHYC 224
#define DDRPHYCLP 225
#define DDRCAPB 226
#define DDRCAPBLP 227
#define AXIDCG 228
#define DDRPHYCAPB 229
#define DDRPHYCAPBLP 230
#define DDRPERFM 231
#define STM32MP1_LAST_CLK 232
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
include/dt-bindings/clock/stm32mp1-clksrc.h 0 → 100644
View file @ d87d524e
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
*/
#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
/* PLL output is enable when x=1, with x=p,q or r */
#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
/* st,clksrc: mandatory clock source */
#define CLK_MPU_HSI 0x00000200
#define CLK_MPU_HSE 0x00000201
#define CLK_MPU_PLL1P 0x00000202
#define CLK_MPU_PLL1P_DIV 0x00000203
#define CLK_AXI_HSI 0x00000240
#define CLK_AXI_HSE 0x00000241
#define CLK_AXI_PLL2P 0x00000242
#define CLK_MCU_HSI 0x00000480
#define CLK_MCU_HSE 0x00000481
#define CLK_MCU_CSI 0x00000482
#define CLK_MCU_PLL3P 0x00000483
#define CLK_PLL12_HSI 0x00000280
#define CLK_PLL12_HSE 0x00000281
#define CLK_PLL3_HSI 0x00008200
#define CLK_PLL3_HSE 0x00008201
#define CLK_PLL3_CSI 0x00008202
#define CLK_PLL4_HSI 0x00008240
#define CLK_PLL4_HSE 0x00008241
#define CLK_PLL4_CSI 0x00008242
#define CLK_PLL4_I2SCKIN 0x00008243
#define CLK_RTC_DISABLED 0x00001400
#define CLK_RTC_LSE 0x00001401
#define CLK_RTC_LSI 0x00001402
#define CLK_RTC_HSE 0x00001403
#define CLK_MCO1_HSI 0x00008000
#define CLK_MCO1_HSE 0x00008001
#define CLK_MCO1_CSI 0x00008002
#define CLK_MCO1_LSI 0x00008003
#define CLK_MCO1_LSE 0x00008004
#define CLK_MCO1_DISABLED 0x0000800F
#define CLK_MCO2_MPU 0x00008040
#define CLK_MCO2_AXI 0x00008041
#define CLK_MCO2_MCU 0x00008042
#define CLK_MCO2_PLL4P 0x00008043
#define CLK_MCO2_HSE 0x00008044
#define CLK_MCO2_HSI 0x00008045
#define CLK_MCO2_DISABLED 0x0000804F
/* st,pkcs: peripheral kernel clock source */
#define CLK_I2C12_PCLK1 0x00008C00
#define CLK_I2C12_PLL4R 0x00008C01
#define CLK_I2C12_HSI 0x00008C02
#define CLK_I2C12_CSI 0x00008C03
#define CLK_I2C12_DISABLED 0x00008C07
#define CLK_I2C35_PCLK1 0x00008C40
#define CLK_I2C35_PLL4R 0x00008C41
#define CLK_I2C35_HSI 0x00008C42
#define CLK_I2C35_CSI 0x00008C43
#define CLK_I2C35_DISABLED 0x00008C47
#define CLK_I2C46_PCLK5 0x00000C00
#define CLK_I2C46_PLL3Q 0x00000C01
#define CLK_I2C46_HSI 0x00000C02
#define CLK_I2C46_CSI 0x00000C03
#define CLK_I2C46_DISABLED 0x00000C07
#define CLK_SAI1_PLL4Q 0x00008C80
#define CLK_SAI1_PLL3Q 0x00008C81
#define CLK_SAI1_I2SCKIN 0x00008C82
#define CLK_SAI1_CKPER 0x00008C83
#define CLK_SAI1_PLL3R 0x00008C84
#define CLK_SAI1_DISABLED 0x00008C87
#define CLK_SAI2_PLL4Q 0x00008CC0
#define CLK_SAI2_PLL3Q 0x00008CC1
#define CLK_SAI2_I2SCKIN 0x00008CC2
#define CLK_SAI2_CKPER 0x00008CC3
#define CLK_SAI2_SPDIF 0x00008CC4
#define CLK_SAI2_PLL3R 0x00008CC5
#define CLK_SAI2_DISABLED 0x00008CC7
#define CLK_SAI3_PLL4Q 0x00008D00
#define CLK_SAI3_PLL3Q 0x00008D01
#define CLK_SAI3_I2SCKIN 0x00008D02
#define CLK_SAI3_CKPER 0x00008D03
#define CLK_SAI3_PLL3R 0x00008D04
#define CLK_SAI3_DISABLED 0x00008D07
#define CLK_SAI4_PLL4Q 0x00008D40
#define CLK_SAI4_PLL3Q 0x00008D41
#define CLK_SAI4_I2SCKIN 0x00008D42
#define CLK_SAI4_CKPER 0x00008D43
#define CLK_SAI4_PLL3R 0x00008D44
#define CLK_SAI4_DISABLED 0x00008D47
#define CLK_SPI2S1_PLL4P 0x00008D80
#define CLK_SPI2S1_PLL3Q 0x00008D81
#define CLK_SPI2S1_I2SCKIN 0x00008D82
#define CLK_SPI2S1_CKPER 0x00008D83
#define CLK_SPI2S1_PLL3R 0x00008D84
#define CLK_SPI2S1_DISABLED 0x00008D87
#define CLK_SPI2S23_PLL4P 0x00008DC0
#define CLK_SPI2S23_PLL3Q 0x00008DC1
#define CLK_SPI2S23_I2SCKIN 0x00008DC2
#define CLK_SPI2S23_CKPER 0x00008DC3
#define CLK_SPI2S23_PLL3R 0x00008DC4
#define CLK_SPI2S23_DISABLED 0x00008DC7
#define CLK_SPI45_PCLK2 0x00008E00
#define CLK_SPI45_PLL4Q 0x00008E01
#define CLK_SPI45_HSI 0x00008E02
#define CLK_SPI45_CSI 0x00008E03
#define CLK_SPI45_HSE 0x00008E04
#define CLK_SPI45_DISABLED 0x00008E07
#define CLK_SPI6_PCLK5 0x00000C40
#define CLK_SPI6_PLL4Q 0x00000C41
#define CLK_SPI6_HSI 0x00000C42
#define CLK_SPI6_CSI 0x00000C43
#define CLK_SPI6_HSE 0x00000C44
#define CLK_SPI6_PLL3Q 0x00000C45
#define CLK_SPI6_DISABLED 0x00000C47
#define CLK_UART6_PCLK2 0x00008E40
#define CLK_UART6_PLL4Q 0x00008E41
#define CLK_UART6_HSI 0x00008E42
#define CLK_UART6_CSI 0x00008E43
#define CLK_UART6_HSE 0x00008E44
#define CLK_UART6_DISABLED 0x00008E47
#define CLK_UART24_PCLK1 0x00008E80
#define CLK_UART24_PLL4Q 0x00008E81
#define CLK_UART24_HSI 0x00008E82
#define CLK_UART24_CSI 0x00008E83
#define CLK_UART24_HSE 0x00008E84
#define CLK_UART24_DISABLED 0x00008E87
#define CLK_UART35_PCLK1 0x00008EC0
#define CLK_UART35_PLL4Q 0x00008EC1
#define CLK_UART35_HSI 0x00008EC2
#define CLK_UART35_CSI 0x00008EC3
#define CLK_UART35_HSE 0x00008EC4
#define CLK_UART35_DISABLED 0x00008EC7
#define CLK_UART78_PCLK1 0x00008F00
#define CLK_UART78_PLL4Q 0x00008F01
#define CLK_UART78_HSI 0x00008F02
#define CLK_UART78_CSI 0x00008F03
#define CLK_UART78_HSE 0x00008F04
#define CLK_UART78_DISABLED 0x00008F07
#define CLK_UART1_PCLK5 0x00000C80
#define CLK_UART1_PLL3Q 0x00000C81
#define CLK_UART1_HSI 0x00000C82
#define CLK_UART1_CSI 0x00000C83
#define CLK_UART1_PLL4Q 0x00000C84
#define CLK_UART1_HSE 0x00000C85
#define CLK_UART1_DISABLED 0x00000C87
#define CLK_SDMMC12_HCLK6 0x00008F40
#define CLK_SDMMC12_PLL3R 0x00008F41
#define CLK_SDMMC12_PLL4P 0x00008F42
#define CLK_SDMMC12_HSI 0x00008F43
#define CLK_SDMMC12_DISABLED 0x00008F47
#define CLK_SDMMC3_HCLK2 0x00008F80
#define CLK_SDMMC3_PLL3R 0x00008F81
#define CLK_SDMMC3_PLL4P 0x00008F82
#define CLK_SDMMC3_HSI 0x00008F83
#define CLK_SDMMC3_DISABLED 0x00008F87
#define CLK_ETH_PLL4P 0x00008FC0
#define CLK_ETH_PLL3Q 0x00008FC1
#define CLK_ETH_DISABLED 0x00008FC3
#define CLK_QSPI_ACLK 0x00009000
#define CLK_QSPI_PLL3R 0x00009001
#define CLK_QSPI_PLL4P 0x00009002
#define CLK_QSPI_CKPER 0x00009003
#define CLK_FMC_ACLK 0x00009040
#define CLK_FMC_PLL3R 0x00009041
#define CLK_FMC_PLL4P 0x00009042
#define CLK_FMC_CKPER 0x00009043
#define CLK_FDCAN_HSE 0x000090C0
#define CLK_FDCAN_PLL3Q 0x000090C1
#define CLK_FDCAN_PLL4Q 0x000090C2
#define CLK_FDCAN_PLL4R 0x000090C3
#define CLK_SPDIF_PLL4P 0x00009140
#define CLK_SPDIF_PLL3Q 0x00009141
#define CLK_SPDIF_HSI 0x00009142
#define CLK_SPDIF_DISABLED 0x00009143
#define CLK_CEC_LSE 0x00009180
#define CLK_CEC_LSI 0x00009181
#define CLK_CEC_CSI_DIV122 0x00009182
#define CLK_CEC_DISABLED 0x00009183
#define CLK_USBPHY_HSE 0x000091C0
#define CLK_USBPHY_PLL4R 0x000091C1
#define CLK_USBPHY_HSE_DIV2 0x000091C2
#define CLK_USBPHY_DISABLED 0x000091C3
#define CLK_USBO_PLL4R 0x800091C0
#define CLK_USBO_USBPHY 0x800091C1
#define CLK_RNG1_CSI 0x00000CC0
#define CLK_RNG1_PLL4R 0x00000CC1
#define CLK_RNG1_LSE 0x00000CC2
#define CLK_RNG1_LSI 0x00000CC3
#define CLK_RNG2_CSI 0x00009200
#define CLK_RNG2_PLL4R 0x00009201
#define CLK_RNG2_LSE 0x00009202
#define CLK_RNG2_LSI 0x00009203
#define CLK_CKPER_HSI 0x00000D00
#define CLK_CKPER_CSI 0x00000D01
#define CLK_CKPER_HSE 0x00000D02
#define CLK_CKPER_DISABLED 0x00000D03
#define CLK_STGEN_HSI 0x00000D40
#define CLK_STGEN_HSE 0x00000D41
#define CLK_STGEN_DISABLED 0x00000D43
#define CLK_DSI_DSIPLL 0x00009240
#define CLK_DSI_PLL4P 0x00009241
#define CLK_ADC_PLL4R 0x00009280
#define CLK_ADC_CKPER 0x00009281
#define CLK_ADC_PLL3Q 0x00009282
#define CLK_ADC_DISABLED 0x00009283
#define CLK_LPTIM45_PCLK3 0x000092C0
#define CLK_LPTIM45_PLL4P 0x000092C1
#define CLK_LPTIM45_PLL3Q 0x000092C2
#define CLK_LPTIM45_LSE 0x000092C3
#define CLK_LPTIM45_LSI 0x000092C4
#define CLK_LPTIM45_CKPER 0x000092C5
#define CLK_LPTIM45_DISABLED 0x000092C7
#define CLK_LPTIM23_PCLK3 0x00009300
#define CLK_LPTIM23_PLL4Q 0x00009301
#define CLK_LPTIM23_CKPER 0x00009302
#define CLK_LPTIM23_LSE 0x00009303
#define CLK_LPTIM23_LSI 0x00009304
#define CLK_LPTIM23_DISABLED 0x00009307
#define CLK_LPTIM1_PCLK1 0x00009340
#define CLK_LPTIM1_PLL4P 0x00009341
#define CLK_LPTIM1_PLL3Q 0x00009342
#define CLK_LPTIM1_LSE 0x00009343
#define CLK_LPTIM1_LSI 0x00009344
#define CLK_LPTIM1_CKPER 0x00009345
#define CLK_LPTIM1_DISABLED 0x00009347
/* define for st,pll /csg */
#define SSCG_MODE_CENTER_SPREAD 0
#define SSCG_MODE_DOWN_SPREAD 1
/* define for st,drive */
#define LSEDRV_LOWEST 0
#define LSEDRV_MEDIUM_LOW 1
#define LSEDRV_MEDIUM_HIGH 2
#define LSEDRV_HIGHEST 3
#endif
include/dt-bindings/pinctrl/stm32-pinfunc.h 0 → 100644
View file @ d87d524e
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Torgue Alexandre <alexandre.torgue@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32_PINFUNC_H
#define _DT_BINDINGS_STM32_PINFUNC_H
/* define PIN modes */
#define GPIO 0x0
#define AF0 0x1
#define AF1 0x2
#define AF2 0x3
#define AF3 0x4
#define AF4 0x5
#define AF5 0x6
#define AF6 0x7
#define AF7 0x8
#define AF8 0x9
#define AF9 0xa
#define AF10 0xb
#define AF11 0xc
#define AF12 0xd
#define AF13 0xe
#define AF14 0xf
#define AF15 0x10
#define ANALOG 0x11
/* define Pins number*/
#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
include/dt-bindings/reset/stm32mp1-resets.h 0 → 100644
View file @ d87d524e
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
#define _DT_BINDINGS_STM32MP1_RESET_H_
#define LTDC_R 3072
#define DSI_R 3076
#define DDRPERFM_R 3080
#define USBPHY_R 3088
#define SPI6_R 3136
#define I2C4_R 3138
#define I2C6_R 3139
#define USART1_R 3140
#define STGEN_R 3156
#define GPIOZ_R 3200
#define CRYP1_R 3204
#define HASH1_R 3205
#define RNG1_R 3206
#define AXIM_R 3216
#define GPU_R 3269
#define ETHMAC_R 3274
#define FMC_R 3276
#define QSPI_R 3278
#define SDMMC1_R 3280
#define SDMMC2_R 3281
#define CRC1_R 3284
#define USBH_R 3288
#define MDMA_R 3328
#define MCU_R 8225
#define TIM2_R 19456
#define TIM3_R 19457
#define TIM4_R 19458
#define TIM5_R 19459
#define TIM6_R 19460
#define TIM7_R 19461
#define TIM12_R 16462
#define TIM13_R 16463
#define TIM14_R 16464
#define LPTIM1_R 19465
#define SPI2_R 19467
#define SPI3_R 19468
#define USART2_R 19470
#define USART3_R 19471
#define UART4_R 19472
#define UART5_R 19473
#define UART7_R 19474
#define UART8_R 19475
#define I2C1_R 19477
#define I2C2_R 19478
#define I2C3_R 19479
#define I2C5_R 19480
#define SPDIF_R 19482
#define CEC_R 19483
#define DAC12_R 19485
#define MDIO_R 19847
#define TIM1_R 19520
#define TIM8_R 19521
#define TIM15_R 19522
#define TIM16_R 19523
#define TIM17_R 19524
#define SPI1_R 19528
#define SPI4_R 19529
#define SPI5_R 19530
#define USART6_R 19533
#define SAI1_R 19536
#define SAI2_R 19537
#define SAI3_R 19538
#define DFSDM_R 19540
#define FDCAN_R 19544
#define LPTIM2_R 19584
#define LPTIM3_R 19585
#define LPTIM4_R 19586
#define LPTIM5_R 19587
#define SAI4_R 19592
#define SYSCFG_R 19595
#define VREF_R 19597
#define TMPSENS_R 19600
#define PMBCTRL_R 19601
#define DMA1_R 19648
#define DMA2_R 19649
#define DMAMUX_R 19650
#define ADC12_R 19653
#define USBO_R 19656
#define SDMMC3_R 19664
#define CAMITF_R 19712
#define CRYP2_R 19716
#define HASH2_R 19717
#define RNG2_R 19718
#define CRC2_R 19719
#define HSEM_R 19723
#define MBOX_R 19724
#define GPIOA_R 19776
#define GPIOB_R 19777
#define GPIOC_R 19778
#define GPIOD_R 19779
#define GPIOE_R 19780
#define GPIOF_R 19781
#define GPIOG_R 19782
#define GPIOH_R 19783
#define GPIOI_R 19784
#define GPIOJ_R 19785
#define GPIOK_R 19786
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
maintainers.rst
View file @ d87d524e
...@@ -125,6 +125,16 @@ RockChip platform port ...@@ -125,6 +125,16 @@ RockChip platform port
:G: `rockchip-linux`_ :G: `rockchip-linux`_
:F: plat/rockchip/ :F: plat/rockchip/
STM32MP1 platform port
----------------------
:M: Yann Gautier <yann.gautier@st.com>
:G: `Yann-lms`_
:F: docs/plat/stm32mp1.rst
:F: fdts/stm32\*
:F: include/dt-bindings/\*/stm32\*
:F: plat/st/
:F: tools/stm32image/
Synquacer platform port Synquacer platform port
----------------------- -----------------------
:M: Sumit Garg <sumit.garg@linaro.org> :M: Sumit Garg <sumit.garg@linaro.org>
...@@ -184,3 +194,4 @@ Xilinx platform port ...@@ -184,3 +194,4 @@ Xilinx platform port
.. _soby-mathew: https://github.com/soby-mathew .. _soby-mathew: https://github.com/soby-mathew
.. _TonyXie06: https://github.com/TonyXie06 .. _TonyXie06: https://github.com/TonyXie06
.. _vwadekar: https://github.com/vwadekar .. _vwadekar: https://github.com/vwadekar
.. _Yann-lms: https://github.com/Yann-lms
plat/st/stm32mp1/bl2_io_storage.c 0 → 100644
View file @ d87d524e
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <assert.h>
#include <boot_api.h>
#include <debug.h>
#include <io_driver.h>
#include <io_dummy.h>
#include <io_storage.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
#include <stm32mp1_private.h>
#include <stm32mp1_rcc.h>
#include <string.h>
#include <utils.h>
/* IO devices */
static const io_dev_connector_t *dummy_dev_con;
static uintptr_t dummy_dev_handle;
static uintptr_t dummy_dev_spec;
static const io_block_spec_t bl32_block_spec = {
.offset = BL32_BASE,
.length = STM32MP1_BL32_SIZE
};
static const io_block_spec_t bl2_block_spec = {
.offset = BL2_BASE,
.length = STM32MP1_BL2_SIZE,
};
static int open_dummy(const uintptr_t spec);
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int (*check)(const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
[BL2_IMAGE_ID] = {
.dev_handle = &dummy_dev_handle,
.image_spec = (uintptr_t)&bl2_block_spec,
.check = open_dummy
},
[BL32_IMAGE_ID] = {
.dev_handle = &dummy_dev_handle,
.image_spec = (uintptr_t)&bl32_block_spec,
.check = open_dummy
},
};
static int open_dummy(const uintptr_t spec)
{
return io_dev_init(dummy_dev_handle, 0);
}
static void print_boot_device(boot_api_context_t *boot_context)
{
switch (boot_context->boot_interface_selected) {
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
INFO("Using SDMMC\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
INFO("Using EMMC\n");
break;
default:
ERROR("Boot interface not found\n");
panic();
break;
}
if (boot_context->boot_interface_instance != 0U) {
INFO(" Instance %d\n", boot_context->boot_interface_instance);
}
}
static void print_reset_reason(void)
{
uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
if (rstsr == 0U) {
WARN("Reset reason unknown\n");
return;
}
INFO("Reset reason (0x%x):\n", rstsr);
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
INFO("System exits from STANDBY\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
INFO("MPU exits from CSTANDBY\n");
return;
}
}
if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
INFO(" Power-on Reset (rst_por)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
INFO(" Brownout Reset (rst_bor)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
INFO(" System reset generated by MPU (MPSYSRST)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
INFO(" Reset due to a clock failure on HSE\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
INFO(" IWDG1 Reset (rst_iwdg1)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
INFO(" IWDG2 Reset (rst_iwdg2)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
INFO(" Pad Reset from NRST\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
INFO(" Reset due to a failure of VDD_CORE\n");
return;
}
ERROR(" Unidentified reset reason\n");
}
void stm32mp1_io_setup(void)
{
int io_result __unused;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
print_reset_reason();
print_boot_device(boot_context);
if ((boot_context->boot_partition_used_toboot == 1U) ||
(boot_context->boot_partition_used_toboot == 2U)) {
INFO("Boot used partition fsbl%d\n",
boot_context->boot_partition_used_toboot);
}
io_result = register_io_dev_dummy(&dummy_dev_con);
assert(io_result == 0);
io_result = io_dev_open(dummy_dev_con, dummy_dev_spec,
&dummy_dev_handle);
assert(io_result == 0);
}
/*
* Return an IO device handle and specification which can be used to access
* an image. Use this to enforce platform load policy.
*/
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
int rc;
const struct plat_io_policy *policy;
assert(image_id < ARRAY_SIZE(policies));
policy = &policies[image_id];
rc = policy->check(policy->image_spec);
if (rc == 0) {
*image_spec = policy->image_spec;
*dev_handle = *(policy->dev_handle);
}
return rc;
}
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