diff --git a/plat/rockchip/common/plat_pm.c b/plat/rockchip/common/plat_pm.c
old mode 100755
new mode 100644
index 3c2c79a6cb4fd2ea646339b33fe15c9dddb559fa..d28100d9c1354e07ed8dc5ad62a645d21459d8a7
--- a/plat/rockchip/common/plat_pm.c
+++ b/plat/rockchip/common/plat_pm.c
@@ -283,9 +283,10 @@ void rockchip_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
rockchip_ops->cores_pwr_dm_resume();
/*
* Program the gic per-cpu distributor or re-distributor interface.
- * For sys power domain operation, resuming of the gic needs to operate in
- * rockchip_ops->sys_pwr_dm_resume, according to the sys power mode implements.
- */
+ * For sys power domain operation, resuming of the gic needs to operate
+ * in rockchip_ops->sys_pwr_dm_resume, according to the sys power mode
+ * implements.
+ */
plat_rockchip_gic_cpuif_enable();
comm_finish:
diff --git a/plat/rockchip/rk3399/drivers/dram/dram.c b/plat/rockchip/rk3399/drivers/dram/dram.c
index ddae84d340887139bdbd6085c3303cd2d5508f66..94aa0766da10cfbe22dee893b01fb3f6d4f6b40a 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram.c
+++ b/plat/rockchip/rk3399/drivers/dram/dram.c
@@ -2147,7 +2147,7 @@ static int to_get_clk_index(unsigned int mhz)
{
int pll_cnt, i;
- pll_cnt = sizeof(dpll_rates_table) / sizeof(struct pll_div);
+ pll_cnt = ARRAY_SIZE(dpll_rates_table);
/* Assumming rate_table is in descending order */
for (i = 0; i < pll_cnt; i++) {
@@ -2155,6 +2155,10 @@ static int to_get_clk_index(unsigned int mhz)
break;
}
+ /* if mhz lower than lowest frequency in table, use lowest frequency */
+ if (i == pll_cnt)
+ i = pll_cnt - 1;
+
return i;
}
@@ -2174,7 +2178,7 @@ uint32_t rkclk_prepare_pll_timing(unsigned int mhz)
return (24 * fbdiv) / refdiv / postdiv1 / postdiv2;
}
-uint64_t ddr_get_rate(void)
+uint32_t ddr_get_rate(void)
{
uint32_t refdiv, postdiv1, fbdiv, postdiv2;
@@ -2464,7 +2468,6 @@ static uint32_t prepare_ddr_timing(uint32_t mhz)
* target freq.
*/
dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing);
-
gen_rk3399_ctl_params(&rk3399_dram_status.timing_config,
&dram_timing, index);
gen_rk3399_pi_params(&rk3399_dram_status.timing_config,
@@ -2494,7 +2497,7 @@ void print_dram_status_info(void)
tf_printf("%u\n", p[i]);
}
-uint64_t ddr_set_rate(uint64_t hz)
+uint32_t ddr_set_rate(uint32_t hz)
{
uint32_t low_power, index;
uint32_t mhz = hz / (1000 * 1000);
@@ -2503,13 +2506,13 @@ uint64_t ddr_set_rate(uint64_t hz)
rk3399_dram_status.index_freq[rk3399_dram_status.current_index])
goto out;
+ index = to_get_clk_index(mhz);
+ mhz = dpll_rates_table[index].mhz;
+
low_power = exit_low_power();
index = prepare_ddr_timing(mhz);
- if (index > 1) {
- /* set timing error, quit */
- mhz = 0;
+ if (index > 1)
goto out;
- }
dcf_start(mhz, index);
wait_dcf_done();
@@ -2526,7 +2529,7 @@ out:
return mhz;
}
-uint64_t ddr_round_rate(uint64_t hz)
+uint32_t ddr_round_rate(uint32_t hz)
{
int index;
uint32_t mhz = hz / (1000 * 1000);
@@ -2536,7 +2539,7 @@ uint64_t ddr_round_rate(uint64_t hz)
return dpll_rates_table[index].mhz * 1000 * 1000;
}
-uint64_t dts_timing_receive(uint64_t timing, uint64_t index)
+uint32_t dts_timing_receive(uint32_t timing, uint32_t index)
{
uint32_t *p = (uint32_t *) &dts_parameter;
static uint32_t receive_nums;
diff --git a/plat/rockchip/rk3399/drivers/dram/dram.h b/plat/rockchip/rk3399/drivers/dram/dram.h
index 62c5170a0114f878db3975c68b47dec089962334..4f9907049d02a77a9a951847b26ad2020b327f59 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram.h
+++ b/plat/rockchip/rk3399/drivers/dram/dram.h
@@ -321,9 +321,9 @@ struct drv_odt_lp_config {
#define DDR_RESTORE_SP(save_sp) ddr_save_sp(save_sp)
void ddr_init(void);
-uint64_t ddr_set_rate(uint64_t hz);
-uint64_t ddr_round_rate(uint64_t hz);
-uint64_t ddr_get_rate(void);
+uint32_t ddr_set_rate(uint32_t hz);
+uint32_t ddr_round_rate(uint32_t hz);
+uint32_t ddr_get_rate(void);
void clr_dcf_irq(void);
-uint64_t dts_timing_receive(uint64_t timing, uint64_t index);
+uint32_t dts_timing_receive(uint32_t timing, uint32_t index);
#endif
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
old mode 100755
new mode 100644
diff --git a/plat/rockchip/rk3399/plat_sip_calls.c b/plat/rockchip/rk3399/plat_sip_calls.c
index 6069be2aacffbab9dbf83763592ad28a6d0bd6b4..a20ee2d8951bdba960c5f0022eb626d8079cc4dd 100644
--- a/plat/rockchip/rk3399/plat_sip_calls.c
+++ b/plat/rockchip/rk3399/plat_sip_calls.c
@@ -31,33 +31,33 @@
#include <runtime_svc.h>
#include <dram.h>
-#define RK_SIP_DDR_CFG64 0x82000008
-#define CONFIG_DRAM_INIT 0x00
-#define CONFIG_DRAM_SET_RATE 0x01
-#define CONFIG_DRAM_ROUND_RATE 0x02
-#define CONFIG_DRAM_SET_AT_SR 0x03
-#define CONFIG_DRAM_GET_BW 0x04
-#define CONFIG_DRAM_GET_RATE 0x05
-#define CONFIG_DRAM_CLR_IRQ 0x06
-#define CONFIG_DRAM_SET_PARAM 0x07
+#define RK_SIP_DDR_CFG 0x82000008
+#define DRAM_INIT 0x00
+#define DRAM_SET_RATE 0x01
+#define DRAM_ROUND_RATE 0x02
+#define DRAM_SET_AT_SR 0x03
+#define DRAM_GET_BW 0x04
+#define DRAM_GET_RATE 0x05
+#define DRAM_CLR_IRQ 0x06
+#define DRAM_SET_PARAM 0x07
-uint64_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id)
+uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id)
{
switch (id) {
- case CONFIG_DRAM_INIT:
+ case DRAM_INIT:
ddr_init();
break;
- case CONFIG_DRAM_SET_RATE:
- return ddr_set_rate(arg0);
- case CONFIG_DRAM_ROUND_RATE:
- return ddr_round_rate(arg0);
- case CONFIG_DRAM_GET_RATE:
+ case DRAM_SET_RATE:
+ return ddr_set_rate((uint32_t)arg0);
+ case DRAM_ROUND_RATE:
+ return ddr_round_rate((uint32_t)arg0);
+ case DRAM_GET_RATE:
return ddr_get_rate();
- case CONFIG_DRAM_CLR_IRQ:
+ case DRAM_CLR_IRQ:
clr_dcf_irq();
break;
- case CONFIG_DRAM_SET_PARAM:
- dts_timing_receive(arg0, arg1);
+ case DRAM_SET_PARAM:
+ dts_timing_receive((uint32_t)arg0, (uint32_t)arg1);
break;
default:
break;
@@ -76,7 +76,7 @@ uint64_t rockchip_plat_sip_handler(uint32_t smc_fid,
uint64_t flags)
{
switch (smc_fid) {
- case RK_SIP_DDR_CFG64:
+ case RK_SIP_DDR_CFG:
SMC_RET1(handle, ddr_smc_handler(x1, x2, x3));
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);